src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57
  58 typedef GLuint uint32_t;
  59 typedef GLubyte uint8_t;
  60
  61   /* We should probably change types within vertex_shader
  62       and pixel_shader structure later on */
  63 #define CARD32 GLuint
  64 #include "vertex_shader.h"
  65 #include "pixel_shader.h"
  66 #undef CARD32
  67
  68 static __inline__ uint32_t r300PackFloat32(float fl)
  69 {
  70         union { float fl; uint32_t u; } u;
  71
  72         u.fl = fl;
  73         return u.u;
  74 }
  75
  76
  77 /************ DMA BUFFERS **************/
  78
  79 /* Need refcounting on dma buffers:
  80  */
  81 struct r300_dma_buffer {
  82         int refcount;           /* the number of retained regions in buf */
  83         drmBufPtr buf;
  84 };
  85
  86 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
  87                         (rvb)->address - rmesa->dma.buf0_address +      \
  88                         (rvb)->start)
  89
  90 /* A retained region, eg vertices for indexed vertices.
  91  */
  92 struct r300_dma_region {
  93         struct r300_dma_buffer *buf;
  94         char *address;          /* == buf->address */
  95         int start, end, ptr;    /* offsets from start of buf */
  96         int aos_start;
  97         int aos_stride;
  98         int aos_size;
  99 };
 100
 101 struct r300_dma {
 102         /* Active dma region.  Allocations for vertices and retained
 103          * regions come from here.  Also used for emitting random vertices,
 104          * these may be flushed by calling flush_current();
 105          */
 106         struct r300_dma_region current;
 107
 108         void (*flush) (r300ContextPtr);
 109
 110         char *buf0_address;     /* start of buf[0], for index calcs */
 111         GLuint nr_released_bufs;        /* flush after so many buffers released */
 112 };
 113
 114        /* Texture related */
 115
 116 #define TEX_0   0x1
 117 #define TEX_1   0x2
 118 #define TEX_2   0x4
 119 #define TEX_3   0x8
 120 #define TEX_4   0x10
 121 #define TEX_5   0x20
 122 #define TEX_6   0x40
 123 #define TEX_7   0x80
 124 #define TEX_ALL 0xff
 125
 126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 127
 128 /* Texture object in locally shared texture space.
 129  */
 130 struct r300_tex_obj {
 131         driTextureObject base;
 132
 133         GLuint bufAddr;         /* Offset to start of locally
 134                                    shared texture block */
 135
 136         GLuint dirty_state;     /* Flags (1 per texunit) for
 137                                    whether or not this texobj
 138                                    has dirty hardware state
 139                                    (pp_*) that needs to be
 140                                    brought into the
 141                                    texunit. */
 142
 143         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 144         /* Six, for the cube faces */
 145
 146
 147         /* hardware register values */
 148         /* Note that R200 has 8 registers per texture and R300 only 7 */
 149         GLuint filter;
 150         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 151         GLuint size;    /* npot only */
 152         GLuint format;
 153         GLuint offset;  /* Image location in texmem.
 154                                    All cube faces follow. */
 155         GLuint unknown4;
 156         GLuint unknown5;
 157         /* end hardware registers */
 158
 159         /* registers computed by r200 code - keep them here to
 160            compare against what is actually written.
 161
 162            to be removed later.. */
 163         GLuint pp_border_color;
 164         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 165         GLuint format_x;
 166
 167
 168         GLboolean border_fallback;
 169 };
 170
 171 struct r300_texture_env_state {
 172         r300TexObjPtr texobj;
 173         GLenum format;
 174         GLenum envMode;
 175 };
 176
 177 #define R300_MAX_TEXTURE_UNITS 8
 178
 179 struct r300_texture_state {
 180         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 181         int tc_count; /* number of incoming texture coordinates from VAP */
 182 };
 183
 184 /**
 185  * A block of hardware state.
 186  *
 187  * When check returns non-zero, the returned number of dwords must be
 188  * copied verbatim into the command buffer in order to update a state atom
 189  * when it is dirty.
 190  */
 191 struct r300_state_atom {
 192         struct r300_state_atom *next, *prev;
 193         const char* name;       /* for debug */
 194         int cmd_size;           /* maximum size in dwords */
 195         GLuint idx;             /* index in an array (e.g. textures) */
 196         uint32_t* cmd;
 197         GLboolean dirty;
 198
 199         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 200 };
 201
 202
 203 #define R300_VPT_CMD_0          0
 204 #define R300_VPT_XSCALE         1
 205 #define R300_VPT_XOFFSET        2
 206 #define R300_VPT_YSCALE         3
 207 #define R300_VPT_YOFFSET        4
 208 #define R300_VPT_ZSCALE         5
 209 #define R300_VPT_ZOFFSET        6
 210 #define R300_VPT_CMDSIZE        7
 211
 212 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 213 #define R300_VIR_CNTL_0         1
 214 #define R300_VIR_CNTL_1         2
 215 #define R300_VIR_CNTL_2         3
 216 #define R300_VIR_CNTL_3         4
 217 #define R300_VIR_CNTL_4         5
 218 #define R300_VIR_CNTL_5         6
 219 #define R300_VIR_CNTL_6         7
 220 #define R300_VIR_CNTL_7         8
 221 #define R300_VIR_CMDSIZE        9
 222
 223 #define R300_VIC_CMD_0          0
 224 #define R300_VIC_CNTL_0         1
 225 #define R300_VIC_CNTL_1         2
 226 #define R300_VIC_CMDSIZE        3
 227
 228 #define R300_VOF_CMD_0          0
 229 #define R300_VOF_CNTL_0         1
 230 #define R300_VOF_CNTL_1         2
 231 #define R300_VOF_CMDSIZE        3
 232
 233
 234 #define R300_PVS_CMD_0          0
 235 #define R300_PVS_CNTL_1         1
 236 #define R300_PVS_CNTL_2         2
 237 #define R300_PVS_CNTL_3         3
 238 #define R300_PVS_CMDSIZE        4
 239
 240 #define R300_GB_MISC_CMD_0              0
 241 #define R300_GB_MISC_MSPOS_0            1
 242 #define R300_GB_MISC_MSPOS_1            2
 243 #define R300_GB_MISC_TILE_CONFIG        3
 244 #define R300_GB_MISC_SELECT             4
 245 #define R300_GB_MISC_AA_CONFIG          5
 246 #define R300_GB_MISC_CMDSIZE            6
 247
 248 #define R300_TXE_CMD_0          0
 249 #define R300_TXE_ENABLE         1
 250 #define R300_TXE_CMDSIZE        2
 251
 252 #define R300_PS_CMD_0           0
 253 #define R300_PS_POINTSIZE       1
 254 #define R300_PS_CMDSIZE         2
 255
 256 #define R300_CUL_CMD_0          0
 257 #define R300_CUL_CULL           1
 258 #define R300_CUL_CMDSIZE        2
 259
 260 #define R300_RC_CMD_0           0
 261 #define R300_RC_CNTL_0          1
 262 #define R300_RC_CNTL_1          2
 263 #define R300_RC_CMDSIZE         3
 264
 265 #define R300_RI_CMD_0           0
 266 #define R300_RI_INTERP_0        1
 267 #define R300_RI_INTERP_1        2
 268 #define R300_RI_INTERP_2        3
 269 #define R300_RI_INTERP_3        4
 270 #define R300_RI_INTERP_4        5
 271 #define R300_RI_INTERP_5        6
 272 #define R300_RI_INTERP_6        7
 273 #define R300_RI_INTERP_7        8
 274 #define R300_RI_CMDSIZE         9
 275
 276 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 277 #define R300_RR_ROUTE_0         1
 278 #define R300_RR_ROUTE_1         2
 279 #define R300_RR_ROUTE_2         3
 280 #define R300_RR_ROUTE_3         4
 281 #define R300_RR_ROUTE_4         5
 282 #define R300_RR_ROUTE_5         6
 283 #define R300_RR_ROUTE_6         7
 284 #define R300_RR_ROUTE_7         8
 285 #define R300_RR_CMDSIZE         9
 286
 287 #define R300_FP_CMD_0           0
 288 #define R300_FP_CNTL0           1
 289 #define R300_FP_CNTL1           2
 290 #define R300_FP_CNTL2           3
 291 #define R300_FP_CMD_1           4
 292 #define R300_FP_NODE0           5
 293 #define R300_FP_NODE1           6
 294 #define R300_FP_NODE2           7
 295 #define R300_FP_NODE3           8
 296 #define R300_FP_CMDSIZE         9
 297
 298 #define R300_FPT_CMD_0          0
 299 #define R300_FPT_INSTR_0        1
 300 #define R300_FPT_CMDSIZE        65
 301
 302 #define R300_FPI_CMD_0          0
 303 #define R300_FPI_INSTR_0        1
 304 #define R300_FPI_CMDSIZE        65
 305
 306 #define R300_FPP_CMD_0          0
 307 #define R300_FPP_PARAM_0        1
 308 #define R300_FPP_CMDSIZE        (32*4+1)
 309
 310 #define R300_AT_CMD_0           0
 311 #define R300_AT_ALPHA_TEST      1
 312 #define R300_AT_CMDSIZE         2
 313
 314 #define R300_BLD_CMD_0          0
 315 #define R300_BLD_CBLEND         1
 316 #define R300_BLD_ABLEND         2
 317 #define R300_BLD_CMDSIZE        3
 318
 319 #define R300_CMK_CMD_0          0
 320 #define R300_CMK_COLORMASK      1
 321 #define R300_CMK_CMDSIZE        2
 322
 323 #define R300_CB_CMD_0           0
 324 #define R300_CB_OFFSET          1
 325 #define R300_CB_CMD_1           2
 326 #define R300_CB_PITCH           3
 327 #define R300_CB_CMDSIZE         4
 328
 329 #define R300_ZC_CMD_0           0
 330 #define R300_ZC_CNTL_0          1
 331 #define R300_ZC_CNTL_1          2
 332 #define R300_ZC_CMDSIZE         3
 333
 334 #define R300_ZB_CMD_0           0
 335 #define R300_ZB_OFFSET          1
 336 #define R300_ZB_PITCH           2
 337 #define R300_ZB_CMDSIZE         3
 338
 339 #define R300_VPI_CMD_0          0
 340 #define R300_VPI_INSTR_0        1
 341 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 342
 343 #define R300_VPP_CMD_0          0
 344 #define R300_VPP_PARAM_0        1
 345 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 346
 347 #define R300_VPS_CMD_0          0
 348 #define R300_VPS_ZERO_0         1
 349 #define R300_VPS_ZERO_1         2
 350 #define R300_VPS_POINTSIZE      3
 351 #define R300_VPS_ZERO_3         4
 352 #define R300_VPS_CMDSIZE        5
 353
 354         /* the layout is common for all fields inside tex */
 355 #define R300_TEX_CMD_0          0
 356 #define R300_TEX_VALUE_0        1
 357 /* We don't really use this, instead specify mtu+1 dynamically
 358 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 359 */
 360
 361 /**
 362  * Cache for hardware register state.
 363  */
 364 struct r300_hw_state {
 365         struct r300_state_atom atomlist;
 366
 367         GLboolean       is_dirty;
 368         GLboolean       all_dirty;
 369         int             max_state_size; /* in dwords */
 370
 371         struct r300_state_atom vpt;     /* viewport (1D98) */
 372         struct r300_state_atom unk2080; /* (2080) */
 373         struct r300_state_atom vte;     /* (20B0) */
 374         struct r300_state_atom unk2134; /* (2134) */
 375         struct r300_state_atom unk2140; /* (2140) */
 376         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 377         struct r300_state_atom vic;     /* vap input control (2180) */
 378         struct r300_state_atom unk21DC; /* (21DC) */
 379         struct r300_state_atom unk221C; /* (221C) */
 380         struct r300_state_atom unk2220; /* (2220) */
 381         struct r300_state_atom unk2288; /* (2288) */
 382         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 383         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 384         struct r300_state_atom gb_enable; /* (4008) */
 385         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 386         struct r300_state_atom unk4200; /* (4200) */
 387         struct r300_state_atom unk4214; /* (4214) */
 388         struct r300_state_atom ps;      /* pointsize (421C) */
 389         struct r300_state_atom unk4230; /* (4230) */
 390         struct r300_state_atom unk4260; /* (4260) */
 391         struct r300_state_atom unk4274; /* (4274) */
 392         struct r300_state_atom unk4288; /* (4288) */
 393         struct r300_state_atom unk42A0; /* (42A0) */
 394         struct r300_state_atom unk42B4; /* (42B4) */
 395         struct r300_state_atom cul;     /* cull cntl (42B8) */
 396         struct r300_state_atom unk42C0; /* (42C0) */
 397         struct r300_state_atom rc;      /* rs control (4300) */
 398         struct r300_state_atom ri;      /* rs interpolators (4310) */
 399         struct r300_state_atom rr;      /* rs route (4330) */
 400         struct r300_state_atom unk43A4; /* (43A4) */
 401         struct r300_state_atom unk43E8; /* (43E8) */
 402         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 403         struct r300_state_atom fpt;     /* texi - (4620) */
 404         struct r300_state_atom unk46A4; /* (46A4) */
 405         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 406         struct r300_state_atom unk4BC0; /* (4BC0) */
 407         struct r300_state_atom unk4BC8; /* (4BC8) */
 408         struct r300_state_atom at;      /* alpha test (4BD4) */
 409         struct r300_state_atom unk4BD8; /* (4BD8) */
 410         struct r300_state_atom fpp;     /* 0x4C00 and following */
 411         struct r300_state_atom unk4E00; /* (4E00) */
 412         struct r300_state_atom bld;     /* blending (4E04) */
 413         struct r300_state_atom cmk;     /* colormask (4E0C) */
 414         struct r300_state_atom unk4E10; /* (4E10) */
 415         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 416         struct r300_state_atom unk4E50; /* (4E50) */
 417         struct r300_state_atom unk4E88; /* (4E88) */
 418         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 419         struct r300_state_atom zc;      /* z control (4F00) */
 420         struct r300_state_atom unk4F08; /* (4F08) */
 421         struct r300_state_atom unk4F10; /* (4F10) */
 422         struct r300_state_atom zb;      /* z buffer (4F20) */
 423         struct r300_state_atom unk4F28; /* (4F28) */
 424         struct r300_state_atom unk4F30; /* (4F30) */
 425         struct r300_state_atom unk4F44; /* (4F44) */
 426         struct r300_state_atom unk4F54; /* (4F54) */
 427
 428         struct r300_state_atom vpi;     /* vp instructions */
 429         struct r300_state_atom vpp;     /* vp parameters */
 430         struct r300_state_atom vps;     /* vertex point size (?) */
 431
 432                 /* 8 texture units */
 433                 /* the state is grouped by function and not by
 434                    texture unit. This makes single unit updates
 435                    really awkward - we are much better off
 436                    updating the whole thing at once */
 437         struct {
 438                 struct r300_state_atom filter;
 439                 struct r300_state_atom unknown1;
 440                 struct r300_state_atom size;
 441                 struct r300_state_atom format;
 442                 struct r300_state_atom offset;
 443                 struct r300_state_atom unknown4;
 444                 struct r300_state_atom unknown5;
 445                 } tex;
 446         struct r300_state_atom txe;     /* tex enable (4104) */
 447 };
 448
 449
 450 /**
 451  * This structure holds the command buffer while it is being constructed.
 452  *
 453  * The first batch of commands in the buffer is always the state that needs
 454  * to be re-emitted when the context is lost. This batch can be skipped
 455  * otherwise.
 456  */
 457 struct r300_cmdbuf {
 458         int             size;           /* DWORDs allocated for buffer */
 459         uint32_t*       cmd_buf;
 460         int             count_used;     /* DWORDs filled so far */
 461         int             count_reemit;   /* size of re-emission batch */
 462 };
 463
 464
 465 /**
 466  * State cache
 467  */
 468
 469 struct r300_depthbuffer_state {
 470         GLfloat scale;
 471 };
 472
 473 struct r300_vap_reg_state {
 474            /* input register assigments */
 475            int i_coords;
 476            int i_color[2];
 477            int i_tex[R300_MAX_TEXTURE_UNITS];
 478         };
 479
 480 /* Vertex shader state */
 481
 482 /* 64 appears to be the maximum */
 483 #define VSF_MAX_FRAGMENT_LENGTH 64
 484
 485
 486 struct r300_vertex_shader_fragment {
 487         int length;
 488         union {
 489                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 490                 float f[VSF_MAX_FRAGMENT_LENGTH];
 491                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 492                 } body;
 493         };
 494
 495 #define VSF_DEST_PROGRAM        0x0
 496 #define VSF_DEST_MATRIX0        0x200
 497 #define VSF_DEST_MATRIX1        0x204
 498 #define VSF_DEST_MATRIX2        0x208
 499 #define VSF_DEST_VECTOR0        0x20c
 500 #define VSF_DEST_VECTOR1        0x20d
 501 #define VSF_DEST_UNKNOWN1       0x400
 502 #define VSF_DEST_UNKNOWN2       0x406
 503
 504 struct r300_vertex_shader_state {
 505         struct r300_vertex_shader_fragment program;
 506
 507         /* a bit of a waste - each uses only a subset of allocated space..
 508             but easier to program */
 509         struct r300_vertex_shader_fragment matrix[3];
 510         struct r300_vertex_shader_fragment vector[2];
 511
 512         struct r300_vertex_shader_fragment unknown1;
 513         struct r300_vertex_shader_fragment unknown2;
 514
 515         int program_start;
 516         int unknown_ptr1;  /* pointer within program space */
 517         int program_end;
 518
 519         int param_offset;
 520         int param_count;
 521
 522         int unknown_ptr2;  /* pointer within program space */
 523         int unknown_ptr3;  /* pointer within program space */
 524         };
 525
 526 /* 64 appears to be the maximum */
 527 #define PSF_MAX_PROGRAM_LENGTH 64
 528
 529 struct r300_pixel_shader_program {
 530         struct {
 531                 int length;
 532                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 533                 } tex;
 534
 535         /* ALU intructions (logic and integer) */
 536         struct {
 537                 int length;
 538                 struct {
 539                         GLuint inst0;
 540                         GLuint inst1;
 541                         GLuint inst2;
 542                         GLuint inst3;
 543                         } inst[PSF_MAX_PROGRAM_LENGTH];
 544                 } alu;
 545
 546         /* node information */
 547         /* nodes are used to synchronize ALU and TEX streams */
 548         /* There could be up to 4 nodes each consisting of
 549            a number of TEX instructions followed by some ALU
 550            instructions */
 551         /* the last node of a program should always be node3 */
 552         struct {
 553                 int tex_offset;
 554                 int tex_end;
 555                 int alu_offset;
 556                 int alu_end;
 557                 } node[4];
 558
 559         int active_nodes;       /* must be between 1 and 4, inclusive */
 560         int first_node_has_tex;  /* other nodes always have it */
 561
 562         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 563
 564         /* entire program */
 565         int tex_offset;
 566         int tex_end;
 567         int alu_offset;
 568         int alu_end;
 569
 570         };
 571
 572         #define MAX_PIXEL_SHADER_PARAMS 32
 573 struct r300_pixel_shader_state {
 574         struct r300_pixel_shader_program program;
 575
 576         /* parameters */
 577         int param_length;  /* to limit the number of unnecessary writes */
 578         struct {
 579                 float x;
 580                 float y;
 581                 float z;
 582                 float w;
 583                 } param[MAX_PIXEL_SHADER_PARAMS];
 584         };
 585
 586 /* 8 is somewhat bogus... it is probably something like 24 */
 587 #define R300_MAX_AOS_ARRAYS             8
 588
 589 struct r300_aos_rec {
 590         GLuint offset;
 591         int element_size; /* in dwords */
 592         int stride;       /* distance between elements, in dwords */
 593
 594         #define AOS_FORMAT_FLOAT        1
 595         #define AOS_FORMAT_UBYTE        2
 596         #define AOS_FORMAT_FLOAT_COLOR  3
 597         int format;
 598
 599         int ncomponents; /* number of components - between 1 and 4, inclusive */
 600
 601          /* just guesses */
 602         #define REG_COORDS      0
 603         #define REG_COLOR0      1
 604         #define REG_TEX0        2
 605         int reg; /* which register they are assigned to. */
 606
 607         };
 608
 609 struct r300_state {
 610         struct r300_depthbuffer_state depth;
 611         struct r300_texture_state texture;
 612         struct r300_vap_reg_state vap_reg;
 613         struct r300_vertex_shader_state vertex_shader;
 614         struct r300_pixel_shader_state pixel_shader;
 615         struct r300_aos_rec aos[R300_MAX_AOS_ARRAYS];
 616         int aos_count;
 617
 618 };
 619
 620
 621 /**
 622  * R300 context structure.
 623  */
 624 struct r300_context {
 625         struct radeon_context radeon; /* parent class, must be first */
 626
 627         struct r300_hw_state hw;
 628         struct r300_cmdbuf cmdbuf;
 629         struct r300_state state;
 630
 631         /* Vertex buffers */
 632         int elt_count;  /* size of the buffer for vertices */
 633         int attrib_count; /* size of the buffer for vertex attributes.. Somehow it can be different ? */
 634
 635
 636         /* Vertex buffers
 637          */
 638         #if 0 /* we'll need it later, but not now */
 639         struct r300_ioctl ioctl;
 640         #endif
 641         struct r300_dma dma;
 642         GLboolean save_on_next_unlock;
 643
 644         /* Texture object bookkeeping
 645          */
 646         unsigned nr_heaps;
 647         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 648         driTextureObject swapped;
 649         int texture_depth;
 650         float initialMaxAnisotropy;
 651
 652         /* Clientdata textures;
 653          */
 654         GLuint prefer_gart_client_texturing;
 655
 656         /* TCL stuff
 657          */
 658         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 659         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 660         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 661         GLuint TexMatEnabled;
 662         GLuint TexMatCompSel;
 663         GLuint TexGenEnabled;
 664         GLuint TexGenInputs;
 665         GLuint TexGenCompSel;
 666         GLmatrix tmpmat;
 667 };
 668
 669 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 670
 671 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 672 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 673                                    __DRIcontextPrivate * driContextPriv,
 674                                    void *sharedContextPrivate);
 675
 676 #endif                          /* __R300_CONTEXT_H__ */