src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45
  46 #include "macros.h"
  47 #include "mtypes.h"
  48 #include "colormac.h"
  49
  50 #define USER_BUFFERS
  51
  52 struct r300_context;
  53 typedef struct r300_context r300ContextRec;
  54 typedef struct r300_context *r300ContextPtr;
  55
  56 #include "radeon_lock.h"
  57 #include "mm.h"
  58
  59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 #include "r300_vertprog.h"
  76 #include "r300_fragprog.h"
  77 #include "r500_fragprog.h"
  78
  79 /**
  80  * This function takes a float and packs it into a uint32_t
  81  */
  82 static inline uint32_t r300PackFloat32(float fl)
  83 {
  84         union {
  85                 float fl;
  86                 uint32_t u;
  87         } u;
  88
  89         u.fl = fl;
  90         return u.u;
  91 }
  92
  93 /* This is probably wrong for some values, I need to test this
  94  * some more.  Range checking would be a good idea also..
  95  *
  96  * But it works for most things.  I'll fix it later if someone
  97  * else with a better clue doesn't
  98  */
  99 static inline uint32_t r300PackFloat24(float f)
 100 {
 101         float mantissa;
 102         int exponent;
 103         uint32_t float24 = 0;
 104
 105         if (f == 0.0)
 106                 return 0;
 107
 108         mantissa = frexpf(f, &exponent);
 109
 110         /* Handle -ve */
 111         if (mantissa < 0) {
 112                 float24 |= (1 << 23);
 113                 mantissa = mantissa * -1.0;
 114         }
 115         /* Handle exponent, bias of 63 */
 116         exponent += 62;
 117         float24 |= (exponent << 16);
 118         /* Kill 7 LSB of mantissa */
 119         float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7;
 120
 121         return float24;
 122 }
 123
 124 /************ DMA BUFFERS **************/
 125
 126 /* Need refcounting on dma buffers:
 127  */
 128 struct r300_dma_buffer {
 129         int refcount;           /**< the number of retained regions in buf */
 130         drmBufPtr buf;
 131         int id;
 132 };
 133 #undef GET_START
 134 #ifdef USER_BUFFERS
 135 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 136 #else
 137 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 138                         (rvb)->address - rmesa->dma.buf0_address +      \
 139                         (rvb)->start)
 140 #endif
 141 /* A retained region, eg vertices for indexed vertices.
 142  */
 143 struct r300_dma_region {
 144         struct r300_dma_buffer *buf;
 145         char *address;          /* == buf->address */
 146         int start, end, ptr;    /* offsets from start of buf */
 147
 148         int aos_offset;         /* address in GART memory */
 149         int aos_stride;         /* distance between elements, in dwords */
 150         int aos_size;           /* number of components (1-4) */
 151 };
 152
 153 struct r300_dma {
 154         /* Active dma region.  Allocations for vertices and retained
 155          * regions come from here.  Also used for emitting random vertices,
 156          * these may be flushed by calling flush_current();
 157          */
 158         struct r300_dma_region current;
 159
 160         void (*flush) (r300ContextPtr);
 161
 162         char *buf0_address;     /* start of buf[0], for index calcs */
 163
 164         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 165          * for which a DISCARD command is currently queued in the command buffer.
 166          */
 167         GLuint nr_released_bufs;
 168 };
 169
 170        /* Texture related */
 171
 172 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 173
 174 /* Texture object in locally shared texture space.
 175  */
 176 struct r300_tex_obj {
 177         driTextureObject base;
 178
 179         GLuint bufAddr;         /* Offset to start of locally
 180                                    shared texture block */
 181
 182         GLuint dirty_state;     /* Flags (1 per texunit) for
 183                                    whether or not this texobj
 184                                    has dirty hardware state
 185                                    (pp_*) that needs to be
 186                                    brought into the
 187                                    texunit. */
 188
 189         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 190         /* Six, for the cube faces */
 191
 192         GLboolean image_override;       /* Image overridden by GLX_EXT_tfp */
 193
 194         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 195         /* hardware register values */
 196         /* Note that R200 has 8 registers per texture and R300 only 7 */
 197         GLuint filter;
 198         GLuint filter_1;
 199         GLuint pitch_reg;
 200         GLuint size;            /* npot only */
 201         GLuint format;
 202         GLuint offset;          /* Image location in the card's address space.
 203                                    All cube faces follow. */
 204         GLuint unknown4;
 205         GLuint unknown5;
 206         /* end hardware registers */
 207
 208         /* registers computed by r200 code - keep them here to
 209            compare against what is actually written.
 210
 211            to be removed later.. */
 212         GLuint pp_border_color;
 213         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 214         GLuint format_x;
 215
 216         GLboolean border_fallback;
 217
 218         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 219 };
 220
 221 struct r300_texture_env_state {
 222         r300TexObjPtr texobj;
 223         GLenum format;
 224         GLenum envMode;
 225 };
 226
 227 /* The blit width for texture uploads
 228  */
 229 #define R300_BLIT_WIDTH_BYTES 1024
 230 #define R300_MAX_TEXTURE_UNITS 8
 231
 232 struct r300_texture_state {
 233         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 234         int tc_count;           /* number of incoming texture coordinates from VAP */
 235 };
 236
 237 /**
 238  * A block of hardware state.
 239  *
 240  * When check returns non-zero, the returned number of dwords must be
 241  * copied verbatim into the command buffer in order to update a state atom
 242  * when it is dirty.
 243  */
 244 struct r300_state_atom {
 245         struct r300_state_atom *next, *prev;
 246         const char *name;       /* for debug */
 247         int cmd_size;           /* maximum size in dwords */
 248         GLuint idx;             /* index in an array (e.g. textures) */
 249         uint32_t *cmd;
 250         GLboolean dirty;
 251
 252         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 253 };
 254
 255 #define R300_VPT_CMD_0          0
 256 #define R300_VPT_XSCALE         1
 257 #define R300_VPT_XOFFSET        2
 258 #define R300_VPT_YSCALE         3
 259 #define R300_VPT_YOFFSET        4
 260 #define R300_VPT_ZSCALE         5
 261 #define R300_VPT_ZOFFSET        6
 262 #define R300_VPT_CMDSIZE        7
 263
 264 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 265 #define R300_VIR_CNTL_0         1
 266 #define R300_VIR_CNTL_1         2
 267 #define R300_VIR_CNTL_2         3
 268 #define R300_VIR_CNTL_3         4
 269 #define R300_VIR_CNTL_4         5
 270 #define R300_VIR_CNTL_5         6
 271 #define R300_VIR_CNTL_6         7
 272 #define R300_VIR_CNTL_7         8
 273 #define R300_VIR_CMDSIZE        9
 274
 275 #define R300_VIC_CMD_0          0
 276 #define R300_VIC_CNTL_0         1
 277 #define R300_VIC_CNTL_1         2
 278 #define R300_VIC_CMDSIZE        3
 279
 280 #define R300_VOF_CMD_0          0
 281 #define R300_VOF_CNTL_0         1
 282 #define R300_VOF_CNTL_1         2
 283 #define R300_VOF_CMDSIZE        3
 284
 285 #define R300_PVS_CMD_0          0
 286 #define R300_PVS_CNTL_1         1
 287 #define R300_PVS_CNTL_2         2
 288 #define R300_PVS_CNTL_3         3
 289 #define R300_PVS_CMDSIZE        4
 290
 291 #define R300_GB_MISC_CMD_0              0
 292 #define R300_GB_MISC_MSPOS_0            1
 293 #define R300_GB_MISC_MSPOS_1            2
 294 #define R300_GB_MISC_TILE_CONFIG        3
 295 #define R300_GB_MISC_SELECT             4
 296 #define R300_GB_MISC_AA_CONFIG          5
 297 #define R300_GB_MISC_CMDSIZE            6
 298
 299 #define R300_TXE_CMD_0          0
 300 #define R300_TXE_ENABLE         1
 301 #define R300_TXE_CMDSIZE        2
 302
 303 #define R300_PS_CMD_0           0
 304 #define R300_PS_POINTSIZE       1
 305 #define R300_PS_CMDSIZE         2
 306
 307 #define R300_ZBS_CMD_0          0
 308 #define R300_ZBS_T_FACTOR       1
 309 #define R300_ZBS_T_CONSTANT     2
 310 #define R300_ZBS_W_FACTOR       3
 311 #define R300_ZBS_W_CONSTANT     4
 312 #define R300_ZBS_CMDSIZE        5
 313
 314 #define R300_CUL_CMD_0          0
 315 #define R300_CUL_CULL           1
 316 #define R300_CUL_CMDSIZE        2
 317
 318 #define R300_RC_CMD_0           0
 319 #define R300_RC_CNTL_0          1
 320 #define R300_RC_CNTL_1          2
 321 #define R300_RC_CMDSIZE         3
 322
 323 #define R300_RI_CMD_0           0
 324 #define R300_RI_INTERP_0        1
 325 #define R300_RI_INTERP_1        2
 326 #define R300_RI_INTERP_2        3
 327 #define R300_RI_INTERP_3        4
 328 #define R300_RI_INTERP_4        5
 329 #define R300_RI_INTERP_5        6
 330 #define R300_RI_INTERP_6        7
 331 #define R300_RI_INTERP_7        8
 332 #define R300_RI_CMDSIZE         9
 333
 334 #define R500_RI_CMDSIZE        17
 335
 336 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 337 #define R300_RR_INST_0          1
 338 #define R300_RR_INST_1          2
 339 #define R300_RR_INST_2          3
 340 #define R300_RR_INST_3          4
 341 #define R300_RR_INST_4          5
 342 #define R300_RR_INST_5          6
 343 #define R300_RR_INST_6          7
 344 #define R300_RR_INST_7          8
 345 #define R300_RR_CMDSIZE         9
 346
 347 #define R300_FP_CMD_0           0
 348 #define R300_FP_CNTL0           1
 349 #define R300_FP_CNTL1           2
 350 #define R300_FP_CNTL2           3
 351 #define R300_FP_CMD_1           4
 352 #define R300_FP_NODE0           5
 353 #define R300_FP_NODE1           6
 354 #define R300_FP_NODE2           7
 355 #define R300_FP_NODE3           8
 356 #define R300_FP_CMDSIZE         9
 357
 358 #define R500_FP_CMD_0           0
 359 #define R500_FP_CNTL            1
 360 #define R500_FP_PIXSIZE         2
 361 #define R500_FP_CMD_1           3
 362 #define R500_FP_CODE_ADDR       4
 363 #define R500_FP_CODE_RANGE      5
 364 #define R500_FP_CODE_OFFSET     6
 365 #define R500_FP_CMD_2           7
 366 #define R500_FP_FC_CNTL         8
 367 #define R500_FP_CMDSIZE         9
 368
 369 #define R300_FPT_CMD_0          0
 370 #define R300_FPT_INSTR_0        1
 371 #define R300_FPT_CMDSIZE        65
 372
 373 #define R300_FPI_CMD_0          0
 374 #define R300_FPI_INSTR_0        1
 375 #define R300_FPI_CMDSIZE        65
 376 /* R500 has space for 512 instructions - 6 dwords per instruction */
 377 #define R500_FPI_CMDSIZE        (512*6+1)
 378
 379 #define R300_FPP_CMD_0          0
 380 #define R300_FPP_PARAM_0        1
 381 #define R300_FPP_CMDSIZE        (32*4+1)
 382 /* R500 has spcae for 256 constants - 4 dwords per constant */
 383 #define R500_FPP_CMDSIZE        (256*4+1)
 384
 385 #define R300_FOGS_CMD_0         0
 386 #define R300_FOGS_STATE         1
 387 #define R300_FOGS_CMDSIZE       2
 388
 389 #define R300_FOGC_CMD_0         0
 390 #define R300_FOGC_R             1
 391 #define R300_FOGC_G             2
 392 #define R300_FOGC_B             3
 393 #define R300_FOGC_CMDSIZE       4
 394
 395 #define R300_FOGP_CMD_0         0
 396 #define R300_FOGP_SCALE         1
 397 #define R300_FOGP_START         2
 398 #define R300_FOGP_CMDSIZE       3
 399
 400 #define R300_AT_CMD_0           0
 401 #define R300_AT_ALPHA_TEST      1
 402 #define R300_AT_UNKNOWN         2
 403 #define R300_AT_CMDSIZE         3
 404
 405 #define R300_BLD_CMD_0          0
 406 #define R300_BLD_CBLEND         1
 407 #define R300_BLD_ABLEND         2
 408 #define R300_BLD_CMDSIZE        3
 409
 410 #define R300_CMK_CMD_0          0
 411 #define R300_CMK_COLORMASK      1
 412 #define R300_CMK_CMDSIZE        2
 413
 414 #define R300_CB_CMD_0           0
 415 #define R300_CB_OFFSET          1
 416 #define R300_CB_CMD_1           2
 417 #define R300_CB_PITCH           3
 418 #define R300_CB_CMDSIZE         4
 419
 420 #define R300_ZS_CMD_0           0
 421 #define R300_ZS_CNTL_0          1
 422 #define R300_ZS_CNTL_1          2
 423 #define R300_ZS_CNTL_2          3
 424 #define R300_ZS_CMDSIZE         4
 425
 426 #define R300_ZB_CMD_0           0
 427 #define R300_ZB_OFFSET          1
 428 #define R300_ZB_PITCH           2
 429 #define R300_ZB_CMDSIZE         3
 430
 431 #define R300_VAP_CNTL_FLUSH     0
 432 #define R300_VAP_CNTL_FLUSH_1   1
 433 #define R300_VAP_CNTL_CMD       2
 434 #define R300_VAP_CNTL_INSTR     3
 435 #define R300_VAP_CNTL_SIZE      4
 436
 437 #define R300_VPI_CMD_0          0
 438 #define R300_VPI_INSTR_0        1
 439 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 440
 441 #define R300_VPP_CMD_0          0
 442 #define R300_VPP_PARAM_0        1
 443 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 444
 445 #define R300_VPUCP_CMD_0                0
 446 #define R300_VPUCP_X            1
 447 #define R300_VPUCP_Y            2
 448 #define R300_VPUCP_Z            3
 449 #define R300_VPUCP_W            4
 450 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 451
 452 #define R300_VPS_CMD_0          0
 453 #define R300_VPS_ZERO_0         1
 454 #define R300_VPS_ZERO_1         2
 455 #define R300_VPS_POINTSIZE      3
 456 #define R300_VPS_ZERO_3         4
 457 #define R300_VPS_CMDSIZE        5
 458
 459         /* the layout is common for all fields inside tex */
 460 #define R300_TEX_CMD_0          0
 461 #define R300_TEX_VALUE_0        1
 462 /* We don't really use this, instead specify mtu+1 dynamically
 463 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 464 */
 465
 466 /**
 467  * Cache for hardware register state.
 468  */
 469 struct r300_hw_state {
 470         struct r300_state_atom atomlist;
 471
 472         GLboolean is_dirty;
 473         GLboolean all_dirty;
 474         int max_state_size;     /* in dwords */
 475
 476         struct r300_state_atom vpt;     /* viewport (1D98) */
 477         struct r300_state_atom vap_cntl;
 478         struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */
 479         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 480         struct r300_state_atom vte;     /* (20B0) */
 481         struct r300_state_atom vap_vf_max_vtx_indx;     /* Maximum Vertex Indx Clamp (2134) */
 482         struct r300_state_atom vap_cntl_status;
 483         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 484         struct r300_state_atom vic;     /* vap input control (2180) */
 485         struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 486         struct r300_state_atom vap_clip_cntl;
 487         struct r300_state_atom vap_clip;
 488         struct r300_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */
 489         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 490         struct r300_state_atom gb_enable;       /* (4008) */
 491         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 492         struct r300_state_atom ga_point_s0;     /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 493         struct r300_state_atom ga_triangle_stipple;     /* (4214) */
 494         struct r300_state_atom ps;      /* pointsize (421C) */
 495         struct r300_state_atom ga_point_minmax; /* (4230) */
 496         struct r300_state_atom lcntl;   /* line control */
 497         struct r300_state_atom ga_line_stipple; /* (4260) */
 498         struct r300_state_atom shade;
 499         struct r300_state_atom polygon_mode;
 500         struct r300_state_atom fogp;    /* fog parameters (4294) */
 501         struct r300_state_atom ga_soft_reset;   /* (429C) */
 502         struct r300_state_atom zbias_cntl;
 503         struct r300_state_atom zbs;     /* zbias (42A4) */
 504         struct r300_state_atom occlusion_cntl;
 505         struct r300_state_atom cul;     /* cull cntl (42B8) */
 506         struct r300_state_atom su_depth_scale;  /* (42C0) */
 507         struct r300_state_atom rc;      /* rs control (4300) */
 508         struct r300_state_atom ri;      /* rs interpolators (4310) */
 509         struct r300_state_atom rr;      /* rs route (4330) */
 510         struct r300_state_atom sc_hyperz;       /* (43A4) */
 511         struct r300_state_atom sc_screendoor;   /* (43E8) */
 512         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 513         struct r300_state_atom fpt;     /* texi - (4620) */
 514         struct r300_state_atom us_out_fmt;      /* (46A4) */
 515         struct r300_state_atom r500fp;  /* r500 fp instructions */
 516         struct r300_state_atom r500fp_const;    /* r500 fp constants */
 517         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 518         struct r300_state_atom fogs;    /* fog state (4BC0) */
 519         struct r300_state_atom fogc;    /* fog color (4BC8) */
 520         struct r300_state_atom at;      /* alpha test (4BD4) */
 521         struct r300_state_atom fg_depth_src;    /* (4BD8) */
 522         struct r300_state_atom fpp;     /* 0x4C00 and following */
 523         struct r300_state_atom rb3d_cctl;       /* (4E00) */
 524         struct r300_state_atom bld;     /* blending (4E04) */
 525         struct r300_state_atom cmk;     /* colormask (4E0C) */
 526         struct r300_state_atom blend_color;     /* constant blend color */
 527         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 528         struct r300_state_atom rb3d_dither_ctl; /* (4E50) */
 529         struct r300_state_atom rb3d_aaresolve_ctl;      /* (4E88) */
 530         struct r300_state_atom rb3d_discard_src_pixel_lte_threshold;    /* (4E88) I saw it only written on RV350 hardware..  */
 531         struct r300_state_atom zs;      /* zstencil control (4F00) */
 532         struct r300_state_atom zstencil_format;
 533         struct r300_state_atom zb;      /* z buffer (4F20) */
 534         struct r300_state_atom zb_depthclearvalue;      /* (4F28) */
 535         struct r300_state_atom unk4F30; /* (4F30) */
 536         struct r300_state_atom zb_hiz_offset;   /* (4F44) */
 537         struct r300_state_atom zb_hiz_pitch;    /* (4F54) */
 538
 539         struct r300_state_atom vpi;     /* vp instructions */
 540         struct r300_state_atom vpp;     /* vp parameters */
 541         struct r300_state_atom vps;     /* vertex point size (?) */
 542         struct r300_state_atom vpucp[6];        /* vp user clip plane - 6 */
 543         /* 8 texture units */
 544         /* the state is grouped by function and not by
 545            texture unit. This makes single unit updates
 546            really awkward - we are much better off
 547            updating the whole thing at once */
 548         struct {
 549                 struct r300_state_atom filter;
 550                 struct r300_state_atom filter_1;
 551                 struct r300_state_atom size;
 552                 struct r300_state_atom format;
 553                 struct r300_state_atom pitch;
 554                 struct r300_state_atom offset;
 555                 struct r300_state_atom chroma_key;
 556                 struct r300_state_atom border_color;
 557         } tex;
 558         struct r300_state_atom txe;     /* tex enable (4104) */
 559 };
 560
 561 /**
 562  * This structure holds the command buffer while it is being constructed.
 563  *
 564  * The first batch of commands in the buffer is always the state that needs
 565  * to be re-emitted when the context is lost. This batch can be skipped
 566  * otherwise.
 567  */
 568 struct r300_cmdbuf {
 569         int size;               /* DWORDs allocated for buffer */
 570         uint32_t *cmd_buf;
 571         int count_used;         /* DWORDs filled so far */
 572         int count_reemit;       /* size of re-emission batch */
 573 };
 574
 575 /**
 576  * State cache
 577  */
 578
 579 struct r300_depthbuffer_state {
 580         GLfloat scale;
 581 };
 582
 583 struct r300_stencilbuffer_state {
 584         GLuint clear;
 585         GLboolean hw_stencil;
 586
 587 };
 588
 589 /* Vertex shader state */
 590
 591 /* Perhaps more if we store programs in vmem? */
 592 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 593 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 594
 595 /* Can be tested with colormat currently. */
 596 #define VSF_MAX_FRAGMENT_TEMPS (14)
 597
 598 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 599 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 600
 601 struct r300_vertex_shader_fragment {
 602         int length;
 603         union {
 604                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 605                 float f[VSF_MAX_FRAGMENT_LENGTH];
 606                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 607         } body;
 608 };
 609
 610 struct r300_vertex_shader_state {
 611         struct r300_vertex_shader_fragment program;
 612 };
 613
 614 extern int hw_tcl_on;
 615
 616 #define COLOR_IS_RGBA
 617 #define TAG(x) r300##x
 618 #include "tnl_dd/t_dd_vertex.h"
 619 #undef TAG
 620
 621 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 622 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 623
 624 /* Should but doesnt work */
 625 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 626
 627 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 628  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 629  */
 630
 631 struct r300_vertex_program_key {
 632         GLuint InputsRead;
 633         GLuint OutputsWritten;
 634         GLuint OutputsAdded;
 635 };
 636
 637 struct r300_vertex_program {
 638         struct r300_vertex_program *next;
 639         struct r300_vertex_program_key key;
 640         int translated;
 641
 642         struct r300_vertex_shader_fragment program;
 643
 644         int pos_end;
 645         int num_temporaries;    /* Number of temp vars used by program */
 646         int wpos_idx;
 647         int inputs[VERT_ATTRIB_MAX];
 648         int outputs[VERT_RESULT_MAX];
 649         int native;
 650         int ref_count;
 651         int use_ref_count;
 652 };
 653
 654 struct r300_vertex_program_cont {
 655         struct gl_vertex_program mesa_program;  /* Must be first */
 656         struct r300_vertex_shader_fragment params;
 657         struct r300_vertex_program *progs;
 658 };
 659
 660 #define PFS_MAX_ALU_INST        64
 661 #define PFS_MAX_TEX_INST        64
 662 #define PFS_MAX_TEX_INDIRECT 4
 663 #define PFS_NUM_TEMP_REGS       32
 664 #define PFS_NUM_CONST_REGS      16
 665
 666 /* Mapping Mesa registers to R300 temporaries */
 667 struct reg_acc {
 668         int reg;                /* Assigned hw temp */
 669         unsigned int refcount;  /* Number of uses by mesa program */
 670 };
 671
 672 /**
 673  * Describe the current lifetime information for an R300 temporary
 674  */
 675 struct reg_lifetime {
 676         /* Index of the first slot where this register is free in the sense
 677            that it can be used as a new destination register.
 678            This is -1 if the register has been assigned to a Mesa register
 679            and the last access to the register has not yet been emitted */
 680         int free;
 681
 682         /* Index of the first slot where this register is currently reserved.
 683            This is used to stop e.g. a scalar operation from being moved
 684            before the allocation time of a register that was first allocated
 685            for a vector operation. */
 686         int reserved;
 687
 688         /* Index of the first slot in which the register can be used as a
 689            source without losing the value that is written by the last
 690            emitted instruction that writes to the register */
 691         int vector_valid;
 692         int scalar_valid;
 693
 694         /* Index to the slot where the register was last read.
 695            This is also the first slot in which the register may be written again */
 696         int vector_lastread;
 697         int scalar_lastread;
 698 };
 699
 700 /**
 701  * Store usage information about an ALU instruction slot during the
 702  * compilation of a fragment program.
 703  */
 704 #define SLOT_SRC_VECTOR  (1<<0)
 705 #define SLOT_SRC_SCALAR  (1<<3)
 706 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 707 #define SLOT_OP_VECTOR   (1<<16)
 708 #define SLOT_OP_SCALAR   (1<<17)
 709 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 710
 711 struct r300_pfs_compile_slot {
 712         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 713            defined above */
 714         unsigned int used;
 715
 716         /* Selected sources */
 717         int vsrc[3];
 718         int ssrc[3];
 719 };
 720
 721 /**
 722  * Store information during compilation of fragment programs.
 723  */
 724 struct r300_pfs_compile_state {
 725         int nrslots;            /* number of ALU slots used so far */
 726
 727         /* Track which (parts of) slots are already filled with instructions */
 728         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 729
 730         /* Track the validity of R300 temporaries */
 731         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 732
 733         /* Used to map Mesa's inputs/temps onto hardware temps */
 734         int temp_in_use;
 735         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 736         struct reg_acc inputs[32];      /* don't actually need 32... */
 737
 738         /* Track usage of hardware temps, for register allocation,
 739          * indirection detection, etc. */
 740         GLuint used_in_node;
 741         GLuint dest_in_node;
 742 };
 743
 744 /**
 745  * Store everything about a fragment program that is needed
 746  * to render with that program.
 747  */
 748 struct r300_fragment_program {
 749         struct gl_fragment_program mesa_program;
 750
 751         GLcontext *ctx;
 752         GLboolean translated;
 753         GLboolean error;
 754         struct r300_pfs_compile_state *cs;
 755
 756         struct {
 757                 int length;
 758                 GLuint inst[PFS_MAX_TEX_INST];
 759         } tex;
 760
 761         struct {
 762                 struct {
 763                         GLuint inst0;
 764                         GLuint inst1;
 765                         GLuint inst2;
 766                         GLuint inst3;
 767                 } inst[PFS_MAX_ALU_INST];
 768         } alu;
 769
 770         struct {
 771                 int tex_offset;
 772                 int tex_end;
 773                 int alu_offset;
 774                 int alu_end;
 775                 int flags;
 776         } node[4];
 777         int cur_node;
 778         int first_node_has_tex;
 779
 780         int alu_offset;
 781         int alu_end;
 782         int tex_offset;
 783         int tex_end;
 784
 785         /* Hardware constants.
 786          * Contains a pointer to the value. The destination of the pointer
 787          * is supposed to be updated when GL state changes.
 788          * Typically, this is either a pointer into
 789          * gl_program_parameter_list::ParameterValues, or a pointer to a
 790          * global constant (e.g. for sin/cos-approximation)
 791          */
 792         const GLfloat *constant[PFS_NUM_CONST_REGS];
 793         int const_nr;
 794
 795         int max_temp_idx;
 796
 797         GLuint optimization;
 798 };
 799
 800 struct r500_fragment_program {
 801         struct gl_fragment_program mesa_program;
 802
 803         GLcontext *ctx;
 804         GLboolean translated;
 805         GLboolean error;
 806         struct r300_pfs_compile_state *cs;
 807
 808         struct {
 809                 GLuint inst0;
 810                 GLuint inst1;
 811                 GLuint inst2;
 812                 GLuint inst3;
 813                 GLuint inst4;
 814                 GLuint inst5;
 815         } inst[512];
 816         /* TODO: This is magic! */
 817
 818         int temp_reg_offset;
 819
 820         int inst_offset;
 821         int inst_end;
 822
 823         /* Hardware constants.
 824          * Contains a pointer to the value. The destination of the pointer
 825          * is supposed to be updated when GL state changes.
 826          * Typically, this is either a pointer into
 827          * gl_program_parameter_list::ParameterValues, or a pointer to a
 828          * global constant (e.g. for sin/cos-approximation)
 829          */
 830         const GLfloat *constant[PFS_NUM_CONST_REGS];
 831         int const_nr;
 832
 833         int max_temp_idx;
 834
 835         GLuint optimization;
 836 };
 837
 838 #define R300_MAX_AOS_ARRAYS             16
 839
 840 #define REG_COORDS      0
 841 #define REG_COLOR0      1
 842 #define REG_TEX0        2
 843
 844 struct r300_state {
 845         struct r300_depthbuffer_state depth;
 846         struct r300_texture_state texture;
 847         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 848         struct r300_vertex_shader_state vertex_shader;
 849         struct r300_pfs_compile_state pfs_compile;
 850         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 851         int aos_count;
 852
 853         GLuint *Elts;
 854         struct r300_dma_region elt_dma;
 855
 856         struct r300_dma_region swtcl_dma;
 857         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 858                                                            They are the same as tnl->render_inputs for fixed pipeline */
 859
 860         struct r300_stencilbuffer_state stencil;
 861
 862 };
 863
 864 #define R300_FALLBACK_NONE 0
 865 #define R300_FALLBACK_TCL 1
 866 #define R300_FALLBACK_RAST 2
 867
 868 /* r300_swtcl.c
 869  */
 870 struct r300_swtcl_info {
 871    GLuint RenderIndex;
 872
 873    /**
 874     * Size of a hardware vertex.  This is calculated when \c ::vertex_attrs is
 875     * installed in the Mesa state vector.
 876     */
 877    GLuint vertex_size;
 878
 879    /**
 880     * Attributes instructing the Mesa TCL pipeline where / how to put vertex
 881     * data in the hardware buffer.
 882     */
 883    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 884
 885    /**
 886     * Number of elements of \c ::vertex_attrs that are actually used.
 887     */
 888    GLuint vertex_attr_count;
 889
 890    /**
 891     * Cached pointer to the buffer where Mesa will store vertex data.
 892     */
 893    GLubyte *verts;
 894
 895    /* Fallback rasterization functions
 896     */
 897   //   r200_point_func draw_point;
 898   //   r200_line_func draw_line;
 899   //   r200_tri_func draw_tri;
 900
 901    GLuint hw_primitive;
 902    GLenum render_primitive;
 903    GLuint numverts;
 904
 905    /**
 906     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 907     */
 908    GLuint coloroffset;
 909
 910    /**
 911     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 912     */
 913    GLuint specoffset;
 914
 915    /**
 916     * Should Mesa project vertex data or will the hardware do it?
 917     */
 918    GLboolean needproj;
 919
 920    struct r300_dma_region indexed_verts;
 921 };
 922
 923
 924 /**
 925  * \brief R300 context structure.
 926  */
 927 struct r300_context {
 928         struct radeon_context radeon;   /* parent class, must be first */
 929
 930         struct r300_hw_state hw;
 931         struct r300_cmdbuf cmdbuf;
 932         struct r300_state state;
 933         struct gl_vertex_program *curr_vp;
 934         struct r300_vertex_program *selected_vp;
 935
 936         /* Vertex buffers
 937          */
 938         struct r300_dma dma;
 939         GLboolean save_on_next_unlock;
 940         GLuint NewGLState;
 941
 942         /* Texture object bookkeeping
 943          */
 944         unsigned nr_heaps;
 945         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 946         driTextureObject swapped;
 947         int texture_depth;
 948         float initialMaxAnisotropy;
 949
 950         /* Clientdata textures;
 951          */
 952         GLuint prefer_gart_client_texturing;
 953
 954 #ifdef USER_BUFFERS
 955         struct r300_memory_manager *rmm;
 956 #endif
 957
 958         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 959         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 960
 961         GLboolean disable_lowimpact_fallback;
 962
 963         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 964         struct r300_swtcl_info swtcl;
 965 };
 966
 967 struct r300_buffer_object {
 968         struct gl_buffer_object mesa_obj;
 969         int id;
 970 };
 971
 972 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 973
 974 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 975 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 976                                    __DRIcontextPrivate * driContextPriv,
 977                                    void *sharedContextPrivate);
 978
 979 extern void r300SelectVertexShader(r300ContextPtr r300);
 980 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 981 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 982                                       struct r300_vertex_program_cont *vp,
 983                                       float *dst);
 984
 985 #define RADEON_D_CAPTURE 0
 986 #define RADEON_D_PLAYBACK 1
 987 #define RADEON_D_PLAYBACK_RAW 2
 988 #define RADEON_D_T 3
 989
 990 #endif                          /* __R300_CONTEXT_H__ */