2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
34 * \author Nicolai Haehnle <prefect_@gmx.net>
37 #ifndef __R300_CONTEXT_H__
38 #define __R300_CONTEXT_H__
40 #include "tnl/t_vertex.h"
42 #include "radeon_drm.h"
53 typedef struct r300_context r300ContextRec
;
54 typedef struct r300_context
*r300ContextPtr
;
56 #include "radeon_lock.h"
59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
60 I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
61 with other compilers ... GLUE!
63 #define WARN_ONCE(a, ...) { \
64 static int warn##__LINE__=1; \
66 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
67 fprintf(stderr, "File %s function %s line %d\n", \
68 __FILE__, __FUNCTION__, __LINE__); \
69 fprintf(stderr, a, ## __VA_ARGS__);\
70 fprintf(stderr, "***************************************************************************\n"); \
75 #include "r300_vertprog.h"
76 #include "r500_fragprog.h"
79 * This function takes a float and packs it into a uint32_t
81 static INLINE
uint32_t r300PackFloat32(float fl
)
92 /* This is probably wrong for some values, I need to test this
93 * some more. Range checking would be a good idea also..
95 * But it works for most things. I'll fix it later if someone
96 * else with a better clue doesn't
98 static INLINE
uint32_t r300PackFloat24(float f
)
102 uint32_t float24
= 0;
107 mantissa
= frexpf(f
, &exponent
);
111 float24
|= (1 << 23);
112 mantissa
= mantissa
* -1.0;
114 /* Handle exponent, bias of 63 */
116 float24
|= (exponent
<< 16);
117 /* Kill 7 LSB of mantissa */
118 float24
|= (r300PackFloat32(mantissa
) & 0x7FFFFF) >> 7;
123 /************ DMA BUFFERS **************/
125 /* Need refcounting on dma buffers:
127 struct r300_dma_buffer
{
128 int refcount
; /**< the number of retained regions in buf */
134 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
136 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \
137 (rvb)->address - rmesa->dma.buf0_address + \
140 /* A retained region, eg vertices for indexed vertices.
142 struct r300_dma_region
{
143 struct r300_dma_buffer
*buf
;
144 char *address
; /* == buf->address */
145 int start
, end
, ptr
; /* offsets from start of buf */
147 int aos_offset
; /* address in GART memory */
148 int aos_stride
; /* distance between elements, in dwords */
149 int aos_size
; /* number of components (1-4) */
153 /* Active dma region. Allocations for vertices and retained
154 * regions come from here. Also used for emitting random vertices,
155 * these may be flushed by calling flush_current();
157 struct r300_dma_region current
;
159 void (*flush
) (r300ContextPtr
);
161 char *buf0_address
; /* start of buf[0], for index calcs */
163 /* Number of "in-flight" DMA buffers, i.e. the number of buffers
164 * for which a DISCARD command is currently queued in the command buffer.
166 GLuint nr_released_bufs
;
169 /* Texture related */
171 typedef struct r300_tex_obj r300TexObj
, *r300TexObjPtr
;
173 /* Texture object in locally shared texture space.
175 struct r300_tex_obj
{
176 driTextureObject base
;
178 GLuint bufAddr
; /* Offset to start of locally
179 shared texture block */
181 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
182 /* Six, for the cube faces */
184 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
186 GLuint pitch
; /* this isn't sent to hardware just used in calculations */
187 /* hardware register values */
188 /* Note that R200 has 8 registers per texture and R300 only 7 */
192 GLuint size
; /* npot only */
194 GLuint offset
; /* Image location in the card's address space.
195 All cube faces follow. */
198 /* end hardware registers */
200 /* registers computed by r200 code - keep them here to
201 compare against what is actually written.
203 to be removed later.. */
204 GLuint pp_border_color
;
205 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
208 GLboolean border_fallback
;
210 GLuint tile_bits
; /* hw texture tile bits used on this texture */
213 struct r300_texture_env_state
{
214 r300TexObjPtr texobj
;
219 /* The blit width for texture uploads
221 #define R300_BLIT_WIDTH_BYTES 1024
222 #define R300_MAX_TEXTURE_UNITS 8
224 struct r300_texture_state
{
225 struct r300_texture_env_state unit
[R300_MAX_TEXTURE_UNITS
];
226 int tc_count
; /* number of incoming texture coordinates from VAP */
230 * A block of hardware state.
232 * When check returns non-zero, the returned number of dwords must be
233 * copied verbatim into the command buffer in order to update a state atom
236 struct r300_state_atom
{
237 struct r300_state_atom
*next
, *prev
;
238 const char *name
; /* for debug */
239 int cmd_size
; /* maximum size in dwords */
240 GLuint idx
; /* index in an array (e.g. textures) */
244 int (*check
) (r300ContextPtr
, struct r300_state_atom
* atom
);
247 #define R300_VPT_CMD_0 0
248 #define R300_VPT_XSCALE 1
249 #define R300_VPT_XOFFSET 2
250 #define R300_VPT_YSCALE 3
251 #define R300_VPT_YOFFSET 4
252 #define R300_VPT_ZSCALE 5
253 #define R300_VPT_ZOFFSET 6
254 #define R300_VPT_CMDSIZE 7
256 #define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
257 #define R300_VIR_CNTL_0 1
258 #define R300_VIR_CNTL_1 2
259 #define R300_VIR_CNTL_2 3
260 #define R300_VIR_CNTL_3 4
261 #define R300_VIR_CNTL_4 5
262 #define R300_VIR_CNTL_5 6
263 #define R300_VIR_CNTL_6 7
264 #define R300_VIR_CNTL_7 8
265 #define R300_VIR_CMDSIZE 9
267 #define R300_VIC_CMD_0 0
268 #define R300_VIC_CNTL_0 1
269 #define R300_VIC_CNTL_1 2
270 #define R300_VIC_CMDSIZE 3
272 #define R300_VOF_CMD_0 0
273 #define R300_VOF_CNTL_0 1
274 #define R300_VOF_CNTL_1 2
275 #define R300_VOF_CMDSIZE 3
277 #define R300_PVS_CMD_0 0
278 #define R300_PVS_CNTL_1 1
279 #define R300_PVS_CNTL_2 2
280 #define R300_PVS_CNTL_3 3
281 #define R300_PVS_CMDSIZE 4
283 #define R300_GB_MISC_CMD_0 0
284 #define R300_GB_MISC_MSPOS_0 1
285 #define R300_GB_MISC_MSPOS_1 2
286 #define R300_GB_MISC_TILE_CONFIG 3
287 #define R300_GB_MISC_SELECT 4
288 #define R300_GB_MISC_AA_CONFIG 5
289 #define R300_GB_MISC_CMDSIZE 6
291 #define R300_TXE_CMD_0 0
292 #define R300_TXE_ENABLE 1
293 #define R300_TXE_CMDSIZE 2
295 #define R300_PS_CMD_0 0
296 #define R300_PS_POINTSIZE 1
297 #define R300_PS_CMDSIZE 2
299 #define R300_ZBS_CMD_0 0
300 #define R300_ZBS_T_FACTOR 1
301 #define R300_ZBS_T_CONSTANT 2
302 #define R300_ZBS_W_FACTOR 3
303 #define R300_ZBS_W_CONSTANT 4
304 #define R300_ZBS_CMDSIZE 5
306 #define R300_CUL_CMD_0 0
307 #define R300_CUL_CULL 1
308 #define R300_CUL_CMDSIZE 2
310 #define R300_RC_CMD_0 0
311 #define R300_RC_CNTL_0 1
312 #define R300_RC_CNTL_1 2
313 #define R300_RC_CMDSIZE 3
315 #define R300_RI_CMD_0 0
316 #define R300_RI_INTERP_0 1
317 #define R300_RI_INTERP_1 2
318 #define R300_RI_INTERP_2 3
319 #define R300_RI_INTERP_3 4
320 #define R300_RI_INTERP_4 5
321 #define R300_RI_INTERP_5 6
322 #define R300_RI_INTERP_6 7
323 #define R300_RI_INTERP_7 8
324 #define R300_RI_CMDSIZE 9
326 #define R500_RI_CMDSIZE 17
328 #define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
329 #define R300_RR_INST_0 1
330 #define R300_RR_INST_1 2
331 #define R300_RR_INST_2 3
332 #define R300_RR_INST_3 4
333 #define R300_RR_INST_4 5
334 #define R300_RR_INST_5 6
335 #define R300_RR_INST_6 7
336 #define R300_RR_INST_7 8
337 #define R300_RR_CMDSIZE 9
339 #define R300_FP_CMD_0 0
340 #define R300_FP_CNTL0 1
341 #define R300_FP_CNTL1 2
342 #define R300_FP_CNTL2 3
343 #define R300_FP_CMD_1 4
344 #define R300_FP_NODE0 5
345 #define R300_FP_NODE1 6
346 #define R300_FP_NODE2 7
347 #define R300_FP_NODE3 8
348 #define R300_FP_CMDSIZE 9
350 #define R500_FP_CMD_0 0
351 #define R500_FP_CNTL 1
352 #define R500_FP_PIXSIZE 2
353 #define R500_FP_CMD_1 3
354 #define R500_FP_CODE_ADDR 4
355 #define R500_FP_CODE_RANGE 5
356 #define R500_FP_CODE_OFFSET 6
357 #define R500_FP_CMD_2 7
358 #define R500_FP_FC_CNTL 8
359 #define R500_FP_CMDSIZE 9
361 #define R300_FPT_CMD_0 0
362 #define R300_FPT_INSTR_0 1
363 #define R300_FPT_CMDSIZE 65
365 #define R300_FPI_CMD_0 0
366 #define R300_FPI_INSTR_0 1
367 #define R300_FPI_CMDSIZE 65
368 /* R500 has space for 512 instructions - 6 dwords per instruction */
369 #define R500_FPI_CMDSIZE (512*6+1)
371 #define R300_FPP_CMD_0 0
372 #define R300_FPP_PARAM_0 1
373 #define R300_FPP_CMDSIZE (32*4+1)
374 /* R500 has spcae for 256 constants - 4 dwords per constant */
375 #define R500_FPP_CMDSIZE (256*4+1)
377 #define R300_FOGS_CMD_0 0
378 #define R300_FOGS_STATE 1
379 #define R300_FOGS_CMDSIZE 2
381 #define R300_FOGC_CMD_0 0
382 #define R300_FOGC_R 1
383 #define R300_FOGC_G 2
384 #define R300_FOGC_B 3
385 #define R300_FOGC_CMDSIZE 4
387 #define R300_FOGP_CMD_0 0
388 #define R300_FOGP_SCALE 1
389 #define R300_FOGP_START 2
390 #define R300_FOGP_CMDSIZE 3
392 #define R300_AT_CMD_0 0
393 #define R300_AT_ALPHA_TEST 1
394 #define R300_AT_UNKNOWN 2
395 #define R300_AT_CMDSIZE 3
397 #define R300_BLD_CMD_0 0
398 #define R300_BLD_CBLEND 1
399 #define R300_BLD_ABLEND 2
400 #define R300_BLD_CMDSIZE 3
402 #define R300_CMK_CMD_0 0
403 #define R300_CMK_COLORMASK 1
404 #define R300_CMK_CMDSIZE 2
406 #define R300_CB_CMD_0 0
407 #define R300_CB_OFFSET 1
408 #define R300_CB_CMD_1 2
409 #define R300_CB_PITCH 3
410 #define R300_CB_CMDSIZE 4
412 #define R300_ZS_CMD_0 0
413 #define R300_ZS_CNTL_0 1
414 #define R300_ZS_CNTL_1 2
415 #define R300_ZS_CNTL_2 3
416 #define R300_ZS_CMDSIZE 4
418 #define R300_ZB_CMD_0 0
419 #define R300_ZB_OFFSET 1
420 #define R300_ZB_PITCH 2
421 #define R300_ZB_CMDSIZE 3
423 #define R300_VAP_CNTL_FLUSH 0
424 #define R300_VAP_CNTL_FLUSH_1 1
425 #define R300_VAP_CNTL_CMD 2
426 #define R300_VAP_CNTL_INSTR 3
427 #define R300_VAP_CNTL_SIZE 4
429 #define R300_VPI_CMD_0 0
430 #define R300_VPI_INSTR_0 1
431 #define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
433 #define R300_VPP_CMD_0 0
434 #define R300_VPP_PARAM_0 1
435 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
437 #define R300_VPUCP_CMD_0 0
438 #define R300_VPUCP_X 1
439 #define R300_VPUCP_Y 2
440 #define R300_VPUCP_Z 3
441 #define R300_VPUCP_W 4
442 #define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
444 #define R300_VPS_CMD_0 0
445 #define R300_VPS_ZERO_0 1
446 #define R300_VPS_ZERO_1 2
447 #define R300_VPS_POINTSIZE 3
448 #define R300_VPS_ZERO_3 4
449 #define R300_VPS_CMDSIZE 5
451 /* the layout is common for all fields inside tex */
452 #define R300_TEX_CMD_0 0
453 #define R300_TEX_VALUE_0 1
454 /* We don't really use this, instead specify mtu+1 dynamically
455 #define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
459 * Cache for hardware register state.
461 struct r300_hw_state
{
462 struct r300_state_atom atomlist
;
466 int max_state_size
; /* in dwords */
468 struct r300_state_atom vpt
; /* viewport (1D98) */
469 struct r300_state_atom vap_cntl
;
470 struct r300_state_atom vap_index_offset
; /* 0x208c r5xx only */
471 struct r300_state_atom vof
; /* VAP output format register 0x2090 */
472 struct r300_state_atom vte
; /* (20B0) */
473 struct r300_state_atom vap_vf_max_vtx_indx
; /* Maximum Vertex Indx Clamp (2134) */
474 struct r300_state_atom vap_cntl_status
;
475 struct r300_state_atom vir
[2]; /* vap input route (2150/21E0) */
476 struct r300_state_atom vic
; /* vap input control (2180) */
477 struct r300_state_atom vap_psc_sgn_norm_cntl
; /* Programmable Stream Control Signed Normalize Control (21DC) */
478 struct r300_state_atom vap_clip_cntl
;
479 struct r300_state_atom vap_clip
;
480 struct r300_state_atom vap_pvs_vtx_timeout_reg
; /* Vertex timeout register (2288) */
481 struct r300_state_atom pvs
; /* pvs_cntl (22D0) */
482 struct r300_state_atom gb_enable
; /* (4008) */
483 struct r300_state_atom gb_misc
; /* Multisampling position shifts ? (4010) */
484 struct r300_state_atom ga_point_s0
; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
485 struct r300_state_atom ga_triangle_stipple
; /* (4214) */
486 struct r300_state_atom ps
; /* pointsize (421C) */
487 struct r300_state_atom ga_point_minmax
; /* (4230) */
488 struct r300_state_atom lcntl
; /* line control */
489 struct r300_state_atom ga_line_stipple
; /* (4260) */
490 struct r300_state_atom shade
;
491 struct r300_state_atom polygon_mode
;
492 struct r300_state_atom fogp
; /* fog parameters (4294) */
493 struct r300_state_atom ga_soft_reset
; /* (429C) */
494 struct r300_state_atom zbias_cntl
;
495 struct r300_state_atom zbs
; /* zbias (42A4) */
496 struct r300_state_atom occlusion_cntl
;
497 struct r300_state_atom cul
; /* cull cntl (42B8) */
498 struct r300_state_atom su_depth_scale
; /* (42C0) */
499 struct r300_state_atom rc
; /* rs control (4300) */
500 struct r300_state_atom ri
; /* rs interpolators (4310) */
501 struct r300_state_atom rr
; /* rs route (4330) */
502 struct r300_state_atom sc_hyperz
; /* (43A4) */
503 struct r300_state_atom sc_screendoor
; /* (43E8) */
504 struct r300_state_atom fp
; /* fragment program cntl + nodes (4600) */
505 struct r300_state_atom fpt
; /* texi - (4620) */
506 struct r300_state_atom us_out_fmt
; /* (46A4) */
507 struct r300_state_atom r500fp
; /* r500 fp instructions */
508 struct r300_state_atom r500fp_const
; /* r500 fp constants */
509 struct r300_state_atom fpi
[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
510 struct r300_state_atom fogs
; /* fog state (4BC0) */
511 struct r300_state_atom fogc
; /* fog color (4BC8) */
512 struct r300_state_atom at
; /* alpha test (4BD4) */
513 struct r300_state_atom fg_depth_src
; /* (4BD8) */
514 struct r300_state_atom fpp
; /* 0x4C00 and following */
515 struct r300_state_atom rb3d_cctl
; /* (4E00) */
516 struct r300_state_atom bld
; /* blending (4E04) */
517 struct r300_state_atom cmk
; /* colormask (4E0C) */
518 struct r300_state_atom blend_color
; /* constant blend color */
519 struct r300_state_atom cb
; /* colorbuffer (4E28) */
520 struct r300_state_atom rb3d_dither_ctl
; /* (4E50) */
521 struct r300_state_atom rb3d_aaresolve_ctl
; /* (4E88) */
522 struct r300_state_atom rb3d_discard_src_pixel_lte_threshold
; /* (4E88) I saw it only written on RV350 hardware.. */
523 struct r300_state_atom zs
; /* zstencil control (4F00) */
524 struct r300_state_atom zstencil_format
;
525 struct r300_state_atom zb
; /* z buffer (4F20) */
526 struct r300_state_atom zb_depthclearvalue
; /* (4F28) */
527 struct r300_state_atom unk4F30
; /* (4F30) */
528 struct r300_state_atom zb_hiz_offset
; /* (4F44) */
529 struct r300_state_atom zb_hiz_pitch
; /* (4F54) */
531 struct r300_state_atom vpi
; /* vp instructions */
532 struct r300_state_atom vpp
; /* vp parameters */
533 struct r300_state_atom vps
; /* vertex point size (?) */
534 struct r300_state_atom vpucp
[6]; /* vp user clip plane - 6 */
535 /* 8 texture units */
536 /* the state is grouped by function and not by
537 texture unit. This makes single unit updates
538 really awkward - we are much better off
539 updating the whole thing at once */
541 struct r300_state_atom filter
;
542 struct r300_state_atom filter_1
;
543 struct r300_state_atom size
;
544 struct r300_state_atom format
;
545 struct r300_state_atom pitch
;
546 struct r300_state_atom offset
;
547 struct r300_state_atom chroma_key
;
548 struct r300_state_atom border_color
;
550 struct r300_state_atom txe
; /* tex enable (4104) */
554 * This structure holds the command buffer while it is being constructed.
556 * The first batch of commands in the buffer is always the state that needs
557 * to be re-emitted when the context is lost. This batch can be skipped
561 int size
; /* DWORDs allocated for buffer */
563 int count_used
; /* DWORDs filled so far */
564 int count_reemit
; /* size of re-emission batch */
571 struct r300_depthbuffer_state
{
575 struct r300_stencilbuffer_state
{
576 GLboolean hw_stencil
;
579 /* Vertex shader state */
581 /* Perhaps more if we store programs in vmem? */
582 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
583 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
585 /* Can be tested with colormat currently. */
586 #define VSF_MAX_FRAGMENT_TEMPS (14)
588 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
589 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
591 struct r300_vertex_shader_fragment
{
594 GLuint d
[VSF_MAX_FRAGMENT_LENGTH
];
595 float f
[VSF_MAX_FRAGMENT_LENGTH
];
596 GLuint i
[VSF_MAX_FRAGMENT_LENGTH
];
600 struct r300_vertex_shader_state
{
601 struct r300_vertex_shader_fragment program
;
604 extern int hw_tcl_on
;
606 #define COLOR_IS_RGBA
607 #define TAG(x) r300##x
608 #include "tnl_dd/t_dd_vertex.h"
611 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
612 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
614 /* Should but doesnt work */
615 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
617 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
618 * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
621 struct r300_vertex_program_key
{
623 GLuint OutputsWritten
;
627 struct r300_vertex_program
{
628 struct r300_vertex_program
*next
;
629 struct r300_vertex_program_key key
;
632 struct r300_vertex_shader_fragment program
;
635 int num_temporaries
; /* Number of temp vars used by program */
637 int inputs
[VERT_ATTRIB_MAX
];
638 int outputs
[VERT_RESULT_MAX
];
644 struct r300_vertex_program_cont
{
645 struct gl_vertex_program mesa_program
; /* Must be first */
646 struct r300_vertex_shader_fragment params
;
647 struct r300_vertex_program
*progs
;
650 #define PFS_MAX_ALU_INST 64
651 #define PFS_MAX_TEX_INST 64
652 #define PFS_MAX_TEX_INDIRECT 4
653 #define PFS_NUM_TEMP_REGS 32
654 #define PFS_NUM_CONST_REGS 16
656 struct r300_pfs_compile_state
;
660 * Stores state that influences the compilation of a fragment program.
662 struct r300_fragment_program_external_state
{
665 * If the sampler is used as a shadow sampler,
670 * depending on the depth texture mode.
672 GLuint depth_texture_mode
: 2;
675 * If the sampler is used as a shadow sampler,
676 * this field is (texture_compare_func - GL_NEVER).
677 * [e.g. if compare function is GL_LEQUAL, this field is 3]
679 * Otherwise, this field is 0.
681 GLuint texture_compare_func
: 3;
687 * Stores an R300 fragment program in its compiled-to-hardware form.
689 struct r300_fragment_program_code
{
692 GLuint inst
[PFS_MAX_TEX_INST
];
701 } inst
[PFS_MAX_ALU_INST
];
712 int first_node_has_tex
;
720 * Remember which program register a given hardware constant
723 struct prog_src_register constant
[PFS_NUM_CONST_REGS
];
730 * Store everything about a fragment program that is needed
731 * to render with that program.
733 struct r300_fragment_program
{
734 struct gl_fragment_program mesa_program
;
736 GLboolean translated
;
739 struct r300_fragment_program_external_state state
;
740 struct r300_fragment_program_code code
;
742 GLboolean WritesDepth
;
746 struct r500_pfs_compile_state
;
748 struct r500_fragment_program_external_state
{
751 * If the sampler is used as a shadow sampler,
756 * depending on the depth texture mode.
758 GLuint depth_texture_mode
: 2;
761 * If the sampler is used as a shadow sampler,
762 * this field is (texture_compare_func - GL_NEVER).
763 * [e.g. if compare function is GL_LEQUAL, this field is 3]
765 * Otherwise, this field is 0.
767 GLuint texture_compare_func
: 3;
771 struct r500_fragment_program_code
{
780 /* TODO: This is magic! */
788 * Remember which program register a given hardware constant
791 struct prog_src_register constant
[PFS_NUM_CONST_REGS
];
797 struct r500_fragment_program
{
798 struct gl_fragment_program mesa_program
;
801 GLboolean translated
;
804 struct r500_fragment_program_external_state state
;
805 struct r500_fragment_program_code code
;
807 GLboolean writes_depth
;
812 #define R300_MAX_AOS_ARRAYS 16
819 struct r300_depthbuffer_state depth
;
820 struct r300_texture_state texture
;
821 int sw_tcl_inputs
[VERT_ATTRIB_MAX
];
822 struct r300_vertex_shader_state vertex_shader
;
823 struct r300_dma_region aos
[R300_MAX_AOS_ARRAYS
];
827 struct r300_dma_region elt_dma
;
829 struct r300_dma_region swtcl_dma
;
830 DECLARE_RENDERINPUTS(render_inputs_bitset
); /* actual render inputs that R300 was configured for.
831 They are the same as tnl->render_inputs for fixed pipeline */
833 struct r300_stencilbuffer_state stencil
;
837 #define R300_FALLBACK_NONE 0
838 #define R300_FALLBACK_TCL 1
839 #define R300_FALLBACK_RAST 2
843 struct r300_swtcl_info
{
847 * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is
848 * installed in the Mesa state vector.
853 * Attributes instructing the Mesa TCL pipeline where / how to put vertex
854 * data in the hardware buffer.
856 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
859 * Number of elements of \c ::vertex_attrs that are actually used.
861 GLuint vertex_attr_count
;
864 * Cached pointer to the buffer where Mesa will store vertex data.
868 /* Fallback rasterization functions
870 // r200_point_func draw_point;
871 // r200_line_func draw_line;
872 // r200_tri_func draw_tri;
875 GLenum render_primitive
;
879 * Offset of the 4UB color data within a hardware (swtcl) vertex.
884 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
889 * Should Mesa project vertex data or will the hardware do it?
893 struct r300_dma_region indexed_verts
;
898 * \brief R300 context structure.
900 struct r300_context
{
901 struct radeon_context radeon
; /* parent class, must be first */
903 struct r300_hw_state hw
;
904 struct r300_cmdbuf cmdbuf
;
905 struct r300_state state
;
906 struct gl_vertex_program
*curr_vp
;
907 struct r300_vertex_program
*selected_vp
;
912 GLboolean save_on_next_unlock
;
915 /* Texture object bookkeeping
918 driTexHeap
*texture_heaps
[RADEON_NR_TEX_HEAPS
];
919 driTextureObject swapped
;
921 float initialMaxAnisotropy
;
923 /* Clientdata textures;
925 GLuint prefer_gart_client_texturing
;
928 struct r300_memory_manager
*rmm
;
931 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
932 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
934 GLboolean disable_lowimpact_fallback
;
936 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
937 struct r300_swtcl_info swtcl
;
940 struct r300_buffer_object
{
941 struct gl_buffer_object mesa_obj
;
945 #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
947 extern void r300DestroyContext(__DRIcontextPrivate
* driContextPriv
);
948 extern GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
949 __DRIcontextPrivate
* driContextPriv
,
950 void *sharedContextPrivate
);
952 extern void r300SelectVertexShader(r300ContextPtr r300
);
953 extern void r300InitShaderFuncs(struct dd_function_table
*functions
);
954 extern int r300VertexProgUpdateParams(GLcontext
* ctx
,
955 struct r300_vertex_program_cont
*vp
,
958 #define RADEON_D_CAPTURE 0
959 #define RADEON_D_PLAYBACK 1
960 #define RADEON_D_PLAYBACK_RAW 2
963 #endif /* __R300_CONTEXT_H__ */