src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45
  46 #include "macros.h"
  47 #include "mtypes.h"
  48 #include "colormac.h"
  49 #include "radeon_context.h"
  50
  51 #define USER_BUFFERS
  52
  53 /* We don't handle 16 bits elts swapping yet */
  54 #ifdef MESA_BIG_ENDIAN
  55 #define FORCE_32BITS_ELTS
  56 #endif
  57
  58 //#define OPTIMIZE_ELTS
  59
  60 struct r300_context;
  61 typedef struct r300_context r300ContextRec;
  62 typedef struct r300_context *r300ContextPtr;
  63
  64 #include "radeon_lock.h"
  65 #include "mm.h"
  66
  67 /* Checkpoint.. for convenience */
  68 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  69 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  70    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  71    with other compilers ... GLUE!
  72 */
  73 #if 1
  74 #define WARN_ONCE(a, ...)       { \
  75         static int warn##__LINE__=1; \
  76         if(warn##__LINE__){ \
  77                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  78                 fprintf(stderr, "File %s function %s line %d\n", \
  79                         __FILE__, __FUNCTION__, __LINE__); \
  80                 fprintf(stderr,  a, ## __VA_ARGS__);\
  81                 fprintf(stderr, "***************************************************************************\n"); \
  82                 warn##__LINE__=0;\
  83                 } \
  84         }
  85 #else
  86 #define WARN_ONCE(a, ...) {}
  87 #endif
  88
  89 #include "r300_vertprog.h"
  90 #include "r300_fragprog.h"
  91
  92 /**
  93  * This function takes a float and packs it into a uint32_t
  94  */
  95 static __inline__ uint32_t r300PackFloat32(float fl)
  96 {
  97         union {
  98                 float fl;
  99                 uint32_t u;
 100         } u;
 101
 102         u.fl = fl;
 103         return u.u;
 104 }
 105
 106 /************ DMA BUFFERS **************/
 107
 108 /* Need refcounting on dma buffers:
 109  */
 110 struct r300_dma_buffer {
 111         int refcount;           /**< the number of retained regions in buf */
 112         drmBufPtr buf;
 113         int id;
 114 };
 115 #undef GET_START
 116 #ifdef USER_BUFFERS
 117 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 118 #else
 119 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 120                         (rvb)->address - rmesa->dma.buf0_address +      \
 121                         (rvb)->start)
 122 #endif
 123 /* A retained region, eg vertices for indexed vertices.
 124  */
 125 struct r300_dma_region {
 126         struct r300_dma_buffer *buf;
 127         char *address;          /* == buf->address */
 128         int start, end, ptr;    /* offsets from start of buf */
 129
 130         int aos_offset;         /* address in GART memory */
 131         int aos_stride;         /* distance between elements, in dwords */
 132         int aos_size;           /* number of components (1-4) */
 133         int aos_reg;            /* VAP register assignment */
 134 };
 135
 136 struct r300_dma {
 137         /* Active dma region.  Allocations for vertices and retained
 138          * regions come from here.  Also used for emitting random vertices,
 139          * these may be flushed by calling flush_current();
 140          */
 141         struct r300_dma_region current;
 142
 143         void (*flush) (r300ContextPtr);
 144
 145         char *buf0_address;     /* start of buf[0], for index calcs */
 146
 147         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 148          * for which a DISCARD command is currently queued in the command buffer.
 149          */
 150         GLuint nr_released_bufs;
 151 };
 152
 153        /* Texture related */
 154
 155 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 156
 157 /* Texture object in locally shared texture space.
 158  */
 159 struct r300_tex_obj {
 160         driTextureObject base;
 161
 162         GLuint bufAddr;         /* Offset to start of locally
 163                                    shared texture block */
 164
 165         GLuint dirty_state;     /* Flags (1 per texunit) for
 166                                    whether or not this texobj
 167                                    has dirty hardware state
 168                                    (pp_*) that needs to be
 169                                    brought into the
 170                                    texunit. */
 171
 172         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 173         /* Six, for the cube faces */
 174
 175         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 176         /* hardware register values */
 177         /* Note that R200 has 8 registers per texture and R300 only 7 */
 178         GLuint filter;
 179         GLuint filter_1;
 180         GLuint pitch_reg;
 181         GLuint size;            /* npot only */
 182         GLuint format;
 183         GLuint offset;          /* Image location in the card's address space.
 184                                    All cube faces follow. */
 185         GLuint unknown4;
 186         GLuint unknown5;
 187         /* end hardware registers */
 188
 189         /* registers computed by r200 code - keep them here to
 190            compare against what is actually written.
 191
 192            to be removed later.. */
 193         GLuint pp_border_color;
 194         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 195         GLuint format_x;
 196
 197         GLboolean border_fallback;
 198
 199         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 200 };
 201
 202 struct r300_texture_env_state {
 203         r300TexObjPtr texobj;
 204         GLenum format;
 205         GLenum envMode;
 206 };
 207
 208 /* The blit width for texture uploads
 209  */
 210 #define R300_BLIT_WIDTH_BYTES 1024
 211 #define R300_MAX_TEXTURE_UNITS 8
 212
 213 struct r300_texture_state {
 214         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 215         int tc_count;           /* number of incoming texture coordinates from VAP */
 216 };
 217
 218 /**
 219  * A block of hardware state.
 220  *
 221  * When check returns non-zero, the returned number of dwords must be
 222  * copied verbatim into the command buffer in order to update a state atom
 223  * when it is dirty.
 224  */
 225 struct r300_state_atom {
 226         struct r300_state_atom *next, *prev;
 227         const char *name;       /* for debug */
 228         int cmd_size;           /* maximum size in dwords */
 229         GLuint idx;             /* index in an array (e.g. textures) */
 230         uint32_t *cmd;
 231         GLboolean dirty;
 232
 233         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 234 };
 235
 236 #define R300_VPT_CMD_0          0
 237 #define R300_VPT_XSCALE         1
 238 #define R300_VPT_XOFFSET        2
 239 #define R300_VPT_YSCALE         3
 240 #define R300_VPT_YOFFSET        4
 241 #define R300_VPT_ZSCALE         5
 242 #define R300_VPT_ZOFFSET        6
 243 #define R300_VPT_CMDSIZE        7
 244
 245 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 246 #define R300_VIR_CNTL_0         1
 247 #define R300_VIR_CNTL_1         2
 248 #define R300_VIR_CNTL_2         3
 249 #define R300_VIR_CNTL_3         4
 250 #define R300_VIR_CNTL_4         5
 251 #define R300_VIR_CNTL_5         6
 252 #define R300_VIR_CNTL_6         7
 253 #define R300_VIR_CNTL_7         8
 254 #define R300_VIR_CMDSIZE        9
 255
 256 #define R300_VIC_CMD_0          0
 257 #define R300_VIC_CNTL_0         1
 258 #define R300_VIC_CNTL_1         2
 259 #define R300_VIC_CMDSIZE        3
 260
 261 #define R300_VOF_CMD_0          0
 262 #define R300_VOF_CNTL_0         1
 263 #define R300_VOF_CNTL_1         2
 264 #define R300_VOF_CMDSIZE        3
 265
 266 #define R300_PVS_CMD_0          0
 267 #define R300_PVS_CNTL_1         1
 268 #define R300_PVS_CNTL_2         2
 269 #define R300_PVS_CNTL_3         3
 270 #define R300_PVS_CMDSIZE        4
 271
 272 #define R300_GB_MISC_CMD_0              0
 273 #define R300_GB_MISC_MSPOS_0            1
 274 #define R300_GB_MISC_MSPOS_1            2
 275 #define R300_GB_MISC_TILE_CONFIG        3
 276 #define R300_GB_MISC_SELECT             4
 277 #define R300_GB_MISC_AA_CONFIG          5
 278 #define R300_GB_MISC_CMDSIZE            6
 279
 280 #define R300_TXE_CMD_0          0
 281 #define R300_TXE_ENABLE         1
 282 #define R300_TXE_CMDSIZE        2
 283
 284 #define R300_PS_CMD_0           0
 285 #define R300_PS_POINTSIZE       1
 286 #define R300_PS_CMDSIZE         2
 287
 288 #define R300_ZBS_CMD_0          0
 289 #define R300_ZBS_T_FACTOR       1
 290 #define R300_ZBS_T_CONSTANT     2
 291 #define R300_ZBS_W_FACTOR       3
 292 #define R300_ZBS_W_CONSTANT     4
 293 #define R300_ZBS_CMDSIZE        5
 294
 295 #define R300_CUL_CMD_0          0
 296 #define R300_CUL_CULL           1
 297 #define R300_CUL_CMDSIZE        2
 298
 299 #define R300_RC_CMD_0           0
 300 #define R300_RC_CNTL_0          1
 301 #define R300_RC_CNTL_1          2
 302 #define R300_RC_CMDSIZE         3
 303
 304 #define R300_RI_CMD_0           0
 305 #define R300_RI_INTERP_0        1
 306 #define R300_RI_INTERP_1        2
 307 #define R300_RI_INTERP_2        3
 308 #define R300_RI_INTERP_3        4
 309 #define R300_RI_INTERP_4        5
 310 #define R300_RI_INTERP_5        6
 311 #define R300_RI_INTERP_6        7
 312 #define R300_RI_INTERP_7        8
 313 #define R300_RI_CMDSIZE         9
 314
 315 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 316 #define R300_RR_ROUTE_0         1
 317 #define R300_RR_ROUTE_1         2
 318 #define R300_RR_ROUTE_2         3
 319 #define R300_RR_ROUTE_3         4
 320 #define R300_RR_ROUTE_4         5
 321 #define R300_RR_ROUTE_5         6
 322 #define R300_RR_ROUTE_6         7
 323 #define R300_RR_ROUTE_7         8
 324 #define R300_RR_CMDSIZE         9
 325
 326 #define R300_FP_CMD_0           0
 327 #define R300_FP_CNTL0           1
 328 #define R300_FP_CNTL1           2
 329 #define R300_FP_CNTL2           3
 330 #define R300_FP_CMD_1           4
 331 #define R300_FP_NODE0           5
 332 #define R300_FP_NODE1           6
 333 #define R300_FP_NODE2           7
 334 #define R300_FP_NODE3           8
 335 #define R300_FP_CMDSIZE         9
 336
 337 #define R300_FPT_CMD_0          0
 338 #define R300_FPT_INSTR_0        1
 339 #define R300_FPT_CMDSIZE        65
 340
 341 #define R300_FPI_CMD_0          0
 342 #define R300_FPI_INSTR_0        1
 343 #define R300_FPI_CMDSIZE        65
 344
 345 #define R300_FPP_CMD_0          0
 346 #define R300_FPP_PARAM_0        1
 347 #define R300_FPP_CMDSIZE        (32*4+1)
 348
 349 #define R300_FOGS_CMD_0         0
 350 #define R300_FOGS_STATE         1
 351 #define R300_FOGS_CMDSIZE       2
 352
 353 #define R300_FOGC_CMD_0         0
 354 #define R300_FOGC_R             1
 355 #define R300_FOGC_G             2
 356 #define R300_FOGC_B             3
 357 #define R300_FOGC_CMDSIZE       4
 358
 359 #define R300_FOGP_CMD_0         0
 360 #define R300_FOGP_SCALE         1
 361 #define R300_FOGP_START         2
 362 #define R300_FOGP_CMDSIZE       3
 363
 364 #define R300_AT_CMD_0           0
 365 #define R300_AT_ALPHA_TEST      1
 366 #define R300_AT_UNKNOWN         2
 367 #define R300_AT_CMDSIZE         3
 368
 369 #define R300_BLD_CMD_0          0
 370 #define R300_BLD_CBLEND         1
 371 #define R300_BLD_ABLEND         2
 372 #define R300_BLD_CMDSIZE        3
 373
 374 #define R300_CMK_CMD_0          0
 375 #define R300_CMK_COLORMASK      1
 376 #define R300_CMK_CMDSIZE        2
 377
 378 #define R300_CB_CMD_0           0
 379 #define R300_CB_OFFSET          1
 380 #define R300_CB_CMD_1           2
 381 #define R300_CB_PITCH           3
 382 #define R300_CB_CMDSIZE         4
 383
 384 #define R300_ZS_CMD_0           0
 385 #define R300_ZS_CNTL_0          1
 386 #define R300_ZS_CNTL_1          2
 387 #define R300_ZS_CNTL_2          3
 388 #define R300_ZS_CMDSIZE         4
 389
 390 #define R300_ZB_CMD_0           0
 391 #define R300_ZB_OFFSET          1
 392 #define R300_ZB_PITCH           2
 393 #define R300_ZB_CMDSIZE         3
 394
 395 #define R300_VPI_CMD_0          0
 396 #define R300_VPI_INSTR_0        1
 397 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 398
 399 #define R300_VPP_CMD_0          0
 400 #define R300_VPP_PARAM_0        1
 401 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 402
 403 #define R300_VPS_CMD_0          0
 404 #define R300_VPS_ZERO_0         1
 405 #define R300_VPS_ZERO_1         2
 406 #define R300_VPS_POINTSIZE      3
 407 #define R300_VPS_ZERO_3         4
 408 #define R300_VPS_CMDSIZE        5
 409
 410         /* the layout is common for all fields inside tex */
 411 #define R300_TEX_CMD_0          0
 412 #define R300_TEX_VALUE_0        1
 413 /* We don't really use this, instead specify mtu+1 dynamically
 414 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 415 */
 416
 417 /**
 418  * Cache for hardware register state.
 419  */
 420 struct r300_hw_state {
 421         struct r300_state_atom atomlist;
 422
 423         GLboolean is_dirty;
 424         GLboolean all_dirty;
 425         int max_state_size;     /* in dwords */
 426
 427         struct r300_state_atom vpt;     /* viewport (1D98) */
 428         struct r300_state_atom vap_cntl;
 429         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 430         struct r300_state_atom vte;     /* (20B0) */
 431         struct r300_state_atom unk2134; /* (2134) */
 432         struct r300_state_atom vap_cntl_status;
 433         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 434         struct r300_state_atom vic;     /* vap input control (2180) */
 435         struct r300_state_atom unk21DC; /* (21DC) */
 436         struct r300_state_atom unk221C; /* (221C) */
 437         struct r300_state_atom unk2220; /* (2220) */
 438         struct r300_state_atom unk2288; /* (2288) */
 439         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 440         struct r300_state_atom gb_enable;       /* (4008) */
 441         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 442         struct r300_state_atom unk4200; /* (4200) */
 443         struct r300_state_atom unk4214; /* (4214) */
 444         struct r300_state_atom ps;      /* pointsize (421C) */
 445         struct r300_state_atom unk4230; /* (4230) */
 446         struct r300_state_atom lcntl;   /* line control */
 447         struct r300_state_atom unk4260; /* (4260) */
 448         struct r300_state_atom shade;
 449         struct r300_state_atom polygon_mode;
 450         struct r300_state_atom fogp;    /* fog parameters (4294) */
 451         struct r300_state_atom unk429C; /* (429C) */
 452         struct r300_state_atom zbias_cntl;
 453         struct r300_state_atom zbs;     /* zbias (42A4) */
 454         struct r300_state_atom occlusion_cntl;
 455         struct r300_state_atom cul;     /* cull cntl (42B8) */
 456         struct r300_state_atom unk42C0; /* (42C0) */
 457         struct r300_state_atom rc;      /* rs control (4300) */
 458         struct r300_state_atom ri;      /* rs interpolators (4310) */
 459         struct r300_state_atom rr;      /* rs route (4330) */
 460         struct r300_state_atom unk43A4; /* (43A4) */
 461         struct r300_state_atom unk43E8; /* (43E8) */
 462         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 463         struct r300_state_atom fpt;     /* texi - (4620) */
 464         struct r300_state_atom unk46A4; /* (46A4) */
 465         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 466         struct r300_state_atom fogs;    /* fog state (4BC0) */
 467         struct r300_state_atom fogc;    /* fog color (4BC8) */
 468         struct r300_state_atom at;      /* alpha test (4BD4) */
 469         struct r300_state_atom unk4BD8; /* (4BD8) */
 470         struct r300_state_atom fpp;     /* 0x4C00 and following */
 471         struct r300_state_atom unk4E00; /* (4E00) */
 472         struct r300_state_atom bld;     /* blending (4E04) */
 473         struct r300_state_atom cmk;     /* colormask (4E0C) */
 474         struct r300_state_atom blend_color;     /* constant blend color */
 475         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 476         struct r300_state_atom unk4E50; /* (4E50) */
 477         struct r300_state_atom unk4E88; /* (4E88) */
 478         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 479         struct r300_state_atom zs;      /* zstencil control (4F00) */
 480         struct r300_state_atom zstencil_format;
 481         struct r300_state_atom zb;      /* z buffer (4F20) */
 482         struct r300_state_atom unk4F28; /* (4F28) */
 483         struct r300_state_atom unk4F30; /* (4F30) */
 484         struct r300_state_atom unk4F44; /* (4F44) */
 485         struct r300_state_atom unk4F54; /* (4F54) */
 486
 487         struct r300_state_atom vpi;     /* vp instructions */
 488         struct r300_state_atom vpp;     /* vp parameters */
 489         struct r300_state_atom vps;     /* vertex point size (?) */
 490         /* 8 texture units */
 491         /* the state is grouped by function and not by
 492            texture unit. This makes single unit updates
 493            really awkward - we are much better off
 494            updating the whole thing at once */
 495         struct {
 496                 struct r300_state_atom filter;
 497                 struct r300_state_atom filter_1;
 498                 struct r300_state_atom size;
 499                 struct r300_state_atom format;
 500                 struct r300_state_atom pitch;
 501                 struct r300_state_atom offset;
 502                 struct r300_state_atom chroma_key;
 503                 struct r300_state_atom border_color;
 504         } tex;
 505         struct r300_state_atom txe;     /* tex enable (4104) */
 506 };
 507
 508 /**
 509  * This structure holds the command buffer while it is being constructed.
 510  *
 511  * The first batch of commands in the buffer is always the state that needs
 512  * to be re-emitted when the context is lost. This batch can be skipped
 513  * otherwise.
 514  */
 515 struct r300_cmdbuf {
 516         int size;               /* DWORDs allocated for buffer */
 517         uint32_t *cmd_buf;
 518         int count_used;         /* DWORDs filled so far */
 519         int count_reemit;       /* size of re-emission batch */
 520 };
 521
 522 /**
 523  * State cache
 524  */
 525
 526 struct r300_depthbuffer_state {
 527         GLfloat scale;
 528 };
 529
 530 struct r300_stencilbuffer_state {
 531         GLuint clear;
 532         GLboolean hw_stencil;
 533
 534 };
 535
 536 /* Vertex shader state */
 537
 538 /* Perhaps more if we store programs in vmem? */
 539 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 540 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 541
 542 /* Can be tested with colormat currently. */
 543 #define VSF_MAX_FRAGMENT_TEMPS (14)
 544
 545 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 546 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 547
 548 struct r300_vertex_shader_fragment {
 549         int length;
 550         union {
 551                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 552                 float f[VSF_MAX_FRAGMENT_LENGTH];
 553                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH / 4];
 554         } body;
 555 };
 556
 557 #define VSF_DEST_PROGRAM        0x0
 558 #define VSF_DEST_MATRIX0        0x200
 559 #define VSF_DEST_MATRIX1        0x204
 560 #define VSF_DEST_MATRIX2        0x208
 561 #define VSF_DEST_VECTOR0        0x20c
 562 #define VSF_DEST_VECTOR1        0x20d
 563 #define VSF_DEST_UNKNOWN1       0x400
 564 #define VSF_DEST_UNKNOWN2       0x406
 565
 566 struct r300_vertex_shader_state {
 567         struct r300_vertex_shader_fragment program;
 568
 569         struct r300_vertex_shader_fragment unknown1;
 570         struct r300_vertex_shader_fragment unknown2;
 571
 572         int program_start;
 573         int unknown_ptr1;       /* pointer within program space */
 574         int program_end;
 575
 576         int param_offset;
 577         int param_count;
 578
 579         int unknown_ptr2;       /* pointer within program space */
 580         int unknown_ptr3;       /* pointer within program space */
 581 };
 582
 583 extern int hw_tcl_on;
 584
 585 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 586 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 587
 588 /* Should but doesnt work */
 589 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 590
 591 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 592  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 593  */
 594
 595 struct r300_vertex_program_key {
 596         GLuint InputsRead;
 597         GLuint OutputsWritten;
 598 };
 599
 600 struct r300_vertex_program {
 601         struct r300_vertex_program *next;
 602         struct r300_vertex_program_key key;
 603         int translated;
 604
 605         struct r300_vertex_shader_fragment program;
 606
 607         int pos_end;
 608         int num_temporaries;    /* Number of temp vars used by program */
 609         int wpos_idx;
 610         int inputs[VERT_ATTRIB_MAX];
 611         int outputs[VERT_RESULT_MAX];
 612         int native;
 613         int ref_count;
 614         int use_ref_count;
 615 };
 616
 617 struct r300_vertex_program_cont {
 618         struct gl_vertex_program mesa_program;  /* Must be first */
 619         struct r300_vertex_shader_fragment params;
 620         struct r300_vertex_program *progs;
 621 };
 622
 623 #define PFS_MAX_ALU_INST        64
 624 #define PFS_MAX_TEX_INST        64
 625 #define PFS_MAX_TEX_INDIRECT 4
 626 #define PFS_NUM_TEMP_REGS       32
 627 #define PFS_NUM_CONST_REGS      16
 628
 629 /* Mapping Mesa registers to R300 temporaries */
 630 struct reg_acc {
 631         int reg;                /* Assigned hw temp */
 632         unsigned int refcount;  /* Number of uses by mesa program */
 633 };
 634
 635 /**
 636  * Describe the current lifetime information for an R300 temporary
 637  */
 638 struct reg_lifetime {
 639         /* Index of the first slot where this register is free in the sense
 640            that it can be used as a new destination register.
 641            This is -1 if the register has been assigned to a Mesa register
 642            and the last access to the register has not yet been emitted */
 643         int free;
 644
 645         /* Index of the first slot where this register is currently reserved.
 646            This is used to stop e.g. a scalar operation from being moved
 647            before the allocation time of a register that was first allocated
 648            for a vector operation. */
 649         int reserved;
 650
 651         /* Index of the first slot in which the register can be used as a
 652            source without losing the value that is written by the last
 653            emitted instruction that writes to the register */
 654         int vector_valid;
 655         int scalar_valid;
 656
 657         /* Index to the slot where the register was last read.
 658            This is also the first slot in which the register may be written again */
 659         int vector_lastread;
 660         int scalar_lastread;
 661 };
 662
 663 /**
 664  * Store usage information about an ALU instruction slot during the
 665  * compilation of a fragment program.
 666  */
 667 #define SLOT_SRC_VECTOR  (1<<0)
 668 #define SLOT_SRC_SCALAR  (1<<3)
 669 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 670 #define SLOT_OP_VECTOR   (1<<16)
 671 #define SLOT_OP_SCALAR   (1<<17)
 672 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 673
 674 struct r300_pfs_compile_slot {
 675         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 676            defined above */
 677         unsigned int used;
 678
 679         /* Selected sources */
 680         int vsrc[3];
 681         int ssrc[3];
 682 };
 683
 684 /**
 685  * Store information during compilation of fragment programs.
 686  */
 687 struct r300_pfs_compile_state {
 688         int nrslots;            /* number of ALU slots used so far */
 689
 690         /* Track which (parts of) slots are already filled with instructions */
 691         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 692
 693         /* Track the validity of R300 temporaries */
 694         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 695
 696         /* Used to map Mesa's inputs/temps onto hardware temps */
 697         int temp_in_use;
 698         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 699         struct reg_acc inputs[32];      /* don't actually need 32... */
 700
 701         /* Track usage of hardware temps, for register allocation,
 702          * indirection detection, etc. */
 703         GLuint used_in_node;
 704         GLuint dest_in_node;
 705 };
 706
 707 /**
 708  * Store everything about a fragment program that is needed
 709  * to render with that program.
 710  */
 711 struct r300_fragment_program {
 712         struct gl_fragment_program mesa_program;
 713
 714         GLcontext *ctx;
 715         GLboolean translated;
 716         GLboolean error;
 717         struct r300_pfs_compile_state *cs;
 718
 719         struct {
 720                 int length;
 721                 GLuint inst[PFS_MAX_TEX_INST];
 722         } tex;
 723
 724         struct {
 725                 struct {
 726                         GLuint inst0;
 727                         GLuint inst1;
 728                         GLuint inst2;
 729                         GLuint inst3;
 730                 } inst[PFS_MAX_ALU_INST];
 731         } alu;
 732
 733         struct {
 734                 int tex_offset;
 735                 int tex_end;
 736                 int alu_offset;
 737                 int alu_end;
 738                 int flags;
 739         } node[4];
 740         int cur_node;
 741         int first_node_has_tex;
 742
 743         int alu_offset;
 744         int alu_end;
 745         int tex_offset;
 746         int tex_end;
 747
 748         /* Hardware constants.
 749          * Contains a pointer to the value. The destination of the pointer
 750          * is supposed to be updated when GL state changes.
 751          * Typically, this is either a pointer into
 752          * gl_program_parameter_list::ParameterValues, or a pointer to a
 753          * global constant (e.g. for sin/cos-approximation)
 754          */
 755         const GLfloat *constant[PFS_NUM_CONST_REGS];
 756         int const_nr;
 757
 758         int max_temp_idx;
 759
 760         GLuint optimization;
 761 };
 762
 763 #define R300_MAX_AOS_ARRAYS             16
 764
 765 #define AOS_FORMAT_USHORT       0
 766 #define AOS_FORMAT_FLOAT        1
 767 #define AOS_FORMAT_UBYTE        2
 768 #define AOS_FORMAT_FLOAT_COLOR  3
 769
 770 #define REG_COORDS      0
 771 #define REG_COLOR0      1
 772 #define REG_TEX0        2
 773
 774 struct dt {
 775         GLint size;
 776         GLenum type;
 777         GLsizei stride;
 778         void *data;
 779 };
 780
 781 struct radeon_vertex_buffer {
 782         int Count;
 783         void *Elts;
 784         int elt_size;
 785         int elt_min, elt_max;   /* debug */
 786
 787         struct dt AttribPtr[VERT_ATTRIB_MAX];
 788
 789         const struct _mesa_prim *Primitive;
 790         GLuint PrimitiveCount;
 791         GLint LockFirst;
 792         GLsizei LockCount;
 793         int lock_uptodate;
 794 };
 795
 796 struct r300_aos_rec {
 797         GLuint offset;
 798         int element_size;       /* in dwords */
 799         int stride;             /* distance between elements, in dwords */
 800
 801         int format;
 802
 803         int ncomponents;        /* number of components - between 1 and 4, inclusive */
 804
 805         int reg;                /* which register they are assigned to. */
 806
 807 };
 808
 809 struct r300_state {
 810         struct r300_depthbuffer_state depth;
 811         struct r300_texture_state texture;
 812         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 813         struct r300_vertex_shader_state vertex_shader;
 814         struct r300_pfs_compile_state pfs_compile;
 815         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 816         int aos_count;
 817         struct radeon_vertex_buffer VB;
 818
 819         GLuint *Elts;
 820         struct r300_dma_region elt_dma;
 821
 822          DECLARE_RENDERINPUTS(render_inputs_bitset);    /* actual render inputs that R300 was configured for.
 823                                                            They are the same as tnl->render_inputs for fixed pipeline */
 824
 825         struct {
 826                 int transform_offset;   /* Transform matrix offset, -1 if none */
 827         } vap_param;            /* vertex processor parameter allocation - tells where to write parameters */
 828
 829         struct r300_stencilbuffer_state stencil;
 830
 831 };
 832
 833 #define R300_FALLBACK_NONE 0
 834 #define R300_FALLBACK_TCL 1
 835 #define R300_FALLBACK_RAST 2
 836
 837 /**
 838  * \brief R300 context structure.
 839  */
 840 struct r300_context {
 841         struct radeon_context radeon;   /* parent class, must be first */
 842
 843         struct r300_hw_state hw;
 844         struct r300_cmdbuf cmdbuf;
 845         struct r300_state state;
 846         struct gl_vertex_program *curr_vp;
 847         struct r300_vertex_program *selected_vp;
 848
 849         /* Vertex buffers
 850          */
 851         struct r300_dma dma;
 852         GLboolean save_on_next_unlock;
 853         GLuint NewGLState;
 854
 855         /* Texture object bookkeeping
 856          */
 857         unsigned nr_heaps;
 858         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 859         driTextureObject swapped;
 860         int texture_depth;
 861         float initialMaxAnisotropy;
 862
 863         /* Clientdata textures;
 864          */
 865         GLuint prefer_gart_client_texturing;
 866
 867 #ifdef USER_BUFFERS
 868         struct r300_memory_manager *rmm;
 869         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 870         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 871 #endif
 872
 873         GLboolean texmicrotile;
 874         GLboolean disable_lowimpact_fallback;
 875 };
 876
 877 struct r300_buffer_object {
 878         struct gl_buffer_object mesa_obj;
 879         int id;
 880 };
 881
 882 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 883
 884 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 885 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 886                                    __DRIcontextPrivate * driContextPriv,
 887                                    void *sharedContextPrivate);
 888
 889 extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
 890
 891 extern void r300SelectVertexShader(r300ContextPtr r300);
 892 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 893 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 894                                       struct r300_vertex_program_cont *vp,
 895                                       float *dst);
 896 extern int r300Fallback(GLcontext * ctx);
 897
 898 extern GLboolean r300RunRender(GLcontext * ctx,
 899                                struct tnl_pipeline_stage *stage);
 900
 901 #define RADEON_D_CAPTURE 0
 902 #define RADEON_D_PLAYBACK 1
 903 #define RADEON_D_PLAYBACK_RAW 2
 904 #define RADEON_D_T 3
 905
 906 #endif                          /* __R300_CONTEXT_H__ */