src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_bo.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 struct r300_context;
  52 typedef struct r300_context r300ContextRec;
  53 typedef struct r300_context *r300ContextPtr;
  54
  55 #include "radeon_lock.h"
  56 #include "main/mm.h"
  57
  58 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  59    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  60    with other compilers ... GLUE!
  61 */
  62 #define WARN_ONCE(a, ...)       { \
  63         static int warn##__LINE__=1; \
  64         if(warn##__LINE__){ \
  65                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  66                 fprintf(stderr, "File %s function %s line %d\n", \
  67                         __FILE__, __FUNCTION__, __LINE__); \
  68                 fprintf(stderr,  a, ## __VA_ARGS__);\
  69                 fprintf(stderr, "***************************************************************************\n"); \
  70                 warn##__LINE__=0;\
  71                 } \
  72         }
  73
  74 #include "r300_vertprog.h"
  75 #include "r500_fragprog.h"
  76
  77 /**
  78  * This function takes a float and packs it into a uint32_t
  79  */
  80 static INLINE uint32_t r300PackFloat32(float fl)
  81 {
  82         union {
  83                 float fl;
  84                 uint32_t u;
  85         } u;
  86
  87         u.fl = fl;
  88         return u.u;
  89 }
  90
  91 /* This is probably wrong for some values, I need to test this
  92  * some more.  Range checking would be a good idea also..
  93  *
  94  * But it works for most things.  I'll fix it later if someone
  95  * else with a better clue doesn't
  96  */
  97 static INLINE uint32_t r300PackFloat24(float f)
  98 {
  99         float mantissa;
 100         int exponent;
 101         uint32_t float24 = 0;
 102
 103         if (f == 0.0)
 104                 return 0;
 105
 106         mantissa = frexpf(f, &exponent);
 107
 108         /* Handle -ve */
 109         if (mantissa < 0) {
 110                 float24 |= (1 << 23);
 111                 mantissa = mantissa * -1.0;
 112         }
 113         /* Handle exponent, bias of 63 */
 114         exponent += 62;
 115         float24 |= (exponent << 16);
 116         /* Kill 7 LSB of mantissa */
 117         float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7;
 118
 119         return float24;
 120 }
 121
 122 /************ DMA BUFFERS **************/
 123
 124
 125 /* Texture related */
 126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 127 typedef struct _r300_texture_image r300_texture_image;
 128
 129
 130 struct _r300_texture_image {
 131         struct gl_texture_image base;
 132
 133         /**
 134          * If mt != 0, the image is stored in hardware format in the
 135          * given mipmap tree. In this case, base.Data may point into the
 136          * mapping of the buffer object that contains the mipmap tree.
 137          *
 138          * If mt == 0, the image is stored in normal memory pointed to
 139          * by base.Data.
 140          */
 141         struct _r300_mipmap_tree *mt;
 142     struct radeon_bo *bo;
 143
 144         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 145         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 146 };
 147
 148 static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image *image)
 149 {
 150         return (r300_texture_image*)image;
 151 }
 152
 153
 154 /* Texture object in locally shared texture space.
 155  */
 156 struct r300_tex_obj {
 157         struct gl_texture_object base;
 158         struct _r300_mipmap_tree *mt;
 159
 160         /**
 161          * This is true if we've verified that the mipmap tree above is complete
 162          * and so on.
 163          */
 164         GLboolean validated;
 165
 166         GLboolean image_override;       /* Image overridden by GLX_EXT_tfp */
 167         GLuint override_offset;
 168
 169         /* hardware register values */
 170         /* Note that R200 has 8 registers per texture and R300 only 7 */
 171         GLuint filter;
 172         GLuint filter_1;
 173         GLuint pitch_reg;
 174         GLuint size;            /* npot only */
 175         GLuint format;
 176         GLuint pp_border_color;
 177         /* end hardware registers */
 178
 179         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 180     struct radeon_bo *bo;
 181 };
 182
 183 static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj)
 184 {
 185         return (r300TexObj*)texObj;
 186 }
 187
 188 /* The blit width for texture uploads
 189  */
 190 #define R300_BLIT_WIDTH_BYTES 1024
 191 #define R300_MAX_TEXTURE_UNITS 8
 192
 193 struct r300_texture_state {
 194         int tc_count;           /* number of incoming texture coordinates from VAP */
 195 };
 196
 197 /**
 198  * A block of hardware state.
 199  *
 200  * When check returns non-zero, the returned number of dwords must be
 201  * copied verbatim into the command buffer in order to update a state atom
 202  * when it is dirty.
 203  */
 204 struct r300_state_atom {
 205         struct r300_state_atom *next, *prev;
 206         const char *name;       /* for debug */
 207         int cmd_size;           /* maximum size in dwords */
 208         GLuint idx;             /* index in an array (e.g. textures) */
 209         uint32_t *cmd;
 210         GLboolean dirty;
 211
 212         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 213         void (*emit) (r300ContextPtr, struct r300_state_atom * atom);
 214 };
 215
 216 #define R300_VPT_CMD_0          0
 217 #define R300_VPT_XSCALE         1
 218 #define R300_VPT_XOFFSET        2
 219 #define R300_VPT_YSCALE         3
 220 #define R300_VPT_YOFFSET        4
 221 #define R300_VPT_ZSCALE         5
 222 #define R300_VPT_ZOFFSET        6
 223 #define R300_VPT_CMDSIZE        7
 224
 225 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 226 #define R300_VIR_CNTL_0         1
 227 #define R300_VIR_CNTL_1         2
 228 #define R300_VIR_CNTL_2         3
 229 #define R300_VIR_CNTL_3         4
 230 #define R300_VIR_CNTL_4         5
 231 #define R300_VIR_CNTL_5         6
 232 #define R300_VIR_CNTL_6         7
 233 #define R300_VIR_CNTL_7         8
 234 #define R300_VIR_CMDSIZE        9
 235
 236 #define R300_VIC_CMD_0          0
 237 #define R300_VIC_CNTL_0         1
 238 #define R300_VIC_CNTL_1         2
 239 #define R300_VIC_CMDSIZE        3
 240
 241 #define R300_VOF_CMD_0          0
 242 #define R300_VOF_CNTL_0         1
 243 #define R300_VOF_CNTL_1         2
 244 #define R300_VOF_CMDSIZE        3
 245
 246 #define R300_PVS_CMD_0          0
 247 #define R300_PVS_CNTL_1         1
 248 #define R300_PVS_CNTL_2         2
 249 #define R300_PVS_CNTL_3         3
 250 #define R300_PVS_CMDSIZE        4
 251
 252 #define R300_GB_MISC_CMD_0              0
 253 #define R300_GB_MISC_MSPOS_0            1
 254 #define R300_GB_MISC_MSPOS_1            2
 255 #define R300_GB_MISC_TILE_CONFIG        3
 256 #define R300_GB_MISC_SELECT             4
 257 #define R300_GB_MISC_AA_CONFIG          5
 258 #define R300_GB_MISC_CMDSIZE            6
 259
 260 #define R300_TXE_CMD_0          0
 261 #define R300_TXE_ENABLE         1
 262 #define R300_TXE_CMDSIZE        2
 263
 264 #define R300_PS_CMD_0           0
 265 #define R300_PS_POINTSIZE       1
 266 #define R300_PS_CMDSIZE         2
 267
 268 #define R300_ZBS_CMD_0          0
 269 #define R300_ZBS_T_FACTOR       1
 270 #define R300_ZBS_T_CONSTANT     2
 271 #define R300_ZBS_W_FACTOR       3
 272 #define R300_ZBS_W_CONSTANT     4
 273 #define R300_ZBS_CMDSIZE        5
 274
 275 #define R300_CUL_CMD_0          0
 276 #define R300_CUL_CULL           1
 277 #define R300_CUL_CMDSIZE        2
 278
 279 #define R300_RC_CMD_0           0
 280 #define R300_RC_CNTL_0          1
 281 #define R300_RC_CNTL_1          2
 282 #define R300_RC_CMDSIZE         3
 283
 284 #define R300_RI_CMD_0           0
 285 #define R300_RI_INTERP_0        1
 286 #define R300_RI_INTERP_1        2
 287 #define R300_RI_INTERP_2        3
 288 #define R300_RI_INTERP_3        4
 289 #define R300_RI_INTERP_4        5
 290 #define R300_RI_INTERP_5        6
 291 #define R300_RI_INTERP_6        7
 292 #define R300_RI_INTERP_7        8
 293 #define R300_RI_CMDSIZE         9
 294
 295 #define R500_RI_CMDSIZE        17
 296
 297 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 298 #define R300_RR_INST_0          1
 299 #define R300_RR_INST_1          2
 300 #define R300_RR_INST_2          3
 301 #define R300_RR_INST_3          4
 302 #define R300_RR_INST_4          5
 303 #define R300_RR_INST_5          6
 304 #define R300_RR_INST_6          7
 305 #define R300_RR_INST_7          8
 306 #define R300_RR_CMDSIZE         9
 307
 308 #define R300_FP_CMD_0           0
 309 #define R300_FP_CNTL0           1
 310 #define R300_FP_CNTL1           2
 311 #define R300_FP_CNTL2           3
 312 #define R300_FP_CMD_1           4
 313 #define R300_FP_NODE0           5
 314 #define R300_FP_NODE1           6
 315 #define R300_FP_NODE2           7
 316 #define R300_FP_NODE3           8
 317 #define R300_FP_CMDSIZE         9
 318
 319 #define R500_FP_CMD_0           0
 320 #define R500_FP_CNTL            1
 321 #define R500_FP_PIXSIZE         2
 322 #define R500_FP_CMD_1           3
 323 #define R500_FP_CODE_ADDR       4
 324 #define R500_FP_CODE_RANGE      5
 325 #define R500_FP_CODE_OFFSET     6
 326 #define R500_FP_CMD_2           7
 327 #define R500_FP_FC_CNTL         8
 328 #define R500_FP_CMDSIZE         9
 329
 330 #define R300_FPT_CMD_0          0
 331 #define R300_FPT_INSTR_0        1
 332 #define R300_FPT_CMDSIZE        65
 333
 334 #define R300_FPI_CMD_0          0
 335 #define R300_FPI_INSTR_0        1
 336 #define R300_FPI_CMDSIZE        65
 337 /* R500 has space for 512 instructions - 6 dwords per instruction */
 338 #define R500_FPI_CMDSIZE        (512*6+1)
 339
 340 #define R300_FPP_CMD_0          0
 341 #define R300_FPP_PARAM_0        1
 342 #define R300_FPP_CMDSIZE        (32*4+1)
 343 /* R500 has spcae for 256 constants - 4 dwords per constant */
 344 #define R500_FPP_CMDSIZE        (256*4+1)
 345
 346 #define R300_FOGS_CMD_0         0
 347 #define R300_FOGS_STATE         1
 348 #define R300_FOGS_CMDSIZE       2
 349
 350 #define R300_FOGC_CMD_0         0
 351 #define R300_FOGC_R             1
 352 #define R300_FOGC_G             2
 353 #define R300_FOGC_B             3
 354 #define R300_FOGC_CMDSIZE       4
 355
 356 #define R300_FOGP_CMD_0         0
 357 #define R300_FOGP_SCALE         1
 358 #define R300_FOGP_START         2
 359 #define R300_FOGP_CMDSIZE       3
 360
 361 #define R300_AT_CMD_0           0
 362 #define R300_AT_ALPHA_TEST      1
 363 #define R300_AT_UNKNOWN         2
 364 #define R300_AT_CMDSIZE         3
 365
 366 #define R300_BLD_CMD_0          0
 367 #define R300_BLD_CBLEND         1
 368 #define R300_BLD_ABLEND         2
 369 #define R300_BLD_CMDSIZE        3
 370
 371 #define R300_CMK_CMD_0          0
 372 #define R300_CMK_COLORMASK      1
 373 #define R300_CMK_CMDSIZE        2
 374
 375 #define R300_CB_CMD_0           0
 376 #define R300_CB_OFFSET          1
 377 #define R300_CB_CMD_1           2
 378 #define R300_CB_PITCH           3
 379 #define R300_CB_CMDSIZE         4
 380
 381 #define R300_ZS_CMD_0           0
 382 #define R300_ZS_CNTL_0          1
 383 #define R300_ZS_CNTL_1          2
 384 #define R300_ZS_CNTL_2          3
 385 #define R300_ZS_CMDSIZE         4
 386
 387 #define R300_ZB_CMD_0           0
 388 #define R300_ZB_OFFSET          1
 389 #define R300_ZB_PITCH           2
 390 #define R300_ZB_CMDSIZE         3
 391
 392 #define R300_VAP_CNTL_FLUSH     0
 393 #define R300_VAP_CNTL_FLUSH_1   1
 394 #define R300_VAP_CNTL_CMD       2
 395 #define R300_VAP_CNTL_INSTR     3
 396 #define R300_VAP_CNTL_SIZE      4
 397
 398 #define R300_VPI_CMD_0          0
 399 #define R300_VPI_INSTR_0        1
 400 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 401
 402 #define R300_VPP_CMD_0          0
 403 #define R300_VPP_PARAM_0        1
 404 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 405
 406 #define R300_VPUCP_CMD_0                0
 407 #define R300_VPUCP_X            1
 408 #define R300_VPUCP_Y            2
 409 #define R300_VPUCP_Z            3
 410 #define R300_VPUCP_W            4
 411 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 412
 413 #define R300_VPS_CMD_0          0
 414 #define R300_VPS_ZERO_0         1
 415 #define R300_VPS_ZERO_1         2
 416 #define R300_VPS_POINTSIZE      3
 417 #define R300_VPS_ZERO_3         4
 418 #define R300_VPS_CMDSIZE        5
 419
 420         /* the layout is common for all fields inside tex */
 421 #define R300_TEX_CMD_0          0
 422 #define R300_TEX_VALUE_0        1
 423 /* We don't really use this, instead specify mtu+1 dynamically
 424 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 425 */
 426
 427 /**
 428  * Cache for hardware register state.
 429  */
 430 struct r300_hw_state {
 431         struct r300_state_atom atomlist;
 432
 433         GLboolean is_dirty;
 434         GLboolean all_dirty;
 435         int max_state_size;     /* in dwords */
 436
 437         struct r300_state_atom vpt;     /* viewport (1D98) */
 438         struct r300_state_atom vap_cntl;
 439         struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */
 440         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 441         struct r300_state_atom vte;     /* (20B0) */
 442         struct r300_state_atom vap_vf_max_vtx_indx;     /* Maximum Vertex Indx Clamp (2134) */
 443         struct r300_state_atom vap_cntl_status;
 444         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 445         struct r300_state_atom vic;     /* vap input control (2180) */
 446         struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 447         struct r300_state_atom vap_clip_cntl;
 448         struct r300_state_atom vap_clip;
 449         struct r300_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */
 450         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 451         struct r300_state_atom gb_enable;       /* (4008) */
 452         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 453         struct r300_state_atom ga_point_s0;     /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 454         struct r300_state_atom ga_triangle_stipple;     /* (4214) */
 455         struct r300_state_atom ps;      /* pointsize (421C) */
 456         struct r300_state_atom ga_point_minmax; /* (4230) */
 457         struct r300_state_atom lcntl;   /* line control */
 458         struct r300_state_atom ga_line_stipple; /* (4260) */
 459         struct r300_state_atom shade;
 460         struct r300_state_atom polygon_mode;
 461         struct r300_state_atom fogp;    /* fog parameters (4294) */
 462         struct r300_state_atom ga_soft_reset;   /* (429C) */
 463         struct r300_state_atom zbias_cntl;
 464         struct r300_state_atom zbs;     /* zbias (42A4) */
 465         struct r300_state_atom occlusion_cntl;
 466         struct r300_state_atom cul;     /* cull cntl (42B8) */
 467         struct r300_state_atom su_depth_scale;  /* (42C0) */
 468         struct r300_state_atom rc;      /* rs control (4300) */
 469         struct r300_state_atom ri;      /* rs interpolators (4310) */
 470         struct r300_state_atom rr;      /* rs route (4330) */
 471         struct r300_state_atom sc_hyperz;       /* (43A4) */
 472         struct r300_state_atom sc_screendoor;   /* (43E8) */
 473         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 474         struct r300_state_atom fpt;     /* texi - (4620) */
 475         struct r300_state_atom us_out_fmt;      /* (46A4) */
 476         struct r300_state_atom r500fp;  /* r500 fp instructions */
 477         struct r300_state_atom r500fp_const;    /* r500 fp constants */
 478         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 479         struct r300_state_atom fogs;    /* fog state (4BC0) */
 480         struct r300_state_atom fogc;    /* fog color (4BC8) */
 481         struct r300_state_atom at;      /* alpha test (4BD4) */
 482         struct r300_state_atom fg_depth_src;    /* (4BD8) */
 483         struct r300_state_atom fpp;     /* 0x4C00 and following */
 484         struct r300_state_atom rb3d_cctl;       /* (4E00) */
 485         struct r300_state_atom bld;     /* blending (4E04) */
 486         struct r300_state_atom cmk;     /* colormask (4E0C) */
 487         struct r300_state_atom blend_color;     /* constant blend color */
 488         struct r300_state_atom rop;     /* ropcntl */
 489         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 490         struct r300_state_atom rb3d_dither_ctl; /* (4E50) */
 491         struct r300_state_atom rb3d_aaresolve_ctl;      /* (4E88) */
 492         struct r300_state_atom rb3d_discard_src_pixel_lte_threshold;    /* (4E88) I saw it only written on RV350 hardware..  */
 493         struct r300_state_atom zs;      /* zstencil control (4F00) */
 494         struct r300_state_atom zstencil_format;
 495         struct r300_state_atom zb;      /* z buffer (4F20) */
 496         struct r300_state_atom zb_depthclearvalue;      /* (4F28) */
 497         struct r300_state_atom unk4F30; /* (4F30) */
 498         struct r300_state_atom zb_hiz_offset;   /* (4F44) */
 499         struct r300_state_atom zb_hiz_pitch;    /* (4F54) */
 500
 501         struct r300_state_atom vpi;     /* vp instructions */
 502         struct r300_state_atom vpp;     /* vp parameters */
 503         struct r300_state_atom vps;     /* vertex point size (?) */
 504         struct r300_state_atom vpucp[6];        /* vp user clip plane - 6 */
 505         /* 8 texture units */
 506         /* the state is grouped by function and not by
 507            texture unit. This makes single unit updates
 508            really awkward - we are much better off
 509            updating the whole thing at once */
 510         struct {
 511                 struct r300_state_atom filter;
 512                 struct r300_state_atom filter_1;
 513                 struct r300_state_atom size;
 514                 struct r300_state_atom format;
 515                 struct r300_state_atom pitch;
 516                 struct r300_state_atom offset;
 517                 struct r300_state_atom chroma_key;
 518                 struct r300_state_atom border_color;
 519         } tex;
 520         struct r300_state_atom txe;     /* tex enable (4104) */
 521
 522         r300TexObj *textures[R300_MAX_TEXTURE_UNITS];
 523 };
 524
 525 /**
 526  * This structure holds the command buffer while it is being constructed.
 527  *
 528  * The first batch of commands in the buffer is always the state that needs
 529  * to be re-emitted when the context is lost. This batch can be skipped
 530  * otherwise.
 531  */
 532 struct r300_cmdbuf {
 533     struct radeon_cs_manager    *csm;
 534     struct radeon_cs            *cs;
 535         int size; /** # of dwords total */
 536         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 537 };
 538
 539 /**
 540  * State cache
 541  */
 542
 543 struct r300_depthbuffer_state {
 544         GLfloat scale;
 545 };
 546
 547 struct r300_stencilbuffer_state {
 548         GLboolean hw_stencil;
 549 };
 550
 551 /* Vertex shader state */
 552
 553 /* Perhaps more if we store programs in vmem? */
 554 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 555 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 556
 557 /* Can be tested with colormat currently. */
 558 #define VSF_MAX_FRAGMENT_TEMPS (14)
 559
 560 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 561 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 562
 563 struct r300_vertex_shader_fragment {
 564         int length;
 565         union {
 566                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 567                 float f[VSF_MAX_FRAGMENT_LENGTH];
 568                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 569         } body;
 570 };
 571
 572 struct r300_vertex_shader_state {
 573         struct r300_vertex_shader_fragment program;
 574 };
 575
 576 extern int hw_tcl_on;
 577
 578 #define COLOR_IS_RGBA
 579 #define TAG(x) r300##x
 580 #include "tnl_dd/t_dd_vertex.h"
 581 #undef TAG
 582
 583 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 584 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 585
 586 /* Should but doesnt work */
 587 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 588
 589 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 590  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 591  */
 592
 593 struct r300_vertex_program_key {
 594         GLuint InputsRead;
 595         GLuint OutputsWritten;
 596         GLuint OutputsAdded;
 597 };
 598
 599 struct r300_vertex_program {
 600         struct r300_vertex_program *next;
 601         struct r300_vertex_program_key key;
 602         int translated;
 603
 604         struct r300_vertex_shader_fragment program;
 605
 606         int pos_end;
 607         int num_temporaries;    /* Number of temp vars used by program */
 608         int wpos_idx;
 609         int inputs[VERT_ATTRIB_MAX];
 610         int outputs[VERT_RESULT_MAX];
 611         int native;
 612         int ref_count;
 613         int use_ref_count;
 614 };
 615
 616 struct r300_vertex_program_cont {
 617         struct gl_vertex_program mesa_program;  /* Must be first */
 618         struct r300_vertex_shader_fragment params;
 619         struct r300_vertex_program *progs;
 620 };
 621
 622 #define PFS_MAX_ALU_INST        64
 623 #define PFS_MAX_TEX_INST        64
 624 #define PFS_MAX_TEX_INDIRECT 4
 625 #define PFS_NUM_TEMP_REGS       32
 626 #define PFS_NUM_CONST_REGS      16
 627
 628 struct r300_pfs_compile_state;
 629
 630
 631 /**
 632  * Stores state that influences the compilation of a fragment program.
 633  */
 634 struct r300_fragment_program_external_state {
 635         struct {
 636                 /**
 637                  * If the sampler is used as a shadow sampler,
 638                  * this field is:
 639                  *  0 - GL_LUMINANCE
 640                  *  1 - GL_INTENSITY
 641                  *  2 - GL_ALPHA
 642                  * depending on the depth texture mode.
 643                  */
 644                 GLuint depth_texture_mode : 2;
 645
 646                 /**
 647                  * If the sampler is used as a shadow sampler,
 648                  * this field is (texture_compare_func - GL_NEVER).
 649                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 650                  *
 651                  * Otherwise, this field is 0.
 652                  */
 653                 GLuint texture_compare_func : 3;
 654         } unit[16];
 655 };
 656
 657
 658 struct r300_fragment_program_node {
 659         int tex_offset; /**< first tex instruction */
 660         int tex_end; /**< last tex instruction, relative to tex_offset */
 661         int alu_offset; /**< first ALU instruction */
 662         int alu_end; /**< last ALU instruction, relative to alu_offset */
 663         int flags;
 664 };
 665
 666 /**
 667  * Stores an R300 fragment program in its compiled-to-hardware form.
 668  */
 669 struct r300_fragment_program_code {
 670         struct {
 671                 int length; /**< total # of texture instructions used */
 672                 GLuint inst[PFS_MAX_TEX_INST];
 673         } tex;
 674
 675         struct {
 676                 int length; /**< total # of ALU instructions used */
 677                 struct {
 678                         GLuint inst0;
 679                         GLuint inst1;
 680                         GLuint inst2;
 681                         GLuint inst3;
 682                 } inst[PFS_MAX_ALU_INST];
 683         } alu;
 684
 685         struct r300_fragment_program_node node[4];
 686         int cur_node;
 687         int first_node_has_tex;
 688
 689         /**
 690          * Remember which program register a given hardware constant
 691          * belongs to.
 692          */
 693         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 694         int const_nr;
 695
 696         int max_temp_idx;
 697 };
 698
 699 /**
 700  * Store everything about a fragment program that is needed
 701  * to render with that program.
 702  */
 703 struct r300_fragment_program {
 704         struct gl_fragment_program mesa_program;
 705
 706         GLboolean translated;
 707         GLboolean error;
 708
 709         struct r300_fragment_program_external_state state;
 710         struct r300_fragment_program_code code;
 711
 712         GLboolean WritesDepth;
 713         GLuint optimization;
 714 };
 715
 716 struct r500_pfs_compile_state;
 717
 718 struct r500_fragment_program_external_state {
 719         struct {
 720                 /**
 721                  * If the sampler is used as a shadow sampler,
 722                  * this field is:
 723                  *  0 - GL_LUMINANCE
 724                  *  1 - GL_INTENSITY
 725                  *  2 - GL_ALPHA
 726                  * depending on the depth texture mode.
 727                  */
 728                 GLuint depth_texture_mode : 2;
 729
 730                 /**
 731                  * If the sampler is used as a shadow sampler,
 732                  * this field is (texture_compare_func - GL_NEVER).
 733                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 734                  *
 735                  * Otherwise, this field is 0.
 736                  */
 737                 GLuint texture_compare_func : 3;
 738         } unit[16];
 739 };
 740
 741 struct r500_fragment_program_code {
 742         struct {
 743                 GLuint inst0;
 744                 GLuint inst1;
 745                 GLuint inst2;
 746                 GLuint inst3;
 747                 GLuint inst4;
 748                 GLuint inst5;
 749         } inst[512];
 750
 751         int inst_offset;
 752         int inst_end;
 753
 754         /**
 755          * Remember which program register a given hardware constant
 756          * belongs to.
 757          */
 758         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 759         int const_nr;
 760
 761         int max_temp_idx;
 762 };
 763
 764 struct r500_fragment_program {
 765         struct gl_fragment_program mesa_program;
 766
 767         GLcontext *ctx;
 768         GLboolean translated;
 769         GLboolean error;
 770
 771         struct r500_fragment_program_external_state state;
 772         struct r500_fragment_program_code code;
 773
 774         GLboolean writes_depth;
 775
 776         GLuint optimization;
 777 };
 778
 779 #define R300_MAX_AOS_ARRAYS             16
 780
 781 #define REG_COORDS      0
 782 #define REG_COLOR0      1
 783 #define REG_TEX0        2
 784
 785 struct r300_aos {
 786         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 787         int offset; /** Offset into buffer object, in bytes */
 788         int components; /** Number of components per vertex */
 789         int stride; /** Stride in dwords (may be 0 for repeating) */
 790         int count; /** Number of vertices */
 791 };
 792
 793 struct r300_state {
 794         struct r300_depthbuffer_state depth;
 795         struct r300_texture_state texture;
 796         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 797         struct r300_vertex_shader_state vertex_shader;
 798         struct r300_aos aos[R300_MAX_AOS_ARRAYS];
 799         int aos_count;
 800
 801         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 802         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 803
 804         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 805                                                            They are the same as tnl->render_inputs for fixed pipeline */
 806
 807         struct r300_stencilbuffer_state stencil;
 808
 809 };
 810
 811 #define R300_FALLBACK_NONE 0
 812 #define R300_FALLBACK_TCL 1
 813 #define R300_FALLBACK_RAST 2
 814
 815 /* r300_swtcl.c
 816  */
 817 struct r300_swtcl_info {
 818    GLuint RenderIndex;
 819
 820    /**
 821     * Size of a hardware vertex.  This is calculated when \c ::vertex_attrs is
 822     * installed in the Mesa state vector.
 823     */
 824    GLuint vertex_size;
 825
 826    /**
 827     * Attributes instructing the Mesa TCL pipeline where / how to put vertex
 828     * data in the hardware buffer.
 829     */
 830    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 831
 832    /**
 833     * Number of elements of \c ::vertex_attrs that are actually used.
 834     */
 835    GLuint vertex_attr_count;
 836
 837    /**
 838     * Cached pointer to the buffer where Mesa will store vertex data.
 839     */
 840    GLubyte *verts;
 841
 842    /* Fallback rasterization functions
 843     */
 844   //   r200_point_func draw_point;
 845   //   r200_line_func draw_line;
 846   //   r200_tri_func draw_tri;
 847
 848    GLuint hw_primitive;
 849    GLenum render_primitive;
 850    GLuint numverts;
 851
 852    /**
 853     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 854     */
 855    GLuint coloroffset;
 856
 857    /**
 858     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 859     */
 860    GLuint specoffset;
 861
 862    struct radeon_bo *bo;
 863    void (*flush) (r300ContextPtr);
 864 };
 865
 866
 867 /**
 868  * \brief R300 context structure.
 869  */
 870 struct r300_context {
 871         struct radeon_context radeon;   /* parent class, must be first */
 872
 873         struct r300_hw_state hw;
 874         struct r300_cmdbuf cmdbuf;
 875         struct r300_state state;
 876         struct gl_vertex_program *curr_vp;
 877         struct r300_vertex_program *selected_vp;
 878
 879         /* Vertex buffers
 880          */
 881         GLuint NewGLState;
 882
 883         int texture_depth;
 884         float initialMaxAnisotropy;
 885
 886         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 887         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 888
 889         GLboolean disable_lowimpact_fallback;
 890
 891         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 892         struct r300_swtcl_info swtcl;
 893 };
 894
 895 struct r300_buffer_object {
 896         struct gl_buffer_object mesa_obj;
 897         int id;
 898 };
 899
 900 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 901
 902 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 903 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 904                                    __DRIcontextPrivate * driContextPriv,
 905                                    void *sharedContextPrivate);
 906
 907 extern void r300SelectVertexShader(r300ContextPtr r300);
 908 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 909 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 910                                       struct r300_vertex_program_cont *vp,
 911                                       float *dst);
 912
 913 #define RADEON_D_CAPTURE 0
 914 #define RADEON_D_PLAYBACK 1
 915 #define RADEON_D_PLAYBACK_RAW 2
 916 #define RADEON_D_T 3
 917
 918 #endif                          /* __R300_CONTEXT_H__ */