src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57 /* Checkpoint.. for convenience */
  58 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 typedef GLuint uint32_t;
  76 typedef GLubyte uint8_t;
  77
  78   /* We should probably change types within vertex_shader
  79       and pixel_shader structure later on */
  80 #define CARD32 GLuint
  81 #include "vertex_shader.h"
  82 #include "pixel_shader.h"
  83 #undef CARD32
  84
  85 static __inline__ uint32_t r300PackFloat32(float fl)
  86 {
  87         union { float fl; uint32_t u; } u;
  88
  89         u.fl = fl;
  90         return u.u;
  91 }
  92
  93
  94 /************ DMA BUFFERS **************/
  95
  96 /* Need refcounting on dma buffers:
  97  */
  98 struct r300_dma_buffer {
  99         int refcount;           /* the number of retained regions in buf */
 100         drmBufPtr buf;
 101 };
 102
 103 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 104                         (rvb)->address - rmesa->dma.buf0_address +      \
 105                         (rvb)->start)
 106
 107 /* A retained region, eg vertices for indexed vertices.
 108  */
 109 struct r300_dma_region {
 110         struct r300_dma_buffer *buf;
 111         char *address;          /* == buf->address */
 112         int start, end, ptr;    /* offsets from start of buf */
 113         int aos_start;
 114         int aos_stride;
 115         int aos_size;
 116 };
 117
 118 struct r300_dma {
 119         /* Active dma region.  Allocations for vertices and retained
 120          * regions come from here.  Also used for emitting random vertices,
 121          * these may be flushed by calling flush_current();
 122          */
 123         struct r300_dma_region current;
 124
 125         void (*flush) (r300ContextPtr);
 126
 127         char *buf0_address;     /* start of buf[0], for index calcs */
 128         GLuint nr_released_bufs;        /* flush after so many buffers released */
 129 };
 130
 131        /* Texture related */
 132
 133 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 134
 135 /* Texture object in locally shared texture space.
 136  */
 137 struct r300_tex_obj {
 138         driTextureObject base;
 139
 140         GLuint bufAddr;         /* Offset to start of locally
 141                                    shared texture block */
 142
 143         GLuint dirty_state;     /* Flags (1 per texunit) for
 144                                    whether or not this texobj
 145                                    has dirty hardware state
 146                                    (pp_*) that needs to be
 147                                    brought into the
 148                                    texunit. */
 149
 150         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 151         /* Six, for the cube faces */
 152
 153
 154         /* hardware register values */
 155         /* Note that R200 has 8 registers per texture and R300 only 7 */
 156         GLuint filter;
 157         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 158         GLuint size;    /* npot only */
 159         GLuint format;
 160         GLuint offset;  /* Image location in texmem.
 161                                    All cube faces follow. */
 162         GLuint unknown4;
 163         GLuint unknown5;
 164         /* end hardware registers */
 165
 166         /* registers computed by r200 code - keep them here to
 167            compare against what is actually written.
 168
 169            to be removed later.. */
 170         GLuint pp_border_color;
 171         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 172         GLuint format_x;
 173
 174
 175         GLboolean border_fallback;
 176 };
 177
 178 struct r300_texture_env_state {
 179         r300TexObjPtr texobj;
 180         GLenum format;
 181         GLenum envMode;
 182 };
 183
 184 #define R300_MAX_TEXTURE_UNITS 8
 185
 186 struct r300_texture_state {
 187         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 188         int tc_count; /* number of incoming texture coordinates from VAP */
 189 };
 190
 191 /**
 192  * A block of hardware state.
 193  *
 194  * When check returns non-zero, the returned number of dwords must be
 195  * copied verbatim into the command buffer in order to update a state atom
 196  * when it is dirty.
 197  */
 198 struct r300_state_atom {
 199         struct r300_state_atom *next, *prev;
 200         const char* name;       /* for debug */
 201         int cmd_size;           /* maximum size in dwords */
 202         GLuint idx;             /* index in an array (e.g. textures) */
 203         uint32_t* cmd;
 204         GLboolean dirty;
 205
 206         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 207 };
 208
 209
 210 #define R300_VPT_CMD_0          0
 211 #define R300_VPT_XSCALE         1
 212 #define R300_VPT_XOFFSET        2
 213 #define R300_VPT_YSCALE         3
 214 #define R300_VPT_YOFFSET        4
 215 #define R300_VPT_ZSCALE         5
 216 #define R300_VPT_ZOFFSET        6
 217 #define R300_VPT_CMDSIZE        7
 218
 219 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 220 #define R300_VIR_CNTL_0         1
 221 #define R300_VIR_CNTL_1         2
 222 #define R300_VIR_CNTL_2         3
 223 #define R300_VIR_CNTL_3         4
 224 #define R300_VIR_CNTL_4         5
 225 #define R300_VIR_CNTL_5         6
 226 #define R300_VIR_CNTL_6         7
 227 #define R300_VIR_CNTL_7         8
 228 #define R300_VIR_CMDSIZE        9
 229
 230 #define R300_VIC_CMD_0          0
 231 #define R300_VIC_CNTL_0         1
 232 #define R300_VIC_CNTL_1         2
 233 #define R300_VIC_CMDSIZE        3
 234
 235 #define R300_VOF_CMD_0          0
 236 #define R300_VOF_CNTL_0         1
 237 #define R300_VOF_CNTL_1         2
 238 #define R300_VOF_CMDSIZE        3
 239
 240
 241 #define R300_PVS_CMD_0          0
 242 #define R300_PVS_CNTL_1         1
 243 #define R300_PVS_CNTL_2         2
 244 #define R300_PVS_CNTL_3         3
 245 #define R300_PVS_CMDSIZE        4
 246
 247 #define R300_GB_MISC_CMD_0              0
 248 #define R300_GB_MISC_MSPOS_0            1
 249 #define R300_GB_MISC_MSPOS_1            2
 250 #define R300_GB_MISC_TILE_CONFIG        3
 251 #define R300_GB_MISC_SELECT             4
 252 #define R300_GB_MISC_AA_CONFIG          5
 253 #define R300_GB_MISC_CMDSIZE            6
 254
 255 #define R300_TXE_CMD_0          0
 256 #define R300_TXE_ENABLE         1
 257 #define R300_TXE_CMDSIZE        2
 258
 259 #define R300_PS_CMD_0           0
 260 #define R300_PS_POINTSIZE       1
 261 #define R300_PS_CMDSIZE         2
 262
 263 #define R300_ZBS_CMD_0          0
 264 #define R300_ZBS_T_FACTOR       1
 265 #define R300_ZBS_T_CONSTANT     2
 266 #define R300_ZBS_W_FACTOR       3
 267 #define R300_ZBS_W_CONSTANT     4
 268 #define R300_ZBS_CMDSIZE        5
 269
 270 #define R300_CUL_CMD_0          0
 271 #define R300_CUL_CULL           1
 272 #define R300_CUL_CMDSIZE        2
 273
 274 #define R300_RC_CMD_0           0
 275 #define R300_RC_CNTL_0          1
 276 #define R300_RC_CNTL_1          2
 277 #define R300_RC_CMDSIZE         3
 278
 279 #define R300_RI_CMD_0           0
 280 #define R300_RI_INTERP_0        1
 281 #define R300_RI_INTERP_1        2
 282 #define R300_RI_INTERP_2        3
 283 #define R300_RI_INTERP_3        4
 284 #define R300_RI_INTERP_4        5
 285 #define R300_RI_INTERP_5        6
 286 #define R300_RI_INTERP_6        7
 287 #define R300_RI_INTERP_7        8
 288 #define R300_RI_CMDSIZE         9
 289
 290 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 291 #define R300_RR_ROUTE_0         1
 292 #define R300_RR_ROUTE_1         2
 293 #define R300_RR_ROUTE_2         3
 294 #define R300_RR_ROUTE_3         4
 295 #define R300_RR_ROUTE_4         5
 296 #define R300_RR_ROUTE_5         6
 297 #define R300_RR_ROUTE_6         7
 298 #define R300_RR_ROUTE_7         8
 299 #define R300_RR_CMDSIZE         9
 300
 301 #define R300_FP_CMD_0           0
 302 #define R300_FP_CNTL0           1
 303 #define R300_FP_CNTL1           2
 304 #define R300_FP_CNTL2           3
 305 #define R300_FP_CMD_1           4
 306 #define R300_FP_NODE0           5
 307 #define R300_FP_NODE1           6
 308 #define R300_FP_NODE2           7
 309 #define R300_FP_NODE3           8
 310 #define R300_FP_CMDSIZE         9
 311
 312 #define R300_FPT_CMD_0          0
 313 #define R300_FPT_INSTR_0        1
 314 #define R300_FPT_CMDSIZE        65
 315
 316 #define R300_FPI_CMD_0          0
 317 #define R300_FPI_INSTR_0        1
 318 #define R300_FPI_CMDSIZE        65
 319
 320 #define R300_FPP_CMD_0          0
 321 #define R300_FPP_PARAM_0        1
 322 #define R300_FPP_CMDSIZE        (32*4+1)
 323
 324 #define R300_AT_CMD_0           0
 325 #define R300_AT_ALPHA_TEST      1
 326 #define R300_AT_UNKNOWN         2
 327 #define R300_AT_CMDSIZE         3
 328
 329 #define R300_BLD_CMD_0          0
 330 #define R300_BLD_CBLEND         1
 331 #define R300_BLD_ABLEND         2
 332 #define R300_BLD_CMDSIZE        3
 333
 334 #define R300_CMK_CMD_0          0
 335 #define R300_CMK_COLORMASK      1
 336 #define R300_CMK_CMDSIZE        2
 337
 338 #define R300_CB_CMD_0           0
 339 #define R300_CB_OFFSET          1
 340 #define R300_CB_CMD_1           2
 341 #define R300_CB_PITCH           3
 342 #define R300_CB_CMDSIZE         4
 343
 344 #define R300_ZS_CMD_0           0
 345 #define R300_ZS_CNTL_0          1
 346 #define R300_ZS_CNTL_1          2
 347 #define R300_ZS_CNTL_2          3
 348 #define R300_ZS_CMDSIZE         4
 349
 350 #define R300_ZB_CMD_0           0
 351 #define R300_ZB_OFFSET          1
 352 #define R300_ZB_PITCH           2
 353 #define R300_ZB_CMDSIZE         3
 354
 355 #define R300_VPI_CMD_0          0
 356 #define R300_VPI_INSTR_0        1
 357 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 358
 359 #define R300_VPP_CMD_0          0
 360 #define R300_VPP_PARAM_0        1
 361 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 362
 363 #define R300_VPS_CMD_0          0
 364 #define R300_VPS_ZERO_0         1
 365 #define R300_VPS_ZERO_1         2
 366 #define R300_VPS_POINTSIZE      3
 367 #define R300_VPS_ZERO_3         4
 368 #define R300_VPS_CMDSIZE        5
 369
 370         /* the layout is common for all fields inside tex */
 371 #define R300_TEX_CMD_0          0
 372 #define R300_TEX_VALUE_0        1
 373 /* We don't really use this, instead specify mtu+1 dynamically
 374 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 375 */
 376
 377 /**
 378  * Cache for hardware register state.
 379  */
 380 struct r300_hw_state {
 381         struct r300_state_atom atomlist;
 382
 383         GLboolean       is_dirty;
 384         GLboolean       all_dirty;
 385         int             max_state_size; /* in dwords */
 386
 387         struct r300_state_atom vpt;     /* viewport (1D98) */
 388         struct r300_state_atom unk2080; /* (2080) */
 389         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 390         struct r300_state_atom vte;     /* (20B0) */
 391         struct r300_state_atom unk2134; /* (2134) */
 392         struct r300_state_atom unk2140; /* (2140) */
 393         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 394         struct r300_state_atom vic;     /* vap input control (2180) */
 395         struct r300_state_atom unk21DC; /* (21DC) */
 396         struct r300_state_atom unk221C; /* (221C) */
 397         struct r300_state_atom unk2220; /* (2220) */
 398         struct r300_state_atom unk2288; /* (2288) */
 399         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 400         struct r300_state_atom gb_enable; /* (4008) */
 401         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 402         struct r300_state_atom unk4200; /* (4200) */
 403         struct r300_state_atom unk4214; /* (4214) */
 404         struct r300_state_atom ps;      /* pointsize (421C) */
 405         struct r300_state_atom unk4230; /* (4230) */
 406         struct r300_state_atom lcntl;   /* line control */
 407 #ifdef EXP_C
 408         struct r300_state_atom lsf;     /* line stipple factor */
 409 #endif
 410         struct r300_state_atom dummy[4];
 411         struct r300_state_atom unk4260; /* (4260) */
 412         struct r300_state_atom unk4274; /* (4274) */
 413         struct r300_state_atom unk4288; /* (4288) */
 414         struct r300_state_atom unk42A0; /* (42A0) */
 415         struct r300_state_atom zbs;     /* zbias (42A4) */
 416         struct r300_state_atom unk42B4; /* (42B4) */
 417         struct r300_state_atom cul;     /* cull cntl (42B8) */
 418         struct r300_state_atom unk42C0; /* (42C0) */
 419         struct r300_state_atom rc;      /* rs control (4300) */
 420         struct r300_state_atom ri;      /* rs interpolators (4310) */
 421         struct r300_state_atom rr;      /* rs route (4330) */
 422         struct r300_state_atom unk43A4; /* (43A4) */
 423         struct r300_state_atom unk43E8; /* (43E8) */
 424         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 425         struct r300_state_atom fpt;     /* texi - (4620) */
 426         struct r300_state_atom unk46A4; /* (46A4) */
 427         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 428         struct r300_state_atom unk4BC0; /* (4BC0) */
 429         struct r300_state_atom unk4BC8; /* (4BC8) */
 430         struct r300_state_atom at;      /* alpha test (4BD4) */
 431         struct r300_state_atom unk4BD8; /* (4BD8) */
 432         struct r300_state_atom fpp;     /* 0x4C00 and following */
 433         struct r300_state_atom unk4E00; /* (4E00) */
 434         struct r300_state_atom bld;     /* blending (4E04) */
 435         struct r300_state_atom cmk;     /* colormask (4E0C) */
 436         struct r300_state_atom unk4E10; /* (4E10) */
 437         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 438         struct r300_state_atom unk4E50; /* (4E50) */
 439         struct r300_state_atom unk4E88; /* (4E88) */
 440         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 441         struct r300_state_atom zs;      /* zstencil control (4F00) */
 442         struct r300_state_atom unk4F10; /* (4F10) */
 443         struct r300_state_atom zb;      /* z buffer (4F20) */
 444         struct r300_state_atom unk4F28; /* (4F28) */
 445         struct r300_state_atom unk4F30; /* (4F30) */
 446         struct r300_state_atom unk4F44; /* (4F44) */
 447         struct r300_state_atom unk4F54; /* (4F54) */
 448
 449         struct r300_state_atom vpi;     /* vp instructions */
 450         struct r300_state_atom vpp;     /* vp parameters */
 451         struct r300_state_atom vps;     /* vertex point size (?) */
 452
 453                 /* 8 texture units */
 454                 /* the state is grouped by function and not by
 455                    texture unit. This makes single unit updates
 456                    really awkward - we are much better off
 457                    updating the whole thing at once */
 458         struct {
 459                 struct r300_state_atom filter;
 460                 struct r300_state_atom unknown1;
 461                 struct r300_state_atom size;
 462                 struct r300_state_atom format;
 463                 struct r300_state_atom offset;
 464                 struct r300_state_atom unknown4;
 465                 struct r300_state_atom border_color;
 466                 } tex;
 467         struct r300_state_atom txe;     /* tex enable (4104) */
 468 };
 469
 470
 471 /**
 472  * This structure holds the command buffer while it is being constructed.
 473  *
 474  * The first batch of commands in the buffer is always the state that needs
 475  * to be re-emitted when the context is lost. This batch can be skipped
 476  * otherwise.
 477  */
 478 struct r300_cmdbuf {
 479         int             size;           /* DWORDs allocated for buffer */
 480         uint32_t*       cmd_buf;
 481         int             count_used;     /* DWORDs filled so far */
 482         int             count_reemit;   /* size of re-emission batch */
 483 };
 484
 485
 486 /**
 487  * State cache
 488  */
 489
 490 struct r300_depthbuffer_state {
 491         GLfloat scale;
 492 };
 493
 494 struct r300_vap_reg_state {
 495            /* input register assigments */
 496            int i_coords;
 497            int i_normal;
 498            int i_color[2];
 499            int i_fog;
 500            int i_tex[R300_MAX_TEXTURE_UNITS];
 501            int i_index;
 502            int i_pointsize;
 503         };
 504
 505 /* Vertex shader state */
 506
 507 /* 64 appears to be the maximum */
 508 #define VSF_MAX_FRAGMENT_LENGTH 64
 509
 510
 511 struct r300_vertex_shader_fragment {
 512         int length;
 513         union {
 514                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 515                 float f[VSF_MAX_FRAGMENT_LENGTH];
 516                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 517                 } body;
 518         };
 519
 520 #define VSF_DEST_PROGRAM        0x0
 521 #define VSF_DEST_MATRIX0        0x200
 522 #define VSF_DEST_MATRIX1        0x204
 523 #define VSF_DEST_MATRIX2        0x208
 524 #define VSF_DEST_VECTOR0        0x20c
 525 #define VSF_DEST_VECTOR1        0x20d
 526 #define VSF_DEST_UNKNOWN1       0x400
 527 #define VSF_DEST_UNKNOWN2       0x406
 528
 529 struct r300_vertex_shader_state {
 530         struct r300_vertex_shader_fragment program;
 531
 532         /* a bit of a waste - each uses only a subset of allocated space..
 533             but easier to program */
 534         struct r300_vertex_shader_fragment matrix[3];
 535         struct r300_vertex_shader_fragment vector[2];
 536
 537         struct r300_vertex_shader_fragment unknown1;
 538         struct r300_vertex_shader_fragment unknown2;
 539
 540         int program_start;
 541         int unknown_ptr1;  /* pointer within program space */
 542         int program_end;
 543
 544         int param_offset;
 545         int param_count;
 546
 547         int unknown_ptr2;  /* pointer within program space */
 548         int unknown_ptr3;  /* pointer within program space */
 549         };
 550
 551 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 552  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 553  */
 554 struct r300_vertex_program {
 555         struct vertex_program mesa_program; /* Must be first */
 556         int translated;
 557
 558         struct r300_vertex_shader_fragment program;
 559         struct r300_vertex_shader_fragment params;
 560
 561         int t2rs;
 562         unsigned long num_temporaries; /* Number of temp vars used by program */
 563         int inputs[VERT_ATTRIB_MAX];
 564 };
 565
 566 /* 64 appears to be the maximum */
 567 #define PSF_MAX_PROGRAM_LENGTH 64
 568
 569 struct r300_pixel_shader_program {
 570         struct {
 571                 int length;
 572                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 573                 } tex;
 574
 575         /* ALU intructions (logic and integer) */
 576         struct {
 577                 int length;
 578                 struct {
 579                         GLuint inst0;
 580                         GLuint inst1;
 581                         GLuint inst2;
 582                         GLuint inst3;
 583                         } inst[PSF_MAX_PROGRAM_LENGTH];
 584                 } alu;
 585
 586         /* node information */
 587         /* nodes are used to synchronize ALU and TEX streams */
 588         /* There could be up to 4 nodes each consisting of
 589            a number of TEX instructions followed by some ALU
 590            instructions */
 591         /* the last node of a program should always be node3 */
 592         struct {
 593                 int tex_offset;
 594                 int tex_end;
 595                 int alu_offset;
 596                 int alu_end;
 597                 } node[4];
 598
 599         int active_nodes;       /* must be between 1 and 4, inclusive */
 600         int first_node_has_tex;  /* other nodes always have it */
 601
 602         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 603
 604         /* entire program */
 605         int tex_offset;
 606         int tex_end;
 607         int alu_offset;
 608         int alu_end;
 609
 610         };
 611
 612 #define MAX_PIXEL_SHADER_PARAMS 32
 613 struct r300_pixel_shader_state {
 614         struct r300_pixel_shader_program program;
 615
 616         /* parameters */
 617         int param_length;  /* to limit the number of unnecessary writes */
 618         struct {
 619                 float x;
 620                 float y;
 621                 float z;
 622                 float w;
 623                 } param[MAX_PIXEL_SHADER_PARAMS];
 624         };
 625
 626 /* 8 is somewhat bogus... it is probably something like 24 */
 627 #define R300_MAX_AOS_ARRAYS             8
 628
 629 #define AOS_FORMAT_FLOAT        1
 630 #define AOS_FORMAT_UBYTE        2
 631 #define AOS_FORMAT_FLOAT_COLOR  3
 632
 633 #define REG_COORDS      0
 634 #define REG_COLOR0      1
 635 #define REG_TEX0        2
 636
 637 struct r300_aos_rec {
 638         GLuint offset;
 639         int element_size; /* in dwords */
 640         int stride;       /* distance between elements, in dwords */
 641
 642         int format;
 643
 644         int ncomponents; /* number of components - between 1 and 4, inclusive */
 645
 646         int reg; /* which register they are assigned to. */
 647
 648         };
 649
 650 struct r300_state {
 651         struct r300_depthbuffer_state depth;
 652         struct r300_texture_state texture;
 653         struct r300_vap_reg_state vap_reg;
 654         struct r300_vertex_shader_state vertex_shader;
 655         struct r300_pixel_shader_state pixel_shader;
 656         struct r300_aos_rec aos[R300_MAX_AOS_ARRAYS];
 657         int aos_count;
 658         GLuint render_inputs; /* actual render inputs that R300 was configured for.
 659                                  They are the same as tnl->render_inputs for fixed pipeline */
 660
 661         int hw_stencil;
 662 };
 663
 664
 665 /**
 666  * R300 context structure.
 667  */
 668 struct r300_context {
 669         struct radeon_context radeon; /* parent class, must be first */
 670
 671         struct r300_hw_state hw;
 672         struct r300_cmdbuf cmdbuf;
 673         struct r300_state state;
 674
 675         /* Vertex buffers
 676          */
 677         struct r300_dma dma;
 678         GLboolean save_on_next_unlock;
 679
 680         /* Texture object bookkeeping
 681          */
 682         unsigned nr_heaps;
 683         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 684         driTextureObject swapped;
 685         int texture_depth;
 686         float initialMaxAnisotropy;
 687
 688         /* Clientdata textures;
 689          */
 690         GLuint prefer_gart_client_texturing;
 691
 692         /* TCL stuff
 693          */
 694         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 695         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 696         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 697         GLuint TexMatEnabled;
 698         GLuint TexMatCompSel;
 699         GLuint TexGenEnabled;
 700         GLuint TexGenInputs;
 701         GLuint TexGenCompSel;
 702         GLmatrix tmpmat;
 703
 704         struct r300_vertex_program *current_vp;
 705 };
 706
 707 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 708
 709 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 710 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 711                                    __DRIcontextPrivate * driContextPriv,
 712                                    void *sharedContextPrivate);
 713
 714 extern void r300InitVertexProgFuncs(struct dd_function_table *functions);
 715 extern void r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp);
 716
 717 #endif                          /* __R300_CONTEXT_H__ */