src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_bo.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 struct r300_context;
  52 typedef struct r300_context r300ContextRec;
  53 typedef struct r300_context *r300ContextPtr;
  54
  55 #include "radeon_lock.h"
  56 #include "main/mm.h"
  57
  58 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  59    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  60    with other compilers ... GLUE!
  61 */
  62 #define WARN_ONCE(a, ...)       { \
  63         static int warn##__LINE__=1; \
  64         if(warn##__LINE__){ \
  65                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  66                 fprintf(stderr, "File %s function %s line %d\n", \
  67                         __FILE__, __FUNCTION__, __LINE__); \
  68                 fprintf(stderr,  a, ## __VA_ARGS__);\
  69                 fprintf(stderr, "***************************************************************************\n"); \
  70                 warn##__LINE__=0;\
  71                 } \
  72         }
  73
  74 #include "r300_vertprog.h"
  75 #include "r500_fragprog.h"
  76
  77 /**
  78  * This function takes a float and packs it into a uint32_t
  79  */
  80 static INLINE uint32_t r300PackFloat32(float fl)
  81 {
  82         union {
  83                 float fl;
  84                 uint32_t u;
  85         } u;
  86
  87         u.fl = fl;
  88         return u.u;
  89 }
  90
  91 /* This is probably wrong for some values, I need to test this
  92  * some more.  Range checking would be a good idea also..
  93  *
  94  * But it works for most things.  I'll fix it later if someone
  95  * else with a better clue doesn't
  96  */
  97 static INLINE uint32_t r300PackFloat24(float f)
  98 {
  99         float mantissa;
 100         int exponent;
 101         uint32_t float24 = 0;
 102
 103         if (f == 0.0)
 104                 return 0;
 105
 106         mantissa = frexpf(f, &exponent);
 107
 108         /* Handle -ve */
 109         if (mantissa < 0) {
 110                 float24 |= (1 << 23);
 111                 mantissa = mantissa * -1.0;
 112         }
 113         /* Handle exponent, bias of 63 */
 114         exponent += 62;
 115         float24 |= (exponent << 16);
 116         /* Kill 7 LSB of mantissa */
 117         float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7;
 118
 119         return float24;
 120 }
 121
 122 /************ DMA BUFFERS **************/
 123
 124
 125 /* Texture related */
 126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 127 typedef struct _r300_texture_image r300_texture_image;
 128
 129
 130 struct _r300_texture_image {
 131         struct gl_texture_image base;
 132
 133         /**
 134          * If mt != 0, the image is stored in hardware format in the
 135          * given mipmap tree. In this case, base.Data may point into the
 136          * mapping of the buffer object that contains the mipmap tree.
 137          *
 138          * If mt == 0, the image is stored in normal memory pointed to
 139          * by base.Data.
 140          */
 141         struct _r300_mipmap_tree *mt;
 142
 143         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 144         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 145 };
 146
 147 static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image *image)
 148 {
 149         return (r300_texture_image*)image;
 150 }
 151
 152
 153 /* Texture object in locally shared texture space.
 154  */
 155 struct r300_tex_obj {
 156         struct gl_texture_object base;
 157         struct _r300_mipmap_tree *mt;
 158
 159         /**
 160          * This is true if we've verified that the mipmap tree above is complete
 161          * and so on.
 162          */
 163         GLboolean validated;
 164
 165         GLboolean image_override;       /* Image overridden by GLX_EXT_tfp */
 166         GLuint override_offset;
 167
 168         /* hardware register values */
 169         /* Note that R200 has 8 registers per texture and R300 only 7 */
 170         GLuint filter;
 171         GLuint filter_1;
 172         GLuint pitch_reg;
 173         GLuint size;            /* npot only */
 174         GLuint format;
 175         GLuint pp_border_color;
 176         /* end hardware registers */
 177
 178         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 179     struct radeon_bo *bo;
 180 };
 181
 182 static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj)
 183 {
 184         return (r300TexObj*)texObj;
 185 }
 186
 187 /* The blit width for texture uploads
 188  */
 189 #define R300_BLIT_WIDTH_BYTES 1024
 190 #define R300_MAX_TEXTURE_UNITS 8
 191
 192 struct r300_texture_state {
 193         int tc_count;           /* number of incoming texture coordinates from VAP */
 194 };
 195
 196 /**
 197  * A block of hardware state.
 198  *
 199  * When check returns non-zero, the returned number of dwords must be
 200  * copied verbatim into the command buffer in order to update a state atom
 201  * when it is dirty.
 202  */
 203 struct r300_state_atom {
 204         struct r300_state_atom *next, *prev;
 205         const char *name;       /* for debug */
 206         int cmd_size;           /* maximum size in dwords */
 207         GLuint idx;             /* index in an array (e.g. textures) */
 208         uint32_t *cmd;
 209         GLboolean dirty;
 210
 211         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 212         void (*emit) (r300ContextPtr, struct r300_state_atom * atom);
 213 };
 214
 215 #define R300_VPT_CMD_0          0
 216 #define R300_VPT_XSCALE         1
 217 #define R300_VPT_XOFFSET        2
 218 #define R300_VPT_YSCALE         3
 219 #define R300_VPT_YOFFSET        4
 220 #define R300_VPT_ZSCALE         5
 221 #define R300_VPT_ZOFFSET        6
 222 #define R300_VPT_CMDSIZE        7
 223
 224 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 225 #define R300_VIR_CNTL_0         1
 226 #define R300_VIR_CNTL_1         2
 227 #define R300_VIR_CNTL_2         3
 228 #define R300_VIR_CNTL_3         4
 229 #define R300_VIR_CNTL_4         5
 230 #define R300_VIR_CNTL_5         6
 231 #define R300_VIR_CNTL_6         7
 232 #define R300_VIR_CNTL_7         8
 233 #define R300_VIR_CMDSIZE        9
 234
 235 #define R300_VIC_CMD_0          0
 236 #define R300_VIC_CNTL_0         1
 237 #define R300_VIC_CNTL_1         2
 238 #define R300_VIC_CMDSIZE        3
 239
 240 #define R300_VOF_CMD_0          0
 241 #define R300_VOF_CNTL_0         1
 242 #define R300_VOF_CNTL_1         2
 243 #define R300_VOF_CMDSIZE        3
 244
 245 #define R300_PVS_CMD_0          0
 246 #define R300_PVS_CNTL_1         1
 247 #define R300_PVS_CNTL_2         2
 248 #define R300_PVS_CNTL_3         3
 249 #define R300_PVS_CMDSIZE        4
 250
 251 #define R300_GB_MISC_CMD_0              0
 252 #define R300_GB_MISC_MSPOS_0            1
 253 #define R300_GB_MISC_MSPOS_1            2
 254 #define R300_GB_MISC_TILE_CONFIG        3
 255 #define R300_GB_MISC_SELECT             4
 256 #define R300_GB_MISC_AA_CONFIG          5
 257 #define R300_GB_MISC_CMDSIZE            6
 258
 259 #define R300_TXE_CMD_0          0
 260 #define R300_TXE_ENABLE         1
 261 #define R300_TXE_CMDSIZE        2
 262
 263 #define R300_PS_CMD_0           0
 264 #define R300_PS_POINTSIZE       1
 265 #define R300_PS_CMDSIZE         2
 266
 267 #define R300_ZBS_CMD_0          0
 268 #define R300_ZBS_T_FACTOR       1
 269 #define R300_ZBS_T_CONSTANT     2
 270 #define R300_ZBS_W_FACTOR       3
 271 #define R300_ZBS_W_CONSTANT     4
 272 #define R300_ZBS_CMDSIZE        5
 273
 274 #define R300_CUL_CMD_0          0
 275 #define R300_CUL_CULL           1
 276 #define R300_CUL_CMDSIZE        2
 277
 278 #define R300_RC_CMD_0           0
 279 #define R300_RC_CNTL_0          1
 280 #define R300_RC_CNTL_1          2
 281 #define R300_RC_CMDSIZE         3
 282
 283 #define R300_RI_CMD_0           0
 284 #define R300_RI_INTERP_0        1
 285 #define R300_RI_INTERP_1        2
 286 #define R300_RI_INTERP_2        3
 287 #define R300_RI_INTERP_3        4
 288 #define R300_RI_INTERP_4        5
 289 #define R300_RI_INTERP_5        6
 290 #define R300_RI_INTERP_6        7
 291 #define R300_RI_INTERP_7        8
 292 #define R300_RI_CMDSIZE         9
 293
 294 #define R500_RI_CMDSIZE        17
 295
 296 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 297 #define R300_RR_INST_0          1
 298 #define R300_RR_INST_1          2
 299 #define R300_RR_INST_2          3
 300 #define R300_RR_INST_3          4
 301 #define R300_RR_INST_4          5
 302 #define R300_RR_INST_5          6
 303 #define R300_RR_INST_6          7
 304 #define R300_RR_INST_7          8
 305 #define R300_RR_CMDSIZE         9
 306
 307 #define R300_FP_CMD_0           0
 308 #define R300_FP_CNTL0           1
 309 #define R300_FP_CNTL1           2
 310 #define R300_FP_CNTL2           3
 311 #define R300_FP_CMD_1           4
 312 #define R300_FP_NODE0           5
 313 #define R300_FP_NODE1           6
 314 #define R300_FP_NODE2           7
 315 #define R300_FP_NODE3           8
 316 #define R300_FP_CMDSIZE         9
 317
 318 #define R500_FP_CMD_0           0
 319 #define R500_FP_CNTL            1
 320 #define R500_FP_PIXSIZE         2
 321 #define R500_FP_CMD_1           3
 322 #define R500_FP_CODE_ADDR       4
 323 #define R500_FP_CODE_RANGE      5
 324 #define R500_FP_CODE_OFFSET     6
 325 #define R500_FP_CMD_2           7
 326 #define R500_FP_FC_CNTL         8
 327 #define R500_FP_CMDSIZE         9
 328
 329 #define R300_FPT_CMD_0          0
 330 #define R300_FPT_INSTR_0        1
 331 #define R300_FPT_CMDSIZE        65
 332
 333 #define R300_FPI_CMD_0          0
 334 #define R300_FPI_INSTR_0        1
 335 #define R300_FPI_CMDSIZE        65
 336 /* R500 has space for 512 instructions - 6 dwords per instruction */
 337 #define R500_FPI_CMDSIZE        (512*6+1)
 338
 339 #define R300_FPP_CMD_0          0
 340 #define R300_FPP_PARAM_0        1
 341 #define R300_FPP_CMDSIZE        (32*4+1)
 342 /* R500 has spcae for 256 constants - 4 dwords per constant */
 343 #define R500_FPP_CMDSIZE        (256*4+1)
 344
 345 #define R300_FOGS_CMD_0         0
 346 #define R300_FOGS_STATE         1
 347 #define R300_FOGS_CMDSIZE       2
 348
 349 #define R300_FOGC_CMD_0         0
 350 #define R300_FOGC_R             1
 351 #define R300_FOGC_G             2
 352 #define R300_FOGC_B             3
 353 #define R300_FOGC_CMDSIZE       4
 354
 355 #define R300_FOGP_CMD_0         0
 356 #define R300_FOGP_SCALE         1
 357 #define R300_FOGP_START         2
 358 #define R300_FOGP_CMDSIZE       3
 359
 360 #define R300_AT_CMD_0           0
 361 #define R300_AT_ALPHA_TEST      1
 362 #define R300_AT_UNKNOWN         2
 363 #define R300_AT_CMDSIZE         3
 364
 365 #define R300_BLD_CMD_0          0
 366 #define R300_BLD_CBLEND         1
 367 #define R300_BLD_ABLEND         2
 368 #define R300_BLD_CMDSIZE        3
 369
 370 #define R300_CMK_CMD_0          0
 371 #define R300_CMK_COLORMASK      1
 372 #define R300_CMK_CMDSIZE        2
 373
 374 #define R300_CB_CMD_0           0
 375 #define R300_CB_OFFSET          1
 376 #define R300_CB_CMD_1           2
 377 #define R300_CB_PITCH           3
 378 #define R300_CB_CMDSIZE         4
 379
 380 #define R300_ZS_CMD_0           0
 381 #define R300_ZS_CNTL_0          1
 382 #define R300_ZS_CNTL_1          2
 383 #define R300_ZS_CNTL_2          3
 384 #define R300_ZS_CMDSIZE         4
 385
 386 #define R300_ZB_CMD_0           0
 387 #define R300_ZB_OFFSET          1
 388 #define R300_ZB_PITCH           2
 389 #define R300_ZB_CMDSIZE         3
 390
 391 #define R300_VAP_CNTL_FLUSH     0
 392 #define R300_VAP_CNTL_FLUSH_1   1
 393 #define R300_VAP_CNTL_CMD       2
 394 #define R300_VAP_CNTL_INSTR     3
 395 #define R300_VAP_CNTL_SIZE      4
 396
 397 #define R300_VPI_CMD_0          0
 398 #define R300_VPI_INSTR_0        1
 399 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 400
 401 #define R300_VPP_CMD_0          0
 402 #define R300_VPP_PARAM_0        1
 403 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 404
 405 #define R300_VPUCP_CMD_0                0
 406 #define R300_VPUCP_X            1
 407 #define R300_VPUCP_Y            2
 408 #define R300_VPUCP_Z            3
 409 #define R300_VPUCP_W            4
 410 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 411
 412 #define R300_VPS_CMD_0          0
 413 #define R300_VPS_ZERO_0         1
 414 #define R300_VPS_ZERO_1         2
 415 #define R300_VPS_POINTSIZE      3
 416 #define R300_VPS_ZERO_3         4
 417 #define R300_VPS_CMDSIZE        5
 418
 419         /* the layout is common for all fields inside tex */
 420 #define R300_TEX_CMD_0          0
 421 #define R300_TEX_VALUE_0        1
 422 /* We don't really use this, instead specify mtu+1 dynamically
 423 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 424 */
 425
 426 /**
 427  * Cache for hardware register state.
 428  */
 429 struct r300_hw_state {
 430         struct r300_state_atom atomlist;
 431
 432         GLboolean is_dirty;
 433         GLboolean all_dirty;
 434         int max_state_size;     /* in dwords */
 435
 436         struct r300_state_atom vpt;     /* viewport (1D98) */
 437         struct r300_state_atom vap_cntl;
 438         struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */
 439         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 440         struct r300_state_atom vte;     /* (20B0) */
 441         struct r300_state_atom vap_vf_max_vtx_indx;     /* Maximum Vertex Indx Clamp (2134) */
 442         struct r300_state_atom vap_cntl_status;
 443         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 444         struct r300_state_atom vic;     /* vap input control (2180) */
 445         struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 446         struct r300_state_atom vap_clip_cntl;
 447         struct r300_state_atom vap_clip;
 448         struct r300_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */
 449         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 450         struct r300_state_atom gb_enable;       /* (4008) */
 451         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 452         struct r300_state_atom ga_point_s0;     /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 453         struct r300_state_atom ga_triangle_stipple;     /* (4214) */
 454         struct r300_state_atom ps;      /* pointsize (421C) */
 455         struct r300_state_atom ga_point_minmax; /* (4230) */
 456         struct r300_state_atom lcntl;   /* line control */
 457         struct r300_state_atom ga_line_stipple; /* (4260) */
 458         struct r300_state_atom shade;
 459         struct r300_state_atom polygon_mode;
 460         struct r300_state_atom fogp;    /* fog parameters (4294) */
 461         struct r300_state_atom ga_soft_reset;   /* (429C) */
 462         struct r300_state_atom zbias_cntl;
 463         struct r300_state_atom zbs;     /* zbias (42A4) */
 464         struct r300_state_atom occlusion_cntl;
 465         struct r300_state_atom cul;     /* cull cntl (42B8) */
 466         struct r300_state_atom su_depth_scale;  /* (42C0) */
 467         struct r300_state_atom rc;      /* rs control (4300) */
 468         struct r300_state_atom ri;      /* rs interpolators (4310) */
 469         struct r300_state_atom rr;      /* rs route (4330) */
 470         struct r300_state_atom sc_hyperz;       /* (43A4) */
 471         struct r300_state_atom sc_screendoor;   /* (43E8) */
 472         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 473         struct r300_state_atom fpt;     /* texi - (4620) */
 474         struct r300_state_atom us_out_fmt;      /* (46A4) */
 475         struct r300_state_atom r500fp;  /* r500 fp instructions */
 476         struct r300_state_atom r500fp_const;    /* r500 fp constants */
 477         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 478         struct r300_state_atom fogs;    /* fog state (4BC0) */
 479         struct r300_state_atom fogc;    /* fog color (4BC8) */
 480         struct r300_state_atom at;      /* alpha test (4BD4) */
 481         struct r300_state_atom fg_depth_src;    /* (4BD8) */
 482         struct r300_state_atom fpp;     /* 0x4C00 and following */
 483         struct r300_state_atom rb3d_cctl;       /* (4E00) */
 484         struct r300_state_atom bld;     /* blending (4E04) */
 485         struct r300_state_atom cmk;     /* colormask (4E0C) */
 486         struct r300_state_atom blend_color;     /* constant blend color */
 487         struct r300_state_atom rop;     /* ropcntl */
 488         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 489         struct r300_state_atom rb3d_dither_ctl; /* (4E50) */
 490         struct r300_state_atom rb3d_aaresolve_ctl;      /* (4E88) */
 491         struct r300_state_atom rb3d_discard_src_pixel_lte_threshold;    /* (4E88) I saw it only written on RV350 hardware..  */
 492         struct r300_state_atom zs;      /* zstencil control (4F00) */
 493         struct r300_state_atom zstencil_format;
 494         struct r300_state_atom zb;      /* z buffer (4F20) */
 495         struct r300_state_atom zb_depthclearvalue;      /* (4F28) */
 496         struct r300_state_atom unk4F30; /* (4F30) */
 497         struct r300_state_atom zb_hiz_offset;   /* (4F44) */
 498         struct r300_state_atom zb_hiz_pitch;    /* (4F54) */
 499
 500         struct r300_state_atom vpi;     /* vp instructions */
 501         struct r300_state_atom vpp;     /* vp parameters */
 502         struct r300_state_atom vps;     /* vertex point size (?) */
 503         struct r300_state_atom vpucp[6];        /* vp user clip plane - 6 */
 504         /* 8 texture units */
 505         /* the state is grouped by function and not by
 506            texture unit. This makes single unit updates
 507            really awkward - we are much better off
 508            updating the whole thing at once */
 509         struct {
 510                 struct r300_state_atom filter;
 511                 struct r300_state_atom filter_1;
 512                 struct r300_state_atom size;
 513                 struct r300_state_atom format;
 514                 struct r300_state_atom pitch;
 515                 struct r300_state_atom offset;
 516                 struct r300_state_atom chroma_key;
 517                 struct r300_state_atom border_color;
 518         } tex;
 519         struct r300_state_atom txe;     /* tex enable (4104) */
 520
 521         r300TexObj *textures[R300_MAX_TEXTURE_UNITS];
 522 };
 523
 524 /**
 525  * This structure holds the command buffer while it is being constructed.
 526  *
 527  * The first batch of commands in the buffer is always the state that needs
 528  * to be re-emitted when the context is lost. This batch can be skipped
 529  * otherwise.
 530  */
 531 struct r300_cmdbuf {
 532     struct radeon_cs_manager    *csm;
 533     struct radeon_cs            *cs;
 534         int size; /** # of dwords total */
 535         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 536 };
 537
 538 /**
 539  * State cache
 540  */
 541
 542 struct r300_depthbuffer_state {
 543         GLfloat scale;
 544 };
 545
 546 struct r300_stencilbuffer_state {
 547         GLboolean hw_stencil;
 548 };
 549
 550 /* Vertex shader state */
 551
 552 /* Perhaps more if we store programs in vmem? */
 553 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 554 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 555
 556 /* Can be tested with colormat currently. */
 557 #define VSF_MAX_FRAGMENT_TEMPS (14)
 558
 559 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 560 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 561
 562 struct r300_vertex_shader_fragment {
 563         int length;
 564         union {
 565                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 566                 float f[VSF_MAX_FRAGMENT_LENGTH];
 567                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 568         } body;
 569 };
 570
 571 struct r300_vertex_shader_state {
 572         struct r300_vertex_shader_fragment program;
 573 };
 574
 575 extern int hw_tcl_on;
 576
 577 #define COLOR_IS_RGBA
 578 #define TAG(x) r300##x
 579 #include "tnl_dd/t_dd_vertex.h"
 580 #undef TAG
 581
 582 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 583 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 584
 585 /* Should but doesnt work */
 586 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 587
 588 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 589  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 590  */
 591
 592 struct r300_vertex_program_key {
 593         GLuint InputsRead;
 594         GLuint OutputsWritten;
 595         GLuint OutputsAdded;
 596 };
 597
 598 struct r300_vertex_program {
 599         struct r300_vertex_program *next;
 600         struct r300_vertex_program_key key;
 601         int translated;
 602
 603         struct r300_vertex_shader_fragment program;
 604
 605         int pos_end;
 606         int num_temporaries;    /* Number of temp vars used by program */
 607         int wpos_idx;
 608         int inputs[VERT_ATTRIB_MAX];
 609         int outputs[VERT_RESULT_MAX];
 610         int native;
 611         int ref_count;
 612         int use_ref_count;
 613 };
 614
 615 struct r300_vertex_program_cont {
 616         struct gl_vertex_program mesa_program;  /* Must be first */
 617         struct r300_vertex_shader_fragment params;
 618         struct r300_vertex_program *progs;
 619 };
 620
 621 #define PFS_MAX_ALU_INST        64
 622 #define PFS_MAX_TEX_INST        64
 623 #define PFS_MAX_TEX_INDIRECT 4
 624 #define PFS_NUM_TEMP_REGS       32
 625 #define PFS_NUM_CONST_REGS      16
 626
 627 struct r300_pfs_compile_state;
 628
 629
 630 /**
 631  * Stores state that influences the compilation of a fragment program.
 632  */
 633 struct r300_fragment_program_external_state {
 634         struct {
 635                 /**
 636                  * If the sampler is used as a shadow sampler,
 637                  * this field is:
 638                  *  0 - GL_LUMINANCE
 639                  *  1 - GL_INTENSITY
 640                  *  2 - GL_ALPHA
 641                  * depending on the depth texture mode.
 642                  */
 643                 GLuint depth_texture_mode : 2;
 644
 645                 /**
 646                  * If the sampler is used as a shadow sampler,
 647                  * this field is (texture_compare_func - GL_NEVER).
 648                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 649                  *
 650                  * Otherwise, this field is 0.
 651                  */
 652                 GLuint texture_compare_func : 3;
 653         } unit[16];
 654 };
 655
 656
 657 struct r300_fragment_program_node {
 658         int tex_offset; /**< first tex instruction */
 659         int tex_end; /**< last tex instruction, relative to tex_offset */
 660         int alu_offset; /**< first ALU instruction */
 661         int alu_end; /**< last ALU instruction, relative to alu_offset */
 662         int flags;
 663 };
 664
 665 /**
 666  * Stores an R300 fragment program in its compiled-to-hardware form.
 667  */
 668 struct r300_fragment_program_code {
 669         struct {
 670                 int length; /**< total # of texture instructions used */
 671                 GLuint inst[PFS_MAX_TEX_INST];
 672         } tex;
 673
 674         struct {
 675                 int length; /**< total # of ALU instructions used */
 676                 struct {
 677                         GLuint inst0;
 678                         GLuint inst1;
 679                         GLuint inst2;
 680                         GLuint inst3;
 681                 } inst[PFS_MAX_ALU_INST];
 682         } alu;
 683
 684         struct r300_fragment_program_node node[4];
 685         int cur_node;
 686         int first_node_has_tex;
 687
 688         /**
 689          * Remember which program register a given hardware constant
 690          * belongs to.
 691          */
 692         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 693         int const_nr;
 694
 695         int max_temp_idx;
 696 };
 697
 698 /**
 699  * Store everything about a fragment program that is needed
 700  * to render with that program.
 701  */
 702 struct r300_fragment_program {
 703         struct gl_fragment_program mesa_program;
 704
 705         GLboolean translated;
 706         GLboolean error;
 707
 708         struct r300_fragment_program_external_state state;
 709         struct r300_fragment_program_code code;
 710
 711         GLboolean WritesDepth;
 712         GLuint optimization;
 713 };
 714
 715 struct r500_pfs_compile_state;
 716
 717 struct r500_fragment_program_external_state {
 718         struct {
 719                 /**
 720                  * If the sampler is used as a shadow sampler,
 721                  * this field is:
 722                  *  0 - GL_LUMINANCE
 723                  *  1 - GL_INTENSITY
 724                  *  2 - GL_ALPHA
 725                  * depending on the depth texture mode.
 726                  */
 727                 GLuint depth_texture_mode : 2;
 728
 729                 /**
 730                  * If the sampler is used as a shadow sampler,
 731                  * this field is (texture_compare_func - GL_NEVER).
 732                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 733                  *
 734                  * Otherwise, this field is 0.
 735                  */
 736                 GLuint texture_compare_func : 3;
 737         } unit[16];
 738 };
 739
 740 struct r500_fragment_program_code {
 741         struct {
 742                 GLuint inst0;
 743                 GLuint inst1;
 744                 GLuint inst2;
 745                 GLuint inst3;
 746                 GLuint inst4;
 747                 GLuint inst5;
 748         } inst[512];
 749
 750         int inst_offset;
 751         int inst_end;
 752
 753         /**
 754          * Remember which program register a given hardware constant
 755          * belongs to.
 756          */
 757         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 758         int const_nr;
 759
 760         int max_temp_idx;
 761 };
 762
 763 struct r500_fragment_program {
 764         struct gl_fragment_program mesa_program;
 765
 766         GLcontext *ctx;
 767         GLboolean translated;
 768         GLboolean error;
 769
 770         struct r500_fragment_program_external_state state;
 771         struct r500_fragment_program_code code;
 772
 773         GLboolean writes_depth;
 774
 775         GLuint optimization;
 776 };
 777
 778 #define R300_MAX_AOS_ARRAYS             16
 779
 780 #define REG_COORDS      0
 781 #define REG_COLOR0      1
 782 #define REG_TEX0        2
 783
 784 struct r300_aos {
 785         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 786         int offset; /** Offset into buffer object, in bytes */
 787         int components; /** Number of components per vertex */
 788         int stride; /** Stride in dwords (may be 0 for repeating) */
 789         int count; /** Number of vertices */
 790 };
 791
 792 struct r300_state {
 793         struct r300_depthbuffer_state depth;
 794         struct r300_texture_state texture;
 795         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 796         struct r300_vertex_shader_state vertex_shader;
 797         struct r300_aos aos[R300_MAX_AOS_ARRAYS];
 798         int aos_count;
 799
 800         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 801         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 802
 803         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 804                                                            They are the same as tnl->render_inputs for fixed pipeline */
 805
 806         struct r300_stencilbuffer_state stencil;
 807
 808 };
 809
 810 #define R300_FALLBACK_NONE 0
 811 #define R300_FALLBACK_TCL 1
 812 #define R300_FALLBACK_RAST 2
 813
 814 /* r300_swtcl.c
 815  */
 816 struct r300_swtcl_info {
 817    GLuint RenderIndex;
 818
 819    /**
 820     * Size of a hardware vertex.  This is calculated when \c ::vertex_attrs is
 821     * installed in the Mesa state vector.
 822     */
 823    GLuint vertex_size;
 824
 825    /**
 826     * Attributes instructing the Mesa TCL pipeline where / how to put vertex
 827     * data in the hardware buffer.
 828     */
 829    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 830
 831    /**
 832     * Number of elements of \c ::vertex_attrs that are actually used.
 833     */
 834    GLuint vertex_attr_count;
 835
 836    /**
 837     * Cached pointer to the buffer where Mesa will store vertex data.
 838     */
 839    GLubyte *verts;
 840
 841    /* Fallback rasterization functions
 842     */
 843   //   r200_point_func draw_point;
 844   //   r200_line_func draw_line;
 845   //   r200_tri_func draw_tri;
 846
 847    GLuint hw_primitive;
 848    GLenum render_primitive;
 849    GLuint numverts;
 850
 851    /**
 852     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 853     */
 854    GLuint coloroffset;
 855
 856    /**
 857     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 858     */
 859    GLuint specoffset;
 860
 861    struct radeon_bo *bo;
 862    void (*flush) (r300ContextPtr);
 863 };
 864
 865
 866 /**
 867  * \brief R300 context structure.
 868  */
 869 struct r300_context {
 870         struct radeon_context radeon;   /* parent class, must be first */
 871
 872         struct r300_hw_state hw;
 873         struct r300_cmdbuf cmdbuf;
 874         struct r300_state state;
 875         struct gl_vertex_program *curr_vp;
 876         struct r300_vertex_program *selected_vp;
 877
 878         /* Vertex buffers
 879          */
 880         GLuint NewGLState;
 881
 882         int texture_depth;
 883         float initialMaxAnisotropy;
 884
 885         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 886         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 887
 888         GLboolean disable_lowimpact_fallback;
 889
 890         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 891         struct r300_swtcl_info swtcl;
 892 };
 893
 894 struct r300_buffer_object {
 895         struct gl_buffer_object mesa_obj;
 896         int id;
 897 };
 898
 899 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 900
 901 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 902 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 903                                    __DRIcontextPrivate * driContextPriv,
 904                                    void *sharedContextPrivate);
 905
 906 extern void r300SelectVertexShader(r300ContextPtr r300);
 907 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 908 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 909                                       struct r300_vertex_program_cont *vp,
 910                                       float *dst);
 911
 912 #define RADEON_D_CAPTURE 0
 913 #define RADEON_D_PLAYBACK 1
 914 #define RADEON_D_PLAYBACK_RAW 2
 915 #define RADEON_D_T 3
 916
 917 #endif                          /* __R300_CONTEXT_H__ */