src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "radeon_common.h"
  44
  45 #include "main/mtypes.h"
  46 #include "shader/prog_instruction.h"
  47 #include "compiler/radeon_code.h"
  48
  49 struct r300_context;
  50 typedef struct r300_context r300ContextRec;
  51 typedef struct r300_context *r300ContextPtr;
  52
  53
  54 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  55    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  56    with other compilers ... GLUE!
  57 */
  58 #define WARN_ONCE(a, ...)       { \
  59         static int warn##__LINE__=1; \
  60         if(warn##__LINE__){ \
  61                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  62                 fprintf(stderr, "File %s function %s line %d\n", \
  63                         __FILE__, __FUNCTION__, __LINE__); \
  64                 fprintf(stderr,  a, ## __VA_ARGS__);\
  65                 fprintf(stderr, "***************************************************************************\n"); \
  66                 warn##__LINE__=0;\
  67                 } \
  68         }
  69
  70 #include "r300_vertprog.h"
  71
  72
  73 /* The blit width for texture uploads
  74  */
  75 #define R300_BLIT_WIDTH_BYTES 1024
  76 #define R300_MAX_TEXTURE_UNITS 8
  77
  78
  79
  80 #define R300_VPT_CMD_0          0
  81 #define R300_VPT_XSCALE         1
  82 #define R300_VPT_XOFFSET        2
  83 #define R300_VPT_YSCALE         3
  84 #define R300_VPT_YOFFSET        4
  85 #define R300_VPT_ZSCALE         5
  86 #define R300_VPT_ZOFFSET        6
  87 #define R300_VPT_CMDSIZE        7
  88
  89 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  90 #define R300_VIR_CNTL_0         1
  91 #define R300_VIR_CNTL_1         2
  92 #define R300_VIR_CNTL_2         3
  93 #define R300_VIR_CNTL_3         4
  94 #define R300_VIR_CNTL_4         5
  95 #define R300_VIR_CNTL_5         6
  96 #define R300_VIR_CNTL_6         7
  97 #define R300_VIR_CNTL_7         8
  98 #define R300_VIR_CMDSIZE        9
  99
 100 #define R300_VIC_CMD_0          0
 101 #define R300_VIC_CNTL_0         1
 102 #define R300_VIC_CNTL_1         2
 103 #define R300_VIC_CMDSIZE        3
 104
 105 #define R300_VOF_CMD_0          0
 106 #define R300_VOF_CNTL_0         1
 107 #define R300_VOF_CNTL_1         2
 108 #define R300_VOF_CMDSIZE        3
 109
 110 #define R300_PVS_CMD_0          0
 111 #define R300_PVS_CNTL_1         1
 112 #define R300_PVS_CNTL_2         2
 113 #define R300_PVS_CNTL_3         3
 114 #define R300_PVS_CMDSIZE        4
 115
 116 #define R300_GB_MISC_CMD_0              0
 117 #define R300_GB_MISC_MSPOS_0            1
 118 #define R300_GB_MISC_MSPOS_1            2
 119 #define R300_GB_MISC_TILE_CONFIG        3
 120 #define R300_GB_MISC_CMDSIZE            4
 121 #define R300_GB_MISC2_CMD_0                 0
 122 #define R300_GB_MISC2_SELECT            1
 123 #define R300_GB_MISC2_AA_CONFIG         2
 124 #define R300_GB_MISC2_CMDSIZE           3
 125
 126 #define R300_TXE_CMD_0          0
 127 #define R300_TXE_ENABLE         1
 128 #define R300_TXE_CMDSIZE        2
 129
 130 #define R300_PS_CMD_0           0
 131 #define R300_PS_POINTSIZE       1
 132 #define R300_PS_CMDSIZE         2
 133
 134 #define R300_ZBS_CMD_0          0
 135 #define R300_ZBS_T_FACTOR       1
 136 #define R300_ZBS_T_CONSTANT     2
 137 #define R300_ZBS_W_FACTOR       3
 138 #define R300_ZBS_W_CONSTANT     4
 139 #define R300_ZBS_CMDSIZE        5
 140
 141 #define R300_CUL_CMD_0          0
 142 #define R300_CUL_CULL           1
 143 #define R300_CUL_CMDSIZE        2
 144
 145 #define R300_RC_CMD_0           0
 146 #define R300_RC_CNTL_0          1
 147 #define R300_RC_CNTL_1          2
 148 #define R300_RC_CMDSIZE         3
 149
 150 #define R300_RI_CMD_0           0
 151 #define R300_RI_INTERP_0        1
 152 #define R300_RI_INTERP_1        2
 153 #define R300_RI_INTERP_2        3
 154 #define R300_RI_INTERP_3        4
 155 #define R300_RI_INTERP_4        5
 156 #define R300_RI_INTERP_5        6
 157 #define R300_RI_INTERP_6        7
 158 #define R300_RI_INTERP_7        8
 159 #define R300_RI_CMDSIZE         9
 160
 161 #define R500_RI_CMDSIZE        17
 162
 163 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 164 #define R300_RR_INST_0          1
 165 #define R300_RR_INST_1          2
 166 #define R300_RR_INST_2          3
 167 #define R300_RR_INST_3          4
 168 #define R300_RR_INST_4          5
 169 #define R300_RR_INST_5          6
 170 #define R300_RR_INST_6          7
 171 #define R300_RR_INST_7          8
 172 #define R300_RR_CMDSIZE         9
 173
 174 #define R300_FP_CMD_0           0
 175 #define R300_FP_CNTL0           1
 176 #define R300_FP_CNTL1           2
 177 #define R300_FP_CNTL2           3
 178 #define R300_FP_CMD_1           4
 179 #define R300_FP_NODE0           5
 180 #define R300_FP_NODE1           6
 181 #define R300_FP_NODE2           7
 182 #define R300_FP_NODE3           8
 183 #define R300_FP_CMDSIZE         9
 184
 185 #define R500_FP_CMD_0           0
 186 #define R500_FP_CNTL            1
 187 #define R500_FP_PIXSIZE         2
 188 #define R500_FP_CMD_1           3
 189 #define R500_FP_CODE_ADDR       4
 190 #define R500_FP_CODE_RANGE      5
 191 #define R500_FP_CODE_OFFSET     6
 192 #define R500_FP_CMD_2           7
 193 #define R500_FP_FC_CNTL         8
 194 #define R500_FP_CMDSIZE         9
 195
 196 #define R300_FPT_CMD_0          0
 197 #define R300_FPT_INSTR_0        1
 198 #define R300_FPT_CMDSIZE        65
 199
 200 #define R300_FPI_CMD_0          0
 201 #define R300_FPI_INSTR_0        1
 202 #define R300_FPI_CMDSIZE        65
 203 /* R500 has space for 512 instructions - 6 dwords per instruction */
 204 #define R500_FPI_CMDSIZE        (512*6+1)
 205
 206 #define R300_FPP_CMD_0          0
 207 #define R300_FPP_PARAM_0        1
 208 #define R300_FPP_CMDSIZE        (32*4+1)
 209 /* R500 has spcae for 256 constants - 4 dwords per constant */
 210 #define R500_FPP_CMDSIZE        (256*4+1)
 211
 212 #define R300_FOGS_CMD_0         0
 213 #define R300_FOGS_STATE         1
 214 #define R300_FOGS_CMDSIZE       2
 215
 216 #define R300_FOGC_CMD_0         0
 217 #define R300_FOGC_R             1
 218 #define R300_FOGC_G             2
 219 #define R300_FOGC_B             3
 220 #define R300_FOGC_CMDSIZE       4
 221
 222 #define R300_FOGP_CMD_0         0
 223 #define R300_FOGP_SCALE         1
 224 #define R300_FOGP_START         2
 225 #define R300_FOGP_CMDSIZE       3
 226
 227 #define R300_AT_CMD_0           0
 228 #define R300_AT_ALPHA_TEST      1
 229 #define R300_AT_UNKNOWN         2
 230 #define R300_AT_CMDSIZE         3
 231
 232 #define R300_BLD_CMD_0          0
 233 #define R300_BLD_CBLEND         1
 234 #define R300_BLD_ABLEND         2
 235 #define R300_BLD_CMDSIZE        3
 236
 237 #define R300_CMK_CMD_0          0
 238 #define R300_CMK_COLORMASK      1
 239 #define R300_CMK_CMDSIZE        2
 240
 241 #define R300_CB_CMD_0           0
 242 #define R300_CB_OFFSET          1
 243 #define R300_CB_CMD_1           2
 244 #define R300_CB_PITCH           3
 245 #define R300_CB_CMDSIZE         4
 246
 247 #define R300_ZS_CMD_0           0
 248 #define R300_ZS_CNTL_0          1
 249 #define R300_ZS_CNTL_1          2
 250 #define R300_ZS_CNTL_2          3
 251 #define R300_ZS_CMDSIZE         4
 252
 253 #define R300_ZB_CMD_0           0
 254 #define R300_ZB_OFFSET          1
 255 #define R300_ZB_PITCH           2
 256 #define R300_ZB_CMDSIZE         3
 257
 258 #define R300_VAP_CNTL_FLUSH     0
 259 #define R300_VAP_CNTL_FLUSH_1   1
 260 #define R300_VAP_CNTL_CMD       2
 261 #define R300_VAP_CNTL_INSTR     3
 262 #define R300_VAP_CNTL_SIZE      4
 263
 264 #define R300_VPI_CMD_0          0
 265 #define R300_VPI_INSTR_0        1
 266 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 267
 268 #define R300_VPP_CMD_0          0
 269 #define R300_VPP_PARAM_0        1
 270 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 271
 272 #define R300_VPUCP_CMD_0                0
 273 #define R300_VPUCP_X            1
 274 #define R300_VPUCP_Y            2
 275 #define R300_VPUCP_Z            3
 276 #define R300_VPUCP_W            4
 277 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 278
 279 #define R300_VPS_CMD_0          0
 280 #define R300_VPS_ZERO_0         1
 281 #define R300_VPS_ZERO_1         2
 282 #define R300_VPS_POINTSIZE      3
 283 #define R300_VPS_ZERO_3         4
 284 #define R300_VPS_CMDSIZE        5
 285
 286         /* the layout is common for all fields inside tex */
 287 #define R300_TEX_CMD_0          0
 288 #define R300_TEX_VALUE_0        1
 289 /* We don't really use this, instead specify mtu+1 dynamically
 290 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 291 */
 292
 293 /**
 294  * Cache for hardware register state.
 295  */
 296 struct r300_hw_state {
 297         struct radeon_state_atom vpt;   /* viewport (1D98) */
 298         struct radeon_state_atom vap_cntl;
 299         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 300         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 301         struct radeon_state_atom vte;   /* (20B0) */
 302         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 303         struct radeon_state_atom vap_cntl_status;
 304         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 305         struct radeon_state_atom vic;   /* vap input control (2180) */
 306         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 307         struct radeon_state_atom vap_clip_cntl;
 308         struct radeon_state_atom vap_clip;
 309         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 310         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 311         struct radeon_state_atom gb_enable;     /* (4008) */
 312         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 313         struct radeon_state_atom gb_misc2;      /* Multisampling position shifts ? (4010) */
 314         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 315         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 316         struct radeon_state_atom ps;    /* pointsize (421C) */
 317         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 318         struct radeon_state_atom lcntl; /* line control */
 319         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 320         struct radeon_state_atom shade;
 321         struct radeon_state_atom shade2;
 322         struct radeon_state_atom polygon_mode;
 323         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 324         struct radeon_state_atom ga_soft_reset; /* (429C) */
 325         struct radeon_state_atom zbias_cntl;
 326         struct radeon_state_atom zbs;   /* zbias (42A4) */
 327         struct radeon_state_atom occlusion_cntl;
 328         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 329         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 330         struct radeon_state_atom rc;    /* rs control (4300) */
 331         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 332         struct radeon_state_atom rr;    /* rs route (4330) */
 333         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 334         struct radeon_state_atom sc_screendoor; /* (43E8) */
 335         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 336         struct radeon_state_atom fpt;   /* texi - (4620) */
 337         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 338         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 339         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 340         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 341         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 342         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 343         struct radeon_state_atom at;    /* alpha test (4BD4) */
 344         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 345         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 346         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 347         struct radeon_state_atom bld;   /* blending (4E04) */
 348         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 349         struct radeon_state_atom blend_color;   /* constant blend color */
 350         struct radeon_state_atom rop;   /* ropcntl */
 351         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 352         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 353         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 354         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 355         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 356         struct radeon_state_atom zstencil_format;
 357         struct radeon_state_atom zb;    /* z buffer (4F20) */
 358         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 359         struct radeon_state_atom zb_zmask;      /* (4F30) */
 360         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 361         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 362
 363         struct radeon_state_atom vpi;   /* vp instructions */
 364         struct radeon_state_atom vpp;   /* vp parameters */
 365         struct radeon_state_atom vps;   /* vertex point size (?) */
 366         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 367         /* 8 texture units */
 368         /* the state is grouped by function and not by
 369            texture unit. This makes single unit updates
 370            really awkward - we are much better off
 371            updating the whole thing at once */
 372         struct {
 373                 struct radeon_state_atom filter;
 374                 struct radeon_state_atom filter_1;
 375                 struct radeon_state_atom size;
 376                 struct radeon_state_atom format;
 377                 struct radeon_state_atom pitch;
 378                 struct radeon_state_atom offset;
 379                 struct radeon_state_atom chroma_key;
 380                 struct radeon_state_atom border_color;
 381         } tex;
 382         struct radeon_state_atom txe;   /* tex enable (4104) */
 383
 384         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 385 };
 386
 387 /**
 388  * State cache
 389  */
 390
 391 /* Vertex shader state */
 392
 393 #define COLOR_IS_RGBA
 394 #define TAG(x) r300##x
 395 #include "tnl_dd/t_dd_vertex.h"
 396 #undef TAG
 397
 398 struct r300_vertex_program_key {
 399         GLbitfield FpReads;
 400         GLuint FogAttr;
 401         GLuint WPosAttr;
 402 };
 403
 404 struct r300_vertex_program {
 405         struct gl_vertex_program *Base;
 406         struct r300_vertex_program *next;
 407
 408         struct r300_vertex_program_key key;
 409         struct r300_vertex_program_code code;
 410
 411         GLboolean error;
 412 };
 413
 414 struct r300_vertex_program_cont {
 415         /* This is the unmodified vertex program mesa provided us with.
 416          * We need to keep it unchanged because we may need to create another
 417          * hw specific vertex program based on this.
 418          */
 419         struct gl_vertex_program mesa_program;
 420         /* This is the list of hw specific vertex programs derived from mesa_program */
 421         struct r300_vertex_program *progs;
 422 };
 423
 424
 425 /**
 426 * Store everything about a fragment program that is needed
 427 * to render with that program.
 428 */
 429 struct r300_fragment_program {
 430         GLboolean error;
 431         struct r300_fragment_program *next;
 432         struct r300_fragment_program_external_state state;
 433
 434         struct rX00_fragment_program_code code;
 435         GLbitfield InputsRead;
 436
 437         /* attribute that we are sending the WPOS in */
 438         gl_frag_attrib wpos_attr;
 439         /* attribute that we are sending the fog coordinate in */
 440         gl_frag_attrib fog_attr;
 441 };
 442
 443 struct r300_fragment_program_cont {
 444         /* This is the unmodified fragment program mesa provided us with.
 445          * We need to keep it unchanged because we may need to create another
 446          * hw specific fragment program based on this.
 447          */
 448         struct gl_fragment_program Base;
 449         /* This is the list of hw specific fragment programs derived from Base */
 450         struct r300_fragment_program *progs;
 451 };
 452
 453
 454 #define R300_MAX_AOS_ARRAYS             16
 455
 456
 457 /* r300_swtcl.c
 458  */
 459 struct r300_swtcl_info {
 460   /*
 461     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 462     */
 463    GLuint coloroffset;
 464
 465    /**
 466     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 467     */
 468    GLuint specoffset;
 469 };
 470
 471 struct r300_vtable {
 472         void (* SetupRSUnit)(GLcontext *ctx);
 473         void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings);
 474         void (* SetupPixelShader)(GLcontext *ctx);
 475 };
 476
 477 struct r300_vertex_buffer {
 478         struct vertex_attribute {
 479                 /* generic */
 480                 GLubyte element;
 481                 GLvoid *data;
 482                 GLboolean free_needed;
 483                 GLuint stride;
 484                 GLuint dwords;
 485                 GLubyte size; /* number of components */
 486
 487                 /* hw specific */
 488                 uint32_t data_type:4;
 489                 uint32_t dst_loc:5;
 490                 uint32_t _signed:1;
 491                 uint32_t normalize:1;
 492                 uint32_t swizzle:12;
 493                 uint32_t write_mask:4;
 494         } attribs[VERT_ATTRIB_MAX];
 495
 496         GLubyte num_attribs;
 497 };
 498
 499 struct r300_index_buffer {
 500         GLvoid *ptr;
 501         GLboolean is_32bit;
 502         GLboolean free_needed;
 503         GLuint count;
 504 };
 505
 506 /**
 507  * \brief R300 context structure.
 508  */
 509 struct r300_context {
 510         struct radeon_context radeon;   /* parent class, must be first */
 511
 512         struct r300_vtable vtbl;
 513
 514         struct r300_hw_state hw;
 515
 516         struct r300_vertex_program *selected_vp;
 517         struct r300_fragment_program *selected_fp;
 518
 519         /* Vertex buffers
 520          */
 521         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 522         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 523
 524         struct r300_options {
 525                 uint32_t conformance_mode:1;
 526                 uint32_t hw_tcl_enabled:1;
 527                 uint32_t s3tc_force_enabled:1;
 528                 uint32_t s3tc_force_disabled:1;
 529                 uint32_t stencil_two_side_disabled:1;
 530         } options;
 531
 532         struct r300_swtcl_info swtcl;
 533         struct r300_vertex_buffer vbuf;
 534         struct r300_index_buffer ind_buf;
 535         GLboolean vap_flush_needed;
 536
 537         uint32_t fallback;
 538
 539         DECLARE_RENDERINPUTS(render_inputs_bitset);
 540 };
 541
 542 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 543
 544 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 545 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 546                                    __DRIcontextPrivate * driContextPriv,
 547                                    void *sharedContextPrivate);
 548
 549 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 550
 551 extern void r300InitShaderFunctions(r300ContextPtr r300);
 552
 553 extern void r300InitDraw(GLcontext *ctx);
 554
 555 #define r300PackFloat32 radeonPackFloat32
 556 #define r300PackFloat24 radeonPackFloat24
 557
 558 #endif                          /* __R300_CONTEXT_H__ */