2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
36 #include "main/glheader.h"
37 #include "main/mtypes.h"
38 #include "main/colormac.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
41 #include "main/image.h"
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
46 #include "tnl/t_context.h"
48 #include "r300_context.h"
49 #include "r300_state.h"
50 #include "r300_emit.h"
51 #include "r300_ioctl.h"
54 #if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \
55 SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \
56 SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \
57 SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \
58 SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \
59 SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE
60 #error Cannot change these!
63 #define DEBUG_ALL DEBUG_VERTS
65 #define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
66 (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
68 GLuint
r300VAPInputRoute0(uint32_t * dst
, GLvector4f
** attribptr
,
69 int *inputs
, GLint
* tab
, GLuint nr
)
73 /* type, inputs, stop bit, size */
74 for (i
= 0; i
< nr
; i
+= 2) {
75 /* make sure input is valid, would lockup the gpu */
76 assert(inputs
[tab
[i
]] != -1);
77 dw
= (R300_SIGNED
| DW_SIZE(i
));
79 dw
|= R300_LAST_VEC
<< R300_DATA_TYPE_0_SHIFT
;
81 assert(inputs
[tab
[i
+ 1]] != -1);
83 DW_SIZE(i
+ 1)) << R300_DATA_TYPE_1_SHIFT
;
85 dw
|= R300_LAST_VEC
<< R300_DATA_TYPE_1_SHIFT
;
94 static GLuint
r300VAPInputRoute1Swizzle(int swizzle
[4])
96 return (swizzle
[0] << R300_SWIZZLE_SELECT_X_SHIFT
) |
97 (swizzle
[1] << R300_SWIZZLE_SELECT_Y_SHIFT
) |
98 (swizzle
[2] << R300_SWIZZLE_SELECT_Z_SHIFT
) |
99 (swizzle
[3] << R300_SWIZZLE_SELECT_W_SHIFT
);
102 GLuint
r300VAPInputRoute1(uint32_t * dst
, int swizzle
[][4], GLuint nr
)
106 for (i
= 0; i
< nr
; i
+= 2) {
107 dw
= (r300VAPInputRoute1Swizzle(swizzle
[i
]) |
108 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
|
109 R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
)) << R300_SWIZZLE0_SHIFT
;
111 dw
|= (r300VAPInputRoute1Swizzle(swizzle
[i
+ 1]) |
112 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
|
113 R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
)) << R300_SWIZZLE1_SHIFT
;
118 return (nr
+ 1) >> 1;
121 GLuint
r300VAPInputCntl0(GLcontext
* ctx
, GLuint InputsRead
)
123 /* No idea what this value means. I have seen other values written to
124 * this register... */
128 GLuint
r300VAPInputCntl1(GLcontext
* ctx
, GLuint InputsRead
)
132 if (InputsRead
& (1 << VERT_ATTRIB_POS
))
133 vic_1
|= R300_INPUT_CNTL_POS
;
135 if (InputsRead
& (1 << VERT_ATTRIB_NORMAL
))
136 vic_1
|= R300_INPUT_CNTL_NORMAL
;
138 if (InputsRead
& (1 << VERT_ATTRIB_COLOR0
))
139 vic_1
|= R300_INPUT_CNTL_COLOR
;
141 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++)
142 if (InputsRead
& (1 << (VERT_ATTRIB_TEX0
+ i
))) {
143 vic_1
|= R300_INPUT_CNTL_TC0
<< i
;
149 GLuint
r300VAPOutputCntl0(GLcontext
* ctx
, GLuint OutputsWritten
)
153 if (OutputsWritten
& (1 << VERT_RESULT_HPOS
))
154 ret
|= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
;
156 if (OutputsWritten
& (1 << VERT_RESULT_COL0
))
157 ret
|= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
;
159 if (OutputsWritten
& (1 << VERT_RESULT_COL1
))
160 ret
|= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT
;
162 if (OutputsWritten
& (1 << VERT_RESULT_BFC0
)
163 || OutputsWritten
& (1 << VERT_RESULT_BFC1
))
165 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT
|
166 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT
|
167 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT
;
169 if (OutputsWritten
& (1 << VERT_RESULT_PSIZ
))
170 ret
|= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
;
175 GLuint
r300VAPOutputCntl1(GLcontext
* ctx
, GLuint OutputsWritten
)
177 GLuint i
, ret
= 0, first_free_texcoord
= 0;
179 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
180 if (OutputsWritten
& (1 << (VERT_RESULT_TEX0
+ i
))) {
181 ret
|= (4 << (3 * i
));
182 ++first_free_texcoord
;
186 if (OutputsWritten
& (1 << VERT_RESULT_FOGC
)) {
187 if (first_free_texcoord
> 8) {
188 fprintf(stderr
, "\tout of free texcoords to write fog coord\n");
191 ret
|= 1 << (3 * first_free_texcoord
);
197 /* Emit vertex data to GART memory
198 * Route inputs to the vertex processor
199 * This function should never return R300_FALLBACK_TCL when using software tcl.
201 int r300EmitArrays(GLcontext
* ctx
)
203 r300ContextPtr rmesa
= R300_CONTEXT(ctx
);
204 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
205 struct vertex_buffer
*vb
= &tnl
->vb
;
207 GLuint count
= vb
->Count
;
209 GLuint InputsRead
= 0, OutputsWritten
= 0;
211 int vir_inputs
[VERT_ATTRIB_MAX
];
212 GLint tab
[VERT_ATTRIB_MAX
];
213 int swizzle
[VERT_ATTRIB_MAX
][4];
214 struct r300_vertex_program
*prog
=
215 (struct r300_vertex_program
*)CURRENT_VERTEX_SHADER(ctx
);
218 inputs
= prog
->inputs
;
219 InputsRead
= prog
->key
.InputsRead
;
220 OutputsWritten
= prog
->key
.OutputsWritten
;
222 inputs
= rmesa
->swtcl
.sw_tcl_inputs
;
224 DECLARE_RENDERINPUTS(render_inputs_bitset
);
225 RENDERINPUTS_COPY(render_inputs_bitset
, tnl
->render_inputs_bitset
);
227 vb
->AttribPtr
[VERT_ATTRIB_POS
] = vb
->ClipPtr
;
229 assert(RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_POS
));
230 assert(RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_NORMAL
) == 0);
232 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_POS
)) {
233 InputsRead
|= 1 << VERT_ATTRIB_POS
;
234 OutputsWritten
|= 1 << VERT_RESULT_HPOS
;
237 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_COLOR0
)) {
238 InputsRead
|= 1 << VERT_ATTRIB_COLOR0
;
239 OutputsWritten
|= 1 << VERT_RESULT_COL0
;
242 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_COLOR1
)) {
243 InputsRead
|= 1 << VERT_ATTRIB_COLOR1
;
244 OutputsWritten
|= 1 << VERT_RESULT_COL1
;
247 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
248 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_TEX(i
))) {
249 InputsRead
|= 1 << (VERT_ATTRIB_TEX0
+ i
);
250 OutputsWritten
|= 1 << (VERT_RESULT_TEX0
+ i
);
254 for (i
= 0, nr
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
255 if (InputsRead
& (1 << i
)) {
262 /* Fixed, apply to vir0 only */
263 memcpy(vir_inputs
, inputs
, VERT_ATTRIB_MAX
* sizeof(int));
265 if (InputsRead
& VERT_ATTRIB_POS
)
266 inputs
[VERT_ATTRIB_POS
] = 0;
267 if (InputsRead
& (1 << VERT_ATTRIB_COLOR0
))
268 inputs
[VERT_ATTRIB_COLOR0
] = 2;
269 if (InputsRead
& (1 << VERT_ATTRIB_COLOR1
))
270 inputs
[VERT_ATTRIB_COLOR1
] = 3;
271 for (i
= VERT_ATTRIB_TEX0
; i
<= VERT_ATTRIB_TEX7
; i
++)
272 if (InputsRead
& (1 << i
))
273 inputs
[i
] = 6 + (i
- VERT_ATTRIB_TEX0
);
275 RENDERINPUTS_COPY(rmesa
->render_inputs_bitset
, render_inputs_bitset
);
279 assert(OutputsWritten
);
281 for (i
= 0, nr
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
282 if (InputsRead
& (1 << i
)) {
287 if (nr
> R300_MAX_AOS_ARRAYS
) {
288 return R300_FALLBACK_TCL
;
291 for (i
= 0; i
< nr
; i
++) {
294 swizzle
[i
][0] = SWIZZLE_ZERO
;
295 swizzle
[i
][1] = SWIZZLE_ZERO
;
296 swizzle
[i
][2] = SWIZZLE_ZERO
;
297 swizzle
[i
][3] = SWIZZLE_ONE
;
299 for (ci
= 0; ci
< vb
->AttribPtr
[tab
[i
]]->size
; ci
++) {
302 rcommon_emit_vector(ctx
, &rmesa
->radeon
.tcl
.aos
[i
],
303 vb
->AttribPtr
[tab
[i
]]->data
,
304 vb
->AttribPtr
[tab
[i
]]->size
,
305 vb
->AttribPtr
[tab
[i
]]->stride
, count
);
308 /* Setup INPUT_ROUTE. */
309 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
310 R300_STATECHANGE(rmesa
, vir
[0]);
311 rmesa
->hw
.vir
[0].cmd
[0] &= 0xC000FFFF;
312 rmesa
->hw
.vir
[1].cmd
[0] &= 0xC000FFFF;
313 rmesa
->hw
.vir
[0].cmd
[0] |=
314 (r300VAPInputRoute0(&rmesa
->hw
.vir
[0].cmd
[R300_VIR_CNTL_0
],
315 vb
->AttribPtr
, inputs
, tab
, nr
) & 0x3FFF) << 16;
316 R300_STATECHANGE(rmesa
, vir
[1]);
317 rmesa
->hw
.vir
[1].cmd
[0] |=
318 (r300VAPInputRoute1(&rmesa
->hw
.vir
[1].cmd
[R300_VIR_CNTL_0
], swizzle
,
321 R300_STATECHANGE(rmesa
, vir
[0]);
322 ((drm_r300_cmd_header_t
*) rmesa
->hw
.vir
[0].cmd
)->packet0
.count
=
323 r300VAPInputRoute0(&rmesa
->hw
.vir
[0].cmd
[R300_VIR_CNTL_0
],
324 vb
->AttribPtr
, inputs
, tab
, nr
);
325 R300_STATECHANGE(rmesa
, vir
[1]);
326 ((drm_r300_cmd_header_t
*) rmesa
->hw
.vir
[1].cmd
)->packet0
.count
=
327 r300VAPInputRoute1(&rmesa
->hw
.vir
[1].cmd
[R300_VIR_CNTL_0
], swizzle
,
331 /* Setup INPUT_CNTL. */
332 R300_STATECHANGE(rmesa
, vic
);
333 rmesa
->hw
.vic
.cmd
[R300_VIC_CNTL_0
] = r300VAPInputCntl0(ctx
, InputsRead
);
334 rmesa
->hw
.vic
.cmd
[R300_VIC_CNTL_1
] = r300VAPInputCntl1(ctx
, InputsRead
);
336 /* Setup OUTPUT_VTX_FMT. */
337 R300_STATECHANGE(rmesa
, vof
);
338 rmesa
->hw
.vof
.cmd
[R300_VOF_CNTL_0
] =
339 r300VAPOutputCntl0(ctx
, OutputsWritten
);
340 rmesa
->hw
.vof
.cmd
[R300_VOF_CNTL_1
] =
341 r300VAPOutputCntl1(ctx
, OutputsWritten
);
343 rmesa
->radeon
.tcl
.aos_count
= nr
;
345 return R300_FALLBACK_NONE
;
348 void r300EmitCacheFlush(r300ContextPtr rmesa
)
350 BATCH_LOCALS(&rmesa
->radeon
);
352 BEGIN_BATCH_NO_AUTOSTATE(4);
353 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT
,
354 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
355 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
356 OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT
,
357 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
358 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);