2 * Copyright (C) 2005 Vladimir Dergachev.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Vladimir Dergachev <volodya@mindspring.com>
31 * Nicolai Haehnle <prefect_@gmx.net>
32 * Aapo Tahkola <aet@rasterburn.org>
33 * Ben Skeggs <darktama@iinet.net.au>
34 * Jerome Glisse <j.glisse@gmail.com>
37 /* This files defines functions for accessing R300 hardware.
39 #ifndef __R300_EMIT_H__
40 #define __R300_EMIT_H__
42 #include "main/glheader.h"
43 #include "r300_context.h"
44 #include "r300_cmdbuf.h"
45 #include "radeon_reg.h"
47 static INLINE
uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
50 if (!rscrn
->kernel_mm
) {
51 drm_r300_cmd_header_t cmd
;
53 cmd
.packet0
.cmd_type
= R300_CMD_PACKET0
;
54 cmd
.packet0
.count
= count
;
55 cmd
.packet0
.reghi
= ((unsigned int)reg
& 0xFF00) >> 8;
56 cmd
.packet0
.reglo
= ((unsigned int)reg
& 0x00FF);
61 return CP_PACKET0(reg
, count
- 1);
66 static INLINE
uint32_t cmdvpu(struct radeon_screen
*rscrn
, int addr
, int count
)
68 drm_r300_cmd_header_t cmd
;
70 cmd
.vpu
.cmd_type
= R300_CMD_VPU
;
71 cmd
.vpu
.count
= count
;
72 cmd
.vpu
.adrhi
= ((unsigned int)addr
& 0xFF00) >> 8;
73 cmd
.vpu
.adrlo
= ((unsigned int)addr
& 0x00FF);
78 static INLINE
uint32_t cmdr500fp(struct radeon_screen
*rscrn
,
79 int addr
, int count
, int type
, int clamp
)
81 drm_r300_cmd_header_t cmd
;
83 cmd
.r500fp
.cmd_type
= R300_CMD_R500FP
;
84 cmd
.r500fp
.count
= count
;
85 cmd
.r500fp
.adrhi_flags
= ((unsigned int)addr
& 0x100) >> 8;
86 cmd
.r500fp
.adrhi_flags
|= type
? R500FP_CONSTANT_TYPE
: 0;
87 cmd
.r500fp
.adrhi_flags
|= clamp
? R500FP_CONSTANT_CLAMP
: 0;
88 cmd
.r500fp
.adrlo
= ((unsigned int)addr
& 0x00FF);
93 static INLINE
uint32_t cmdpacket3(struct radeon_screen
*rscrn
, int packet
)
95 drm_r300_cmd_header_t cmd
;
97 cmd
.packet3
.cmd_type
= R300_CMD_PACKET3
;
98 cmd
.packet3
.packet
= packet
;
103 static INLINE
uint32_t cmdcpdelay(struct radeon_screen
*rscrn
,
104 unsigned short count
)
106 drm_r300_cmd_header_t cmd
;
108 cmd
.delay
.cmd_type
= R300_CMD_CP_DELAY
;
109 cmd
.delay
.count
= count
;
114 static INLINE
uint32_t cmdwait(struct radeon_screen
*rscrn
,
117 drm_r300_cmd_header_t cmd
;
119 cmd
.wait
.cmd_type
= R300_CMD_WAIT
;
120 cmd
.wait
.flags
= flags
;
125 static INLINE
uint32_t cmdpacify(struct radeon_screen
*rscrn
)
127 drm_r300_cmd_header_t cmd
;
129 cmd
.header
.cmd_type
= R300_CMD_END3D
;
135 * Write the header of a packet3 to the command buffer.
136 * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
138 #define OUT_BATCH_PACKET3(packet, num_extra) do {\
139 if (!b_l_rmesa->radeonScreen->kernel_mm) { \
140 OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\
141 R300_CMD_PACKET3_RAW)); \
142 } else b_l_rmesa->cmdbuf.cs->section_cdw++;\
143 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
147 * Must be sent to switch to 2d commands
149 void static INLINE
end_3d(radeonContextPtr radeon
)
151 BATCH_LOCALS(radeon
);
153 if (!radeon
->radeonScreen
->kernel_mm
) {
154 BEGIN_BATCH_NO_AUTOSTATE(1);
155 OUT_BATCH(cmdpacify(radeon
->radeonScreen
));
160 void static INLINE
cp_delay(r300ContextPtr rmesa
, unsigned short count
)
162 BATCH_LOCALS(&rmesa
->radeon
);
164 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
165 BEGIN_BATCH_NO_AUTOSTATE(1);
166 OUT_BATCH(cmdcpdelay(rmesa
->radeon
.radeonScreen
, count
));
171 void static INLINE
cp_wait(radeonContextPtr radeon
, unsigned char flags
)
173 BATCH_LOCALS(radeon
);
176 if (!radeon
->radeonScreen
->kernel_mm
) {
177 BEGIN_BATCH_NO_AUTOSTATE(1);
178 OUT_BATCH(cmdwait(radeon
->radeonScreen
, flags
));
183 wait_until
= (1 << 14);
186 wait_until
= (1 << 15);
188 case R300_NEW_WAIT_2D_3D
:
189 wait_until
= (1 << 14) | (1 << 15);
191 case R300_NEW_WAIT_2D_2D_CLEAN
:
192 wait_until
= (1 << 14) | (1 << 16) | (1 << 18);
194 case R300_NEW_WAIT_3D_3D_CLEAN
:
195 wait_until
= (1 << 15) | (1 << 17) | (1 << 18);
197 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN
:
198 wait_until
= (1 << 14) | (1 << 16) | (1 << 18);
199 wait_until
|= (1 << 15) | (1 << 17) | (1 << 18);
204 BEGIN_BATCH_NO_AUTOSTATE(2);
205 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
206 OUT_BATCH(wait_until
);
211 extern int r300EmitArrays(GLcontext
* ctx
);
213 extern void r300ReleaseArrays(GLcontext
* ctx
);
214 extern int r300PrimitiveType(r300ContextPtr rmesa
, int prim
);
215 extern int r300NumVerts(r300ContextPtr rmesa
, int num_verts
, int prim
);
217 extern void r300EmitCacheFlush(r300ContextPtr rmesa
);
219 extern GLuint
r300VAPInputRoute0(uint32_t * dst
, GLvector4f
** attribptr
,
220 int *inputs
, GLint
* tab
, GLuint nr
);
221 extern GLuint
r300VAPInputRoute1(uint32_t * dst
, int swizzle
[][4], GLuint nr
);
222 extern GLuint
r300VAPInputCntl0(GLcontext
* ctx
, GLuint InputsRead
);
223 extern GLuint
r300VAPInputCntl1(GLcontext
* ctx
, GLuint InputsRead
);
224 extern GLuint
r300VAPOutputCntl0(GLcontext
* ctx
, GLuint OutputsWritten
);
225 extern GLuint
r300VAPOutputCntl1(GLcontext
* ctx
, GLuint OutputsWritten
);