2 * Copyright (C) 2005 Vladimir Dergachev.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Vladimir Dergachev <volodya@mindspring.com>
31 * Nicolai Haehnle <prefect_@gmx.net>
32 * Aapo Tahkola <aet@rasterburn.org>
33 * Ben Skeggs <darktama@iinet.net.au>
34 * Jerome Glisse <j.glisse@gmail.com>
37 /* This files defines functions for accessing R300 hardware.
39 #ifndef __R300_EMIT_H__
40 #define __R300_EMIT_H__
42 #include "main/glheader.h"
43 #include "r300_context.h"
44 #include "r300_cmdbuf.h"
45 #include "radeon_reg.h"
47 static INLINE
uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
50 if (!rscrn
->kernel_mm
) {
51 drm_r300_cmd_header_t cmd
;
54 cmd
.packet0
.cmd_type
= R300_CMD_PACKET0
;
55 cmd
.packet0
.count
= count
;
56 cmd
.packet0
.reghi
= ((unsigned int)reg
& 0xFF00) >> 8;
57 cmd
.packet0
.reglo
= ((unsigned int)reg
& 0x00FF);
62 return CP_PACKET0(reg
, count
- 1);
67 static INLINE
uint32_t cmdvpu(struct radeon_screen
*rscrn
, int addr
, int count
)
69 drm_r300_cmd_header_t cmd
;
72 cmd
.vpu
.cmd_type
= R300_CMD_VPU
;
73 cmd
.vpu
.count
= count
;
74 cmd
.vpu
.adrhi
= ((unsigned int)addr
& 0xFF00) >> 8;
75 cmd
.vpu
.adrlo
= ((unsigned int)addr
& 0x00FF);
80 static INLINE
uint32_t cmdr500fp(struct radeon_screen
*rscrn
,
81 int addr
, int count
, int type
, int clamp
)
83 drm_r300_cmd_header_t cmd
;
86 cmd
.r500fp
.cmd_type
= R300_CMD_R500FP
;
87 cmd
.r500fp
.count
= count
;
88 cmd
.r500fp
.adrhi_flags
= ((unsigned int)addr
& 0x100) >> 8;
89 cmd
.r500fp
.adrhi_flags
|= type
? R500FP_CONSTANT_TYPE
: 0;
90 cmd
.r500fp
.adrhi_flags
|= clamp
? R500FP_CONSTANT_CLAMP
: 0;
91 cmd
.r500fp
.adrlo
= ((unsigned int)addr
& 0x00FF);
96 static INLINE
uint32_t cmdpacket3(struct radeon_screen
*rscrn
, int packet
)
98 drm_r300_cmd_header_t cmd
;
101 cmd
.packet3
.cmd_type
= R300_CMD_PACKET3
;
102 cmd
.packet3
.packet
= packet
;
107 static INLINE
uint32_t cmdcpdelay(struct radeon_screen
*rscrn
,
108 unsigned short count
)
110 drm_r300_cmd_header_t cmd
;
114 cmd
.delay
.cmd_type
= R300_CMD_CP_DELAY
;
115 cmd
.delay
.count
= count
;
120 static INLINE
uint32_t cmdwait(struct radeon_screen
*rscrn
,
123 drm_r300_cmd_header_t cmd
;
126 cmd
.wait
.cmd_type
= R300_CMD_WAIT
;
127 cmd
.wait
.flags
= flags
;
132 static INLINE
uint32_t cmdpacify(struct radeon_screen
*rscrn
)
134 drm_r300_cmd_header_t cmd
;
137 cmd
.header
.cmd_type
= R300_CMD_END3D
;
143 * Write the header of a packet3 to the command buffer.
144 * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
146 #define OUT_BATCH_PACKET3(packet, num_extra) do {\
147 if (!b_l_rmesa->radeonScreen->kernel_mm) { \
148 OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\
149 R300_CMD_PACKET3_RAW)); \
150 } else b_l_rmesa->cmdbuf.cs->section_cdw++;\
151 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
155 * Must be sent to switch to 2d commands
157 void static INLINE
end_3d(radeonContextPtr radeon
)
159 BATCH_LOCALS(radeon
);
161 if (!radeon
->radeonScreen
->kernel_mm
) {
162 BEGIN_BATCH_NO_AUTOSTATE(1);
163 OUT_BATCH(cmdpacify(radeon
->radeonScreen
));
168 void static INLINE
cp_delay(r300ContextPtr rmesa
, unsigned short count
)
170 BATCH_LOCALS(&rmesa
->radeon
);
172 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
173 BEGIN_BATCH_NO_AUTOSTATE(1);
174 OUT_BATCH(cmdcpdelay(rmesa
->radeon
.radeonScreen
, count
));
179 void static INLINE
cp_wait(radeonContextPtr radeon
, unsigned char flags
)
181 BATCH_LOCALS(radeon
);
184 if (!radeon
->radeonScreen
->kernel_mm
) {
185 BEGIN_BATCH_NO_AUTOSTATE(1);
186 OUT_BATCH(cmdwait(radeon
->radeonScreen
, flags
));
191 wait_until
= (1 << 14);
194 wait_until
= (1 << 15);
196 case R300_NEW_WAIT_2D_3D
:
197 wait_until
= (1 << 14) | (1 << 15);
199 case R300_NEW_WAIT_2D_2D_CLEAN
:
200 wait_until
= (1 << 14) | (1 << 16) | (1 << 18);
202 case R300_NEW_WAIT_3D_3D_CLEAN
:
203 wait_until
= (1 << 15) | (1 << 17) | (1 << 18);
205 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN
:
206 wait_until
= (1 << 14) | (1 << 16) | (1 << 18);
207 wait_until
|= (1 << 15) | (1 << 17) | (1 << 18);
212 BEGIN_BATCH_NO_AUTOSTATE(2);
213 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
214 OUT_BATCH(wait_until
);
219 extern int r300EmitArrays(GLcontext
* ctx
);
221 extern int r300PrimitiveType(r300ContextPtr rmesa
, int prim
);
222 extern int r300NumVerts(r300ContextPtr rmesa
, int num_verts
, int prim
);
224 extern void r300EmitCacheFlush(r300ContextPtr rmesa
);
226 extern GLuint
r300VAPInputRoute0(uint32_t * dst
, GLvector4f
** attribptr
,
227 int *inputs
, GLint
* tab
, GLuint nr
);
228 extern GLuint
r300VAPInputRoute1(uint32_t * dst
, int swizzle
[][4], GLuint nr
);
229 extern GLuint
r300VAPInputCntl0(GLcontext
* ctx
, GLuint InputsRead
);
230 extern GLuint
r300VAPInputCntl1(GLcontext
* ctx
, GLuint InputsRead
);
231 extern GLuint
r300VAPOutputCntl0(GLcontext
* ctx
, GLuint OutputsWritten
);
232 extern GLuint
r300VAPOutputCntl1(GLcontext
* ctx
, GLuint OutputsWritten
);