src/mesa/drivers/dri/r300/r300_emit.h

   1 /*
   2  * Copyright (C) 2005 Vladimir Dergachev.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Vladimir Dergachev <volodya@mindspring.com>
  31  *   Nicolai Haehnle <prefect_@gmx.net>
  32  *   Aapo Tahkola <aet@rasterburn.org>
  33  *   Ben Skeggs <darktama@iinet.net.au>
  34  *   Jerome Glisse <j.glisse@gmail.com>
  35  */
  36
  37 /* This files defines functions for accessing R300 hardware.
  38  */
  39 #ifndef __R300_EMIT_H__
  40 #define __R300_EMIT_H__
  41
  42 #include "main/glheader.h"
  43 #include "r300_context.h"
  44 #include "r300_cmdbuf.h"
  45 #include "radeon_reg.h"
  46
  47 /* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up
  48  * with DRM */
  49 #define CP_PACKET2  (2 << 30)
  50 #define CP_PACKET0(reg, n)      (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
  51 #define CP_PACKET3( pkt, n )                                            \
  52         (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
  53
  54 static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
  55                                   int reg, int count)
  56 {
  57     if (!rscrn->kernel_mm) {
  58             drm_r300_cmd_header_t cmd;
  59
  60         cmd.packet0.cmd_type = R300_CMD_PACKET0;
  61             cmd.packet0.count = count;
  62         cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
  63             cmd.packet0.reglo = ((unsigned int)reg & 0x00FF);
  64
  65         return cmd.u;
  66     }
  67     if (count) {
  68         return CP_PACKET0(reg, count - 1);
  69     }
  70     return CP_PACKET2;
  71 }
  72
  73 static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count)
  74 {
  75         drm_r300_cmd_header_t cmd;
  76
  77         cmd.vpu.cmd_type = R300_CMD_VPU;
  78         cmd.vpu.count = count;
  79         cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
  80         cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF);
  81
  82         return cmd.u;
  83 }
  84
  85 static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn,
  86                                  int addr, int count, int type, int clamp)
  87 {
  88         drm_r300_cmd_header_t cmd;
  89
  90         cmd.r500fp.cmd_type = R300_CMD_R500FP;
  91         cmd.r500fp.count = count;
  92         cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
  93         cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0;
  94         cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0;
  95         cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF);
  96
  97         return cmd.u;
  98 }
  99
 100 static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet)
 101 {
 102         drm_r300_cmd_header_t cmd;
 103
 104         cmd.packet3.cmd_type = R300_CMD_PACKET3;
 105         cmd.packet3.packet = packet;
 106
 107         return cmd.u;
 108 }
 109
 110 static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
 111                                   unsigned short count)
 112 {
 113         drm_r300_cmd_header_t cmd;
 114
 115         cmd.delay.cmd_type = R300_CMD_CP_DELAY;
 116         cmd.delay.count = count;
 117
 118         return cmd.u;
 119 }
 120
 121 static INLINE uint32_t cmdwait(struct radeon_screen *rscrn,
 122                                unsigned char flags)
 123 {
 124         drm_r300_cmd_header_t cmd;
 125
 126         cmd.wait.cmd_type = R300_CMD_WAIT;
 127         cmd.wait.flags = flags;
 128
 129         return cmd.u;
 130 }
 131
 132 static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
 133 {
 134         drm_r300_cmd_header_t cmd;
 135
 136         cmd.header.cmd_type = R300_CMD_END3D;
 137
 138         return cmd.u;
 139 }
 140
 141
 142 /** Single register write to command buffer; requires 2 dwords. */
 143 #define OUT_BATCH_REGVAL(reg, val) \
 144         OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \
 145         OUT_BATCH((val))
 146
 147 /** Continuous register range write to command buffer; requires 1 dword,
 148  * expects count dwords afterwards for register contents. */
 149 #define OUT_BATCH_REGSEQ(reg, count) \
 150         OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count)));
 151
 152 /** Write a 32 bit float to the ring; requires 1 dword. */
 153 #define OUT_BATCH_FLOAT32(f) \
 154         OUT_BATCH(r300PackFloat32((f)));
 155
 156 /**
 157  * Write the header of a packet3 to the command buffer.
 158  * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
 159  */
 160 #define OUT_BATCH_PACKET3(packet, num_extra) do {\
 161     if (!b_l_r300->radeon.radeonScreen->kernel_mm) { \
 162         OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\
 163                   R300_CMD_PACKET3_RAW)); \
 164     }\
 165         OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
 166         } while(0)
 167
 168 /**
 169  * Must be sent to switch to 2d commands
 170  */
 171 void static INLINE end_3d(r300ContextPtr rmesa)
 172 {
 173         BATCH_LOCALS(rmesa);
 174
 175     if (!rmesa->radeon.radeonScreen->kernel_mm) {
 176         BEGIN_BATCH(1);
 177             OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen));
 178         END_BATCH();
 179     }
 180 }
 181
 182 void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
 183 {
 184         BATCH_LOCALS(rmesa);
 185
 186     if (!rmesa->radeon.radeonScreen->kernel_mm) {
 187         BEGIN_BATCH(1);
 188             OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
 189         END_BATCH();
 190     }
 191 }
 192
 193 void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags)
 194 {
 195         BATCH_LOCALS(rmesa);
 196     uint32_t wait_until;
 197
 198     if (!rmesa->radeon.radeonScreen->kernel_mm) {
 199         BEGIN_BATCH_NO_AUTOSTATE(1);
 200         OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags));
 201             END_BATCH();
 202     } else {
 203         switch(flags) {
 204         case R300_WAIT_2D:
 205             wait_until = (1 << 14);
 206             break;
 207         case R300_WAIT_3D:
 208             wait_until = (1 << 15);
 209             break;
 210         case R300_NEW_WAIT_2D_3D:
 211             wait_until = (1 << 14) | (1 << 15);
 212             break;
 213         case R300_NEW_WAIT_2D_2D_CLEAN:
 214             wait_until = (1 << 14) | (1 << 16) | (1 << 18);
 215             break;
 216         case R300_NEW_WAIT_3D_3D_CLEAN:
 217             wait_until = (1 << 15) | (1 << 17) | (1 << 18);
 218             break;
 219         case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
 220             wait_until  = (1 << 14) | (1 << 16) | (1 << 18);
 221             wait_until |= (1 << 15) | (1 << 17) | (1 << 18);
 222             break;
 223         default:
 224             return;
 225         }
 226         BEGIN_BATCH_NO_AUTOSTATE(2);
 227         OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 228         OUT_BATCH(wait_until);
 229             END_BATCH();
 230     }
 231 }
 232
 233 extern int r300EmitArrays(GLcontext * ctx);
 234
 235 extern void r300ReleaseArrays(GLcontext * ctx);
 236 extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
 237 extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
 238
 239 extern void r300EmitCacheFlush(r300ContextPtr rmesa);
 240
 241 extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
 242                                  int *inputs, GLint * tab, GLuint nr);
 243 extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
 244 extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
 245 extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
 246 extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
 247 extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
 248
 249 #endif