src/mesa/drivers/dri/r300/r300_fragprog.c

   1 /*
   2  * Copyright (C) 2005 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * \file
  30  *
  31  * Fragment program compiler. Perform transformations on the intermediate
  32  * representation until the program is in a form where we can translate
  33  * it more or less directly into machine-readable form.
  34  *
  35  * \author Ben Skeggs <darktama@iinet.net.au>
  36  * \author Jerome Glisse <j.glisse@gmail.com>
  37  */
  38
  39 #include "glheader.h"
  40 #include "macros.h"
  41 #include "enums.h"
  42 #include "shader/prog_instruction.h"
  43 #include "shader/prog_parameter.h"
  44 #include "shader/prog_print.h"
  45
  46 #include "r300_context.h"
  47 #include "r300_fragprog.h"
  48 #include "r300_fragprog_swizzle.h"
  49 #include "r300_state.h"
  50
  51 #include "radeon_nqssadce.h"
  52 #include "radeon_program_alu.h"
  53
  54
  55 static void reset_srcreg(struct prog_src_register* reg)
  56 {
  57         _mesa_bzero(reg, sizeof(*reg));
  58         reg->Swizzle = SWIZZLE_NOOP;
  59 }
  60
  61 static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
  62 {
  63         gl_state_index fail_value_tokens[STATE_LENGTH] = {
  64                 STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
  65         };
  66         struct prog_src_register reg = { 0, };
  67
  68         fail_value_tokens[2] = tmu;
  69         reg.File = PROGRAM_STATE_VAR;
  70         reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
  71         reg.Swizzle = SWIZZLE_WWWW;
  72         return reg;
  73 }
  74
  75 /**
  76  * Transform TEX, TXP, TXB, and KIL instructions in the following way:
  77  *  - premultiply texture coordinates for RECT
  78  *  - extract operand swizzles
  79  *  - introduce a temporary register when write masks are needed
  80  *
  81  * \todo If/when r5xx uses the radeon_program architecture, this can probably
  82  * be reused.
  83  */
  84 static GLboolean transform_TEX(
  85         struct radeon_transform_context *t,
  86         struct prog_instruction* orig_inst, void* data)
  87 {
  88         struct r300_fragment_program_compiler *compiler =
  89                 (struct r300_fragment_program_compiler*)data;
  90         struct prog_instruction inst = *orig_inst;
  91         struct prog_instruction* tgt;
  92         GLboolean destredirect = GL_FALSE;
  93
  94         if (inst.Opcode != OPCODE_TEX &&
  95             inst.Opcode != OPCODE_TXB &&
  96             inst.Opcode != OPCODE_TXP &&
  97             inst.Opcode != OPCODE_KIL)
  98                 return GL_FALSE;
  99
 100         if (inst.Opcode != OPCODE_KIL &&
 101             t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
 102                 GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
 103
 104                 if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) {
 105                         tgt = radeonAppendInstructions(t->Program, 1);
 106
 107                         tgt->Opcode = OPCODE_MOV;
 108                         tgt->DstReg = inst.DstReg;
 109                         if (comparefunc == GL_ALWAYS) {
 110                                 tgt->SrcReg[0].File = PROGRAM_BUILTIN;
 111                                 tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
 112                         } else {
 113                                 tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
 114                         }
 115                         return GL_TRUE;
 116                 }
 117
 118                 inst.DstReg.File = PROGRAM_TEMPORARY;
 119                 inst.DstReg.Index = radeonFindFreeTemporary(t);
 120                 inst.DstReg.WriteMask = WRITEMASK_XYZW;
 121         }
 122
 123
 124         /* Hardware uses [0..1]x[0..1] range for rectangle textures
 125          * instead of [0..Width]x[0..Height].
 126          * Add a scaling instruction.
 127          */
 128         if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) {
 129                 gl_state_index tokens[STATE_LENGTH] = {
 130                         STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0,
 131                         0
 132                 };
 133
 134                 int tempreg = radeonFindFreeTemporary(t);
 135                 int factor_index;
 136
 137                 tokens[2] = inst.TexSrcUnit;
 138                 factor_index = _mesa_add_state_reference(t->Program->Parameters, tokens);
 139
 140                 tgt = radeonAppendInstructions(t->Program, 1);
 141
 142                 tgt->Opcode = OPCODE_MUL;
 143                 tgt->DstReg.File = PROGRAM_TEMPORARY;
 144                 tgt->DstReg.Index = tempreg;
 145                 tgt->SrcReg[0] = inst.SrcReg[0];
 146                 tgt->SrcReg[1].File = PROGRAM_STATE_VAR;
 147                 tgt->SrcReg[1].Index = factor_index;
 148
 149                 reset_srcreg(&inst.SrcReg[0]);
 150                 inst.SrcReg[0].File = PROGRAM_TEMPORARY;
 151                 inst.SrcReg[0].Index = tempreg;
 152         }
 153
 154         if (inst.Opcode != OPCODE_KIL) {
 155                 if (inst.DstReg.File != PROGRAM_TEMPORARY ||
 156                     inst.DstReg.WriteMask != WRITEMASK_XYZW) {
 157                         int tempreg = radeonFindFreeTemporary(t);
 158
 159                         inst.DstReg.File = PROGRAM_TEMPORARY;
 160                         inst.DstReg.Index = tempreg;
 161                         inst.DstReg.WriteMask = WRITEMASK_XYZW;
 162                         destredirect = GL_TRUE;
 163                 }
 164         }
 165
 166         tgt = radeonAppendInstructions(t->Program, 1);
 167         _mesa_copy_instructions(tgt, &inst, 1);
 168
 169         if (inst.Opcode != OPCODE_KIL &&
 170             t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
 171                 GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
 172                 GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode;
 173                 int rcptemp = radeonFindFreeTemporary(t);
 174                 int pass, fail;
 175
 176                 tgt = radeonAppendInstructions(t->Program, 3);
 177
 178                 tgt[0].Opcode = OPCODE_RCP;
 179                 tgt[0].DstReg.File = PROGRAM_TEMPORARY;
 180                 tgt[0].DstReg.Index = rcptemp;
 181                 tgt[0].DstReg.WriteMask = WRITEMASK_W;
 182                 tgt[0].SrcReg[0] = inst.SrcReg[0];
 183                 tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW;
 184
 185                 tgt[1].Opcode = OPCODE_MAD;
 186                 tgt[1].DstReg = inst.DstReg;
 187                 tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask;
 188                 tgt[1].SrcReg[0] = inst.SrcReg[0];
 189                 tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ;
 190                 tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY;
 191                 tgt[1].SrcReg[1].Index = rcptemp;
 192                 tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW;
 193                 tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY;
 194                 tgt[1].SrcReg[2].Index = inst.DstReg.Index;
 195                 if (depthmode == 0) /* GL_LUMINANCE */
 196                         tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z);
 197                 else if (depthmode == 2) /* GL_ALPHA */
 198                         tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW;
 199
 200                 /* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
 201                  *   r  < tex  <=>      -tex+r < 0
 202                  *   r >= tex  <=> not (-tex+r < 0 */
 203                 if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL)
 204                         tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW;
 205                 else
 206                         tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW;
 207
 208                 tgt[2].Opcode = OPCODE_CMP;
 209                 tgt[2].DstReg = orig_inst->DstReg;
 210                 tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
 211                 tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
 212
 213                 if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
 214                         pass = 1;
 215                         fail = 2;
 216                 } else {
 217                         pass = 2;
 218                         fail = 1;
 219                 }
 220
 221                 tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
 222                 tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
 223                 tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
 224         } else if (destredirect) {
 225                 tgt = radeonAppendInstructions(t->Program, 1);
 226
 227                 tgt->Opcode = OPCODE_MOV;
 228                 tgt->DstReg = orig_inst->DstReg;
 229                 tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
 230                 tgt->SrcReg[0].Index = inst.DstReg.Index;
 231         }
 232
 233         return GL_TRUE;
 234 }
 235
 236
 237 static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp)
 238 {
 239         struct gl_fragment_program *mp = &fp->mesa_program;
 240
 241         /* Ask Mesa nicely to fill in ParameterValues for us */
 242         if (mp->Base.Parameters)
 243                 _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters);
 244 }
 245
 246
 247 /**
 248  * Transform the program to support fragment.position.
 249  *
 250  * Introduce a small fragment at the start of the program that will be
 251  * the only code that directly reads the FRAG_ATTRIB_WPOS input.
 252  * All other code pieces that reference that input will be rewritten
 253  * to read from a newly allocated temporary.
 254  *
 255  * \todo if/when r5xx supports the radeon_program architecture, this is a
 256  * likely candidate for code sharing.
 257  */
 258 static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler)
 259 {
 260         GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead;
 261
 262         if (!(InputsRead & FRAG_BIT_WPOS))
 263                 return;
 264
 265         static gl_state_index tokens[STATE_LENGTH] = {
 266                 STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0
 267         };
 268         struct prog_instruction *fpi;
 269         GLuint window_index;
 270         int i = 0;
 271         GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY);
 272
 273         _mesa_insert_instructions(compiler->program, 0, 3);
 274         fpi = compiler->program->Instructions;
 275
 276         /* perspective divide */
 277         fpi[i].Opcode = OPCODE_RCP;
 278
 279         fpi[i].DstReg.File = PROGRAM_TEMPORARY;
 280         fpi[i].DstReg.Index = tempregi;
 281         fpi[i].DstReg.WriteMask = WRITEMASK_W;
 282         fpi[i].DstReg.CondMask = COND_TR;
 283
 284         fpi[i].SrcReg[0].File = PROGRAM_INPUT;
 285         fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
 286         fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW;
 287         i++;
 288
 289         fpi[i].Opcode = OPCODE_MUL;
 290
 291         fpi[i].DstReg.File = PROGRAM_TEMPORARY;
 292         fpi[i].DstReg.Index = tempregi;
 293         fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
 294         fpi[i].DstReg.CondMask = COND_TR;
 295
 296         fpi[i].SrcReg[0].File = PROGRAM_INPUT;
 297         fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
 298         fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW;
 299
 300         fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY;
 301         fpi[i].SrcReg[1].Index = tempregi;
 302         fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW;
 303         i++;
 304
 305         /* viewport transformation */
 306         window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens);
 307
 308         fpi[i].Opcode = OPCODE_MAD;
 309
 310         fpi[i].DstReg.File = PROGRAM_TEMPORARY;
 311         fpi[i].DstReg.Index = tempregi;
 312         fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
 313         fpi[i].DstReg.CondMask = COND_TR;
 314
 315         fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY;
 316         fpi[i].SrcReg[0].Index = tempregi;
 317         fpi[i].SrcReg[0].Swizzle =
 318             MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
 319
 320         fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR;
 321         fpi[i].SrcReg[1].Index = window_index;
 322         fpi[i].SrcReg[1].Swizzle =
 323             MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
 324
 325         fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR;
 326         fpi[i].SrcReg[2].Index = window_index;
 327         fpi[i].SrcReg[2].Swizzle =
 328             MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
 329         i++;
 330
 331         for (; i < compiler->program->NumInstructions; ++i) {
 332                 int reg;
 333                 for (reg = 0; reg < 3; reg++) {
 334                         if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT &&
 335                             fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) {
 336                                 fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY;
 337                                 fpi[i].SrcReg[reg].Index = tempregi;
 338                         }
 339                 }
 340         }
 341 }
 342
 343
 344 static void nqssadce_init(struct nqssadce_state* s)
 345 {
 346         s->Outputs[FRAG_RESULT_COLR].Sourced = WRITEMASK_XYZW;
 347         s->Outputs[FRAG_RESULT_DEPR].Sourced = WRITEMASK_W;
 348 }
 349
 350
 351 static GLuint build_dtm(GLuint depthmode)
 352 {
 353         switch(depthmode) {
 354         default:
 355         case GL_LUMINANCE: return 0;
 356         case GL_INTENSITY: return 1;
 357         case GL_ALPHA: return 2;
 358         }
 359 }
 360
 361 static GLuint build_func(GLuint comparefunc)
 362 {
 363         return comparefunc - GL_NEVER;
 364 }
 365
 366
 367 /**
 368  * Collect all external state that is relevant for compiling the given
 369  * fragment program.
 370  */
 371 static void build_state(
 372         r300ContextPtr r300,
 373         struct r300_fragment_program *fp,
 374         struct r300_fragment_program_external_state *state)
 375 {
 376         int unit;
 377
 378         _mesa_bzero(state, sizeof(*state));
 379
 380         for(unit = 0; unit < 16; ++unit) {
 381                 if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
 382                         struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
 383
 384                         state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
 385                         state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
 386                 }
 387         }
 388 }
 389
 390
 391 void r300TranslateFragmentShader(r300ContextPtr r300,
 392                                  struct r300_fragment_program *fp)
 393 {
 394         struct r300_fragment_program_external_state state;
 395
 396         build_state(r300, fp, &state);
 397         if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
 398                 /* TODO: cache compiled programs */
 399                 fp->translated = GL_FALSE;
 400                 _mesa_memcpy(&fp->state, &state, sizeof(state));
 401         }
 402
 403         if (!fp->translated) {
 404                 struct r300_fragment_program_compiler compiler;
 405
 406                 compiler.r300 = r300;
 407                 compiler.fp = fp;
 408                 compiler.code = &fp->code;
 409                 compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base);
 410
 411                 if (RADEON_DEBUG & DEBUG_PIXEL) {
 412                         _mesa_printf("Fragment Program: Initial program:\n");
 413                         _mesa_print_program(compiler.program);
 414                 }
 415
 416                 insert_WPOS_trailer(&compiler);
 417
 418                 struct radeon_program_transformation transformations[] = {
 419                         { &transform_TEX, &compiler },
 420                         { &radeonTransformALU, 0 },
 421                         { &radeonTransformTrigSimple, 0 }
 422                 };
 423                 radeonLocalTransform(
 424                         r300->radeon.glCtx,
 425                         compiler.program,
 426                         3, transformations);
 427
 428                 if (RADEON_DEBUG & DEBUG_PIXEL) {
 429                         _mesa_printf("Fragment Program: After native rewrite:\n");
 430                         _mesa_print_program(compiler.program);
 431                 }
 432
 433                 struct radeon_nqssadce_descr nqssadce = {
 434                         .Init = &nqssadce_init,
 435                         .IsNativeSwizzle = &r300FPIsNativeSwizzle,
 436                         .BuildSwizzle = &r300FPBuildSwizzle,
 437                         .RewriteDepthOut = GL_TRUE
 438                 };
 439                 radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce);
 440
 441                 if (RADEON_DEBUG & DEBUG_PIXEL) {
 442                         _mesa_printf("Compiler: after NqSSA-DCE:\n");
 443                         _mesa_print_program(compiler.program);
 444                 }
 445
 446                 if (!r300FragmentProgramEmit(&compiler))
 447                         fp->error = GL_TRUE;
 448
 449                 /* Subtle: Rescue any parameters that have been added during transformations */
 450                 _mesa_free_parameter_list(fp->mesa_program.Base.Parameters);
 451                 fp->mesa_program.Base.Parameters = compiler.program->Parameters;
 452                 compiler.program->Parameters = 0;
 453
 454                 _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL);
 455
 456                 if (!fp->error)
 457                         fp->translated = GL_TRUE;
 458                 if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL))
 459                         r300FragmentProgramDump(fp, &fp->code);
 460                 r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM);
 461         }
 462
 463         update_params(r300, fp);
 464 }
 465
 466 /* just some random things... */
 467 void r300FragmentProgramDump(
 468         struct r300_fragment_program *fp,
 469         struct r300_fragment_program_code *code)
 470 {
 471         int n, i, j;
 472         static int pc = 0;
 473
 474         fprintf(stderr, "pc=%d*************************************\n", pc++);
 475
 476         fprintf(stderr, "Hardware program\n");
 477         fprintf(stderr, "----------------\n");
 478
 479         for (n = 0; n < (code->cur_node + 1); n++) {
 480                 fprintf(stderr, "NODE %d: alu_offset: %d, tex_offset: %d, "
 481                         "alu_end: %d, tex_end: %d, flags: %08x\n", n,
 482                         code->node[n].alu_offset,
 483                         code->node[n].tex_offset,
 484                         code->node[n].alu_end, code->node[n].tex_end,
 485                         code->node[n].flags);
 486
 487                 if (n > 0 || code->first_node_has_tex) {
 488                         fprintf(stderr, "  TEX:\n");
 489                         for (i = code->node[n].tex_offset;
 490                              i <= code->node[n].tex_offset + code->node[n].tex_end;
 491                              ++i) {
 492                                 const char *instr;
 493
 494                                 switch ((code->tex.
 495                                          inst[i] >> R300_TEX_INST_SHIFT) &
 496                                         15) {
 497                                 case R300_TEX_OP_LD:
 498                                         instr = "TEX";
 499                                         break;
 500                                 case R300_TEX_OP_KIL:
 501                                         instr = "KIL";
 502                                         break;
 503                                 case R300_TEX_OP_TXP:
 504                                         instr = "TXP";
 505                                         break;
 506                                 case R300_TEX_OP_TXB:
 507                                         instr = "TXB";
 508                                         break;
 509                                 default:
 510                                         instr = "UNKNOWN";
 511                                 }
 512
 513                                 fprintf(stderr,
 514                                         "    %s t%i, %c%i, texture[%i]   (%08x)\n",
 515                                         instr,
 516                                         (code->tex.
 517                                          inst[i] >> R300_DST_ADDR_SHIFT) & 31,
 518                                         't',
 519                                         (code->tex.
 520                                          inst[i] >> R300_SRC_ADDR_SHIFT) & 31,
 521                                         (code->tex.
 522                                          inst[i] & R300_TEX_ID_MASK) >>
 523                                         R300_TEX_ID_SHIFT,
 524                                         code->tex.inst[i]);
 525                         }
 526                 }
 527
 528                 for (i = code->node[n].alu_offset;
 529                      i <= code->node[n].alu_offset + code->node[n].alu_end; ++i) {
 530                         char srcc[3][10], dstc[20];
 531                         char srca[3][10], dsta[20];
 532                         char argc[3][20];
 533                         char arga[3][20];
 534                         char flags[5], tmp[10];
 535
 536                         for (j = 0; j < 3; ++j) {
 537                                 int regc = code->alu.inst[i].inst1 >> (j * 6);
 538                                 int rega = code->alu.inst[i].inst3 >> (j * 6);
 539
 540                                 sprintf(srcc[j], "%c%i",
 541                                         (regc & 32) ? 'c' : 't', regc & 31);
 542                                 sprintf(srca[j], "%c%i",
 543                                         (rega & 32) ? 'c' : 't', rega & 31);
 544                         }
 545
 546                         dstc[0] = 0;
 547                         sprintf(flags, "%s%s%s",
 548                                 (code->alu.inst[i].
 549                                  inst1 & R300_ALU_DSTC_REG_X) ? "x" : "",
 550                                 (code->alu.inst[i].
 551                                  inst1 & R300_ALU_DSTC_REG_Y) ? "y" : "",
 552                                 (code->alu.inst[i].
 553                                  inst1 & R300_ALU_DSTC_REG_Z) ? "z" : "");
 554                         if (flags[0] != 0) {
 555                                 sprintf(dstc, "t%i.%s ",
 556                                         (code->alu.inst[i].
 557                                          inst1 >> R300_ALU_DSTC_SHIFT) & 31,
 558                                         flags);
 559                         }
 560                         sprintf(flags, "%s%s%s",
 561                                 (code->alu.inst[i].
 562                                  inst1 & R300_ALU_DSTC_OUTPUT_X) ? "x" : "",
 563                                 (code->alu.inst[i].
 564                                  inst1 & R300_ALU_DSTC_OUTPUT_Y) ? "y" : "",
 565                                 (code->alu.inst[i].
 566                                  inst1 & R300_ALU_DSTC_OUTPUT_Z) ? "z" : "");
 567                         if (flags[0] != 0) {
 568                                 sprintf(tmp, "o%i.%s",
 569                                         (code->alu.inst[i].
 570                                          inst1 >> R300_ALU_DSTC_SHIFT) & 31,
 571                                         flags);
 572                                 strcat(dstc, tmp);
 573                         }
 574
 575                         dsta[0] = 0;
 576                         if (code->alu.inst[i].inst3 & R300_ALU_DSTA_REG) {
 577                                 sprintf(dsta, "t%i.w ",
 578                                         (code->alu.inst[i].
 579                                          inst3 >> R300_ALU_DSTA_SHIFT) & 31);
 580                         }
 581                         if (code->alu.inst[i].inst3 & R300_ALU_DSTA_OUTPUT) {
 582                                 sprintf(tmp, "o%i.w ",
 583                                         (code->alu.inst[i].
 584                                          inst3 >> R300_ALU_DSTA_SHIFT) & 31);
 585                                 strcat(dsta, tmp);
 586                         }
 587                         if (code->alu.inst[i].inst3 & R300_ALU_DSTA_DEPTH) {
 588                                 strcat(dsta, "Z");
 589                         }
 590
 591                         fprintf(stderr,
 592                                 "%3i: xyz: %3s %3s %3s -> %-20s (%08x)\n"
 593                                 "       w: %3s %3s %3s -> %-20s (%08x)\n", i,
 594                                 srcc[0], srcc[1], srcc[2], dstc,
 595                                 code->alu.inst[i].inst1, srca[0], srca[1],
 596                                 srca[2], dsta, code->alu.inst[i].inst3);
 597
 598                         for (j = 0; j < 3; ++j) {
 599                                 int regc = code->alu.inst[i].inst0 >> (j * 7);
 600                                 int rega = code->alu.inst[i].inst2 >> (j * 7);
 601                                 int d;
 602                                 char buf[20];
 603
 604                                 d = regc & 31;
 605                                 if (d < 12) {
 606                                         switch (d % 4) {
 607                                         case R300_ALU_ARGC_SRC0C_XYZ:
 608                                                 sprintf(buf, "%s.xyz",
 609                                                         srcc[d / 4]);
 610                                                 break;
 611                                         case R300_ALU_ARGC_SRC0C_XXX:
 612                                                 sprintf(buf, "%s.xxx",
 613                                                         srcc[d / 4]);
 614                                                 break;
 615                                         case R300_ALU_ARGC_SRC0C_YYY:
 616                                                 sprintf(buf, "%s.yyy",
 617                                                         srcc[d / 4]);
 618                                                 break;
 619                                         case R300_ALU_ARGC_SRC0C_ZZZ:
 620                                                 sprintf(buf, "%s.zzz",
 621                                                         srcc[d / 4]);
 622                                                 break;
 623                                         }
 624                                 } else if (d < 15) {
 625                                         sprintf(buf, "%s.www", srca[d - 12]);
 626                                 } else if (d == 20) {
 627                                         sprintf(buf, "0.0");
 628                                 } else if (d == 21) {
 629                                         sprintf(buf, "1.0");
 630                                 } else if (d == 22) {
 631                                         sprintf(buf, "0.5");
 632                                 } else if (d >= 23 && d < 32) {
 633                                         d -= 23;
 634                                         switch (d / 3) {
 635                                         case 0:
 636                                                 sprintf(buf, "%s.yzx",
 637                                                         srcc[d % 3]);
 638                                                 break;
 639                                         case 1:
 640                                                 sprintf(buf, "%s.zxy",
 641                                                         srcc[d % 3]);
 642                                                 break;
 643                                         case 2:
 644                                                 sprintf(buf, "%s.Wzy",
 645                                                         srcc[d % 3]);
 646                                                 break;
 647                                         }
 648                                 } else {
 649                                         sprintf(buf, "%i", d);
 650                                 }
 651
 652                                 sprintf(argc[j], "%s%s%s%s",
 653                                         (regc & 32) ? "-" : "",
 654                                         (regc & 64) ? "|" : "",
 655                                         buf, (regc & 64) ? "|" : "");
 656
 657                                 d = rega & 31;
 658                                 if (d < 9) {
 659                                         sprintf(buf, "%s.%c", srcc[d / 3],
 660                                                 'x' + (char)(d % 3));
 661                                 } else if (d < 12) {
 662                                         sprintf(buf, "%s.w", srca[d - 9]);
 663                                 } else if (d == 16) {
 664                                         sprintf(buf, "0.0");
 665                                 } else if (d == 17) {
 666                                         sprintf(buf, "1.0");
 667                                 } else if (d == 18) {
 668                                         sprintf(buf, "0.5");
 669                                 } else {
 670                                         sprintf(buf, "%i", d);
 671                                 }
 672
 673                                 sprintf(arga[j], "%s%s%s%s",
 674                                         (rega & 32) ? "-" : "",
 675                                         (rega & 64) ? "|" : "",
 676                                         buf, (rega & 64) ? "|" : "");
 677                         }
 678
 679                         fprintf(stderr, "     xyz: %8s %8s %8s    op: %08x\n"
 680                                 "       w: %8s %8s %8s    op: %08x\n",
 681                                 argc[0], argc[1], argc[2],
 682                                 code->alu.inst[i].inst0, arga[0], arga[1],
 683                                 arga[2], code->alu.inst[i].inst2);
 684                 }
 685         }
 686 }