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[mesa.git] / src / mesa / drivers / dri / r300 / r300_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /*
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 */
32
33 /*TODO'S
34 *
35 * - COS/SIN/SCS/LIT instructions
36 * - Depth write, WPOS/FOGC inputs
37 * - FogOption
38 * - Negate on individual components (implement in swizzle code?)
39 * - Verify results of opcodes for accuracy, I've only checked them
40 * in specific cases.
41 * - and more...
42 */
43
44 #include "glheader.h"
45 #include "macros.h"
46 #include "enums.h"
47
48 #include "program.h"
49 #include "program_instruction.h"
50 #include "r300_context.h"
51 #include "r300_fragprog.h"
52 #include "r300_reg.h"
53
54 #define PFS_INVAL 0xFFFFFFFF
55 #define COMPILE_STATE struct r300_pfs_compile_state *cs = rp->cs
56
57 static void dump_program(struct r300_fragment_program *rp);
58 static void emit_arith(struct r300_fragment_program *rp, int op,
59 pfs_reg_t dest, int mask,
60 pfs_reg_t src0, pfs_reg_t src1, pfs_reg_t src2,
61 int flags);
62
63 /***************************************
64 * begin: useful data structions for fragment program generation
65 ***************************************/
66
67 /* description of r300 native hw instructions */
68 static const struct {
69 const char *name;
70 int argc;
71 int v_op;
72 int s_op;
73 } r300_fpop[] = {
74 { "MAD", 3, R300_FPI0_OUTC_MAD, R300_FPI2_OUTA_MAD },
75 { "DP3", 2, R300_FPI0_OUTC_DP3, R300_FPI2_OUTA_DP4 },
76 { "DP4", 2, R300_FPI0_OUTC_DP4, R300_FPI2_OUTA_DP4 },
77 { "MIN", 2, R300_FPI0_OUTC_MIN, R300_FPI2_OUTA_MIN },
78 { "MAX", 2, R300_FPI0_OUTC_MAX, R300_FPI2_OUTA_MAX },
79 { "CMP", 3, R300_FPI0_OUTC_CMP, R300_FPI2_OUTA_CMP },
80 { "FRC", 1, R300_FPI0_OUTC_FRC, R300_FPI2_OUTA_FRC },
81 { "EX2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_EX2 },
82 { "LG2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_LG2 },
83 { "RCP", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RCP },
84 { "RSQ", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RSQ },
85 { "REPL_ALPHA", 1, R300_FPI0_OUTC_REPL_ALPHA, PFS_INVAL }
86 };
87
88 #define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \
89 SWIZZLE_##y, \
90 SWIZZLE_##z, \
91 SWIZZLE_ZERO))
92
93 #define SLOT_VECTOR (1<<0)
94 #define SLOT_SCALAR (1<<3)
95 #define SLOT_BOTH (SLOT_VECTOR|SLOT_SCALAR)
96
97 /* vector swizzles r300 can support natively, with a couple of
98 * cases we handle specially
99 *
100 * pfs_reg_t.v_swz/pfs_reg_t.s_swz is an index into this table
101 **/
102 static const struct r300_pfs_swizzle {
103 GLuint hash; /* swizzle value this matches */
104 GLuint base; /* base value for hw swizzle */
105 GLuint stride; /* difference in base between arg0/1/2 */
106 GLuint flags;
107 } v_swiz[] = {
108 /* native swizzles */
109 { MAKE_SWZ3(X, Y, Z), R300_FPI0_ARGC_SRC0C_XYZ, 4, SLOT_VECTOR },
110 { MAKE_SWZ3(X, X, X), R300_FPI0_ARGC_SRC0C_XXX, 4, SLOT_VECTOR },
111 { MAKE_SWZ3(Y, Y, Y), R300_FPI0_ARGC_SRC0C_YYY, 4, SLOT_VECTOR },
112 { MAKE_SWZ3(Z, Z, Z), R300_FPI0_ARGC_SRC0C_ZZZ, 4, SLOT_VECTOR },
113 { MAKE_SWZ3(W, W, W), R300_FPI0_ARGC_SRC0A, 1, SLOT_SCALAR },
114 { MAKE_SWZ3(Y, Z, X), R300_FPI0_ARGC_SRC0C_YZX, 1, SLOT_VECTOR },
115 { MAKE_SWZ3(Z, X, Y), R300_FPI0_ARGC_SRC0C_ZXY, 1, SLOT_VECTOR },
116 { MAKE_SWZ3(W, Z, Y), R300_FPI0_ARGC_SRC0CA_WZY, 1, SLOT_BOTH },
117 { MAKE_SWZ3(ONE, ONE, ONE), R300_FPI0_ARGC_ONE, 0, 0},
118 { MAKE_SWZ3(ZERO, ZERO, ZERO), R300_FPI0_ARGC_ZERO, 0, 0},
119 { PFS_INVAL, R300_FPI0_ARGC_HALF, 0, 0},
120 { PFS_INVAL, 0, 0, 0},
121 };
122 #define SWIZZLE_XYZ 0
123 #define SWIZZLE_XXX 1
124 #define SWIZZLE_YYY 2
125 #define SWIZZLE_ZZZ 3
126 #define SWIZZLE_WWW 4
127 #define SWIZZLE_YZX 5
128 #define SWIZZLE_ZXY 6
129 #define SWIZZLE_WZY 7
130 #define SWIZZLE_111 8
131 #define SWIZZLE_000 9
132 #define SWIZZLE_HHH 10
133
134 #define SWZ_X_MASK (7 << 0)
135 #define SWZ_Y_MASK (7 << 3)
136 #define SWZ_Z_MASK (7 << 6)
137 #define SWZ_W_MASK (7 << 9)
138 /* used during matching of non-native swizzles */
139 static const struct {
140 GLuint hash; /* used to mask matching swizzle components */
141 int mask; /* actual outmask */
142 int count; /* count of components matched */
143 } s_mask[] = {
144 { SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK, 1|2|4, 3},
145 { SWZ_X_MASK|SWZ_Y_MASK, 1|2, 2},
146 { SWZ_X_MASK|SWZ_Z_MASK, 1|4, 2},
147 { SWZ_Y_MASK|SWZ_Z_MASK, 2|4, 2},
148 { SWZ_X_MASK, 1, 1},
149 { SWZ_Y_MASK, 2, 1},
150 { SWZ_Z_MASK, 4, 1},
151 { PFS_INVAL, PFS_INVAL, PFS_INVAL}
152 };
153
154 /* mapping from SWIZZLE_* to r300 native values for scalar insns */
155 static const struct {
156 int base; /* hw value of swizzle */
157 int stride; /* difference between SRC0/1/2 */
158 GLuint flags;
159 } s_swiz[] = {
160 { R300_FPI2_ARGA_SRC0C_X, 3, SLOT_VECTOR },
161 { R300_FPI2_ARGA_SRC0C_Y, 3, SLOT_VECTOR },
162 { R300_FPI2_ARGA_SRC0C_Z, 3, SLOT_VECTOR },
163 { R300_FPI2_ARGA_SRC0A , 1, SLOT_SCALAR },
164 { R300_FPI2_ARGA_ZERO , 0, 0 },
165 { R300_FPI2_ARGA_ONE , 0, 0 },
166 { R300_FPI2_ARGA_HALF , 0, 0 }
167 };
168 #define SWIZZLE_HALF 6
169
170 /* boiler-plate reg, for convenience */
171 static const pfs_reg_t undef = {
172 type: REG_TYPE_TEMP,
173 index: 0,
174 v_swz: SWIZZLE_XYZ,
175 s_swz: SWIZZLE_W,
176 negate_v: 0,
177 negate_s: 0,
178 absolute: 0,
179 no_use: GL_FALSE,
180 valid: GL_FALSE
181 };
182
183 /* constant zero source */
184 static const pfs_reg_t pfs_one = {
185 type: REG_TYPE_CONST,
186 index: 0,
187 v_swz: SWIZZLE_111,
188 s_swz: SWIZZLE_ONE,
189 valid: GL_TRUE
190 };
191
192 /* constant one source */
193 static const pfs_reg_t pfs_zero = {
194 type: REG_TYPE_CONST,
195 index: 0,
196 v_swz: SWIZZLE_000,
197 s_swz: SWIZZLE_ZERO,
198 valid: GL_TRUE
199 };
200
201 /***************************************
202 * end: data structures
203 ***************************************/
204
205 #define ERROR(fmt, args...) do { \
206 fprintf(stderr, "%s::%s(): " fmt "\n",\
207 __FILE__, __func__, ##args); \
208 rp->error = GL_TRUE; \
209 } while(0)
210
211 static int get_hw_temp(struct r300_fragment_program *rp)
212 {
213 COMPILE_STATE;
214 int r = ffs(~cs->hwreg_in_use);
215 if (!r) {
216 ERROR("Out of hardware temps\n");
217 return 0;
218 }
219
220 cs->hwreg_in_use |= (1 << --r);
221 if (r > rp->max_temp_idx)
222 rp->max_temp_idx = r;
223
224 return r;
225 }
226
227 static int get_hw_temp_tex(struct r300_fragment_program *rp)
228 {
229 COMPILE_STATE;
230 int r;
231
232 r = ffs(~(cs->hwreg_in_use | cs->used_in_node));
233 if (!r)
234 return get_hw_temp(rp); /* Will cause an indirection */
235
236 cs->hwreg_in_use |= (1 << --r);
237 if (r > rp->max_temp_idx)
238 rp->max_temp_idx = r;
239
240 return r;
241 }
242
243 static void free_hw_temp(struct r300_fragment_program *rp, int idx)
244 {
245 COMPILE_STATE;
246 cs->hwreg_in_use &= ~(1<<idx);
247 }
248
249 static pfs_reg_t get_temp_reg(struct r300_fragment_program *rp)
250 {
251 COMPILE_STATE;
252 pfs_reg_t r = undef;
253
254 r.index = ffs(~cs->temp_in_use);
255 if (!r.index) {
256 ERROR("Out of program temps\n");
257 return r;
258 }
259 cs->temp_in_use |= (1 << --r.index);
260
261 cs->temps[r.index].refcount = 0xFFFFFFFF;
262 cs->temps[r.index].reg = -1;
263 r.valid = GL_TRUE;
264 return r;
265 }
266
267 static pfs_reg_t get_temp_reg_tex(struct r300_fragment_program *rp)
268 {
269 COMPILE_STATE;
270 pfs_reg_t r = undef;
271
272 r.index = ffs(~cs->temp_in_use);
273 if (!r.index) {
274 ERROR("Out of program temps\n");
275 return r;
276 }
277 cs->temp_in_use |= (1 << --r.index);
278
279 cs->temps[r.index].refcount = 0xFFFFFFFF;
280 cs->temps[r.index].reg = get_hw_temp_tex(rp);
281 r.valid = GL_TRUE;
282 return r;
283 }
284
285 static void free_temp(struct r300_fragment_program *rp, pfs_reg_t r)
286 {
287 COMPILE_STATE;
288 if (!(cs->temp_in_use & (1<<r.index))) return;
289
290 if (r.type == REG_TYPE_TEMP) {
291 free_hw_temp(rp, cs->temps[r.index].reg);
292 cs->temps[r.index].reg = -1;
293 cs->temp_in_use &= ~(1<<r.index);
294 } else if (r.type == REG_TYPE_INPUT) {
295 free_hw_temp(rp, cs->inputs[r.index].reg);
296 cs->inputs[r.index].reg = -1;
297 }
298 }
299
300 static pfs_reg_t emit_param4fv(struct r300_fragment_program *rp,
301 GLfloat *values)
302 {
303 pfs_reg_t r = undef;
304 r.type = REG_TYPE_CONST;
305 int pidx;
306
307 pidx = rp->param_nr++;
308 r.index = rp->const_nr++;
309 if (pidx >= PFS_NUM_CONST_REGS || r.index >= PFS_NUM_CONST_REGS) {
310 ERROR("Out of const/param slots!\n");
311 return r;
312 }
313
314 rp->param[pidx].idx = r.index;
315 rp->param[pidx].values = values;
316 rp->params_uptodate = GL_FALSE;
317
318 r.valid = GL_TRUE;
319 return r;
320 }
321
322 #if 0
323 static pfs_reg_t emit_const4fv(struct r300_fragment_program *rp, GLfloat *cp)
324 {
325 pfs_reg_t r = undef;
326 r.type = REG_TYPE_CONST;
327
328 r.index = rp->const_nr++;
329 if (r.index >= PFS_NUM_CONST_REGS) {
330 ERROR("Out of hw constants!\n");
331 return r;
332 }
333
334 COPY_4V(rp->constant[r.index], cp);
335
336 r.valid = GL_TRUE;
337 return r;
338 }
339 #endif
340
341 static __inline pfs_reg_t negate(pfs_reg_t r)
342 {
343 r.negate_v = 1;
344 r.negate_s = 1;
345 return r;
346 }
347
348 /* Hack, to prevent clobbering sources used multiple times when
349 * emulating non-native instructions
350 */
351 static __inline pfs_reg_t keep(pfs_reg_t r)
352 {
353 r.no_use = GL_TRUE;
354 return r;
355 }
356
357 static __inline pfs_reg_t absolute(pfs_reg_t r)
358 {
359 r.absolute = 1;
360 return r;
361 }
362
363 static int swz_native(struct r300_fragment_program *rp,
364 pfs_reg_t src, pfs_reg_t *r, GLuint arbneg)
365 {
366 /* Native swizzle, nothing to see here */
367 src.negate_s = (arbneg >> 3) & 1;
368
369 if ((arbneg & 0x7) == 0x0) {
370 src.negate_v = 0;
371 *r = src;
372 } else if ((arbneg & 0x7) == 0x7) {
373 src.negate_v = 1;
374 *r = src;
375 } else {
376 if (!r->valid)
377 *r = get_temp_reg(rp);
378 src.negate_v = 1;
379 emit_arith(rp, PFS_OP_MAD, *r, arbneg & 0x7,
380 keep(src), pfs_one, pfs_zero, 0);
381 src.negate_v = 0;
382 emit_arith(rp, PFS_OP_MAD, *r,
383 (arbneg ^ 0x7) | WRITEMASK_W,
384 src, pfs_one, pfs_zero, 0);
385 }
386
387 return 3;
388 }
389
390 static int swz_emit_partial(struct r300_fragment_program *rp, pfs_reg_t src,
391 pfs_reg_t *r, int mask, int mc, GLuint arbneg)
392 {
393 GLuint tmp;
394 GLuint wmask = 0;
395
396 if (!r->valid)
397 *r = get_temp_reg(rp);
398
399 /* A partial match, src.v_swz/mask define what parts of the
400 * desired swizzle we match */
401 if (mc + s_mask[mask].count == 3) {
402 wmask = WRITEMASK_W;
403 src.negate_s = (arbneg >> 3) & 1;
404 }
405
406 tmp = arbneg & s_mask[mask].mask;
407 if (tmp) {
408 tmp = tmp ^ s_mask[mask].mask;
409 if (tmp) {
410 src.negate_v = 1;
411 emit_arith(rp, PFS_OP_MAD, *r,
412 arbneg & s_mask[mask].mask,
413 keep(src), pfs_one, pfs_zero, 0);
414 src.negate_v = 0;
415 if (!wmask) src.no_use = GL_TRUE;
416 else src.no_use = GL_FALSE;
417 emit_arith(rp, PFS_OP_MAD, *r, tmp | wmask,
418 src, pfs_one, pfs_zero, 0);
419 } else {
420 src.negate_v = 1;
421 if (!wmask) src.no_use = GL_TRUE;
422 else src.no_use = GL_FALSE;
423 emit_arith(rp, PFS_OP_MAD, *r,
424 (arbneg & s_mask[mask].mask) | wmask,
425 src, pfs_one, pfs_zero, 0);
426 src.negate_v = 0;
427 }
428 } else {
429 if (!wmask) src.no_use = GL_TRUE;
430 else src.no_use = GL_FALSE;
431 emit_arith(rp, PFS_OP_MAD, *r,
432 s_mask[mask].mask | wmask,
433 src, pfs_one, pfs_zero, 0);
434 }
435
436 return s_mask[mask].count;
437 }
438
439 #define swizzle(r, x, y, z, w) do_swizzle(rp, r, \
440 ((SWIZZLE_##x<<0)| \
441 (SWIZZLE_##y<<3)| \
442 (SWIZZLE_##z<<6)| \
443 (SWIZZLE_##w<<9)), \
444 0)
445
446 static pfs_reg_t do_swizzle(struct r300_fragment_program *rp,
447 pfs_reg_t src, GLuint arbswz, GLuint arbneg)
448 {
449 pfs_reg_t r = undef;
450
451 int c_mask = 0;
452 int v_matched = 0;
453
454 /* If swizzling from something without an XYZW native swizzle,
455 * emit result to a temp, and do new swizzle from the temp.
456 */
457 if (src.v_swz != SWIZZLE_XYZ || src.s_swz != SWIZZLE_W) {
458 pfs_reg_t temp = get_temp_reg(rp);
459 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_XYZW, src, pfs_one,
460 pfs_zero, 0);
461 src = temp;
462 }
463 src.s_swz = GET_SWZ(arbswz, 3);
464
465 do {
466 do {
467 #define CUR_HASH (v_swiz[src.v_swz].hash & s_mask[c_mask].hash)
468 if (CUR_HASH == (arbswz & s_mask[c_mask].hash)) {
469 if (s_mask[c_mask].count == 3)
470 v_matched += swz_native(rp, src, &r,
471 arbneg);
472 else
473 v_matched += swz_emit_partial(rp, src,
474 &r,
475 c_mask,
476 v_matched,
477 arbneg);
478
479 if (v_matched == 3)
480 return r;
481
482 /* Fill with something invalid.. all 0's was
483 * wrong before, matched SWIZZLE_X. So all
484 * 1's will be okay for now */
485 arbswz |= (PFS_INVAL & s_mask[c_mask].hash);
486 }
487 } while(v_swiz[++src.v_swz].hash != PFS_INVAL);
488 src.v_swz = SWIZZLE_XYZ;
489 } while (s_mask[++c_mask].hash != PFS_INVAL);
490
491 ERROR("should NEVER get here\n");
492 return r;
493 }
494
495 static pfs_reg_t t_src(struct r300_fragment_program *rp,
496 struct prog_src_register fpsrc)
497 {
498 pfs_reg_t r = undef;
499 #if 0
500 pfs_reg_t n = undef;
501 #endif
502
503 switch (fpsrc.File) {
504 case PROGRAM_TEMPORARY:
505 r.index = fpsrc.Index;
506 r.valid = GL_TRUE;
507 break;
508 case PROGRAM_INPUT:
509 r.index = fpsrc.Index;
510 r.type = REG_TYPE_INPUT;
511 r.valid = GL_TRUE;
512 break;
513 case PROGRAM_LOCAL_PARAM:
514 r = emit_param4fv(rp,
515 rp->mesa_program.Base.LocalParams[fpsrc.Index]);
516 break;
517 case PROGRAM_ENV_PARAM:
518 r = emit_param4fv(rp,
519 rp->ctx->FragmentProgram.Parameters[fpsrc.Index]);
520 break;
521 case PROGRAM_STATE_VAR:
522 case PROGRAM_NAMED_PARAM:
523 r = emit_param4fv(rp,
524 rp->mesa_program.Base.Parameters->ParameterValues[fpsrc.Index]);
525 break;
526 default:
527 ERROR("unknown SrcReg->File %x\n", fpsrc.File);
528 return r;
529 }
530
531 /* no point swizzling ONE/ZERO/HALF constants... */
532 if (r.v_swz < SWIZZLE_111 && r.s_swz < SWIZZLE_ZERO)
533 r = do_swizzle(rp, r, fpsrc.Swizzle, fpsrc.NegateBase);
534 #if 0
535 /* WRONG! Need to be able to do individual component negation,
536 * should probably handle this in the swizzling code unless
537 * all components are negated, then we can do this natively */
538 if ((fpsrc.NegateBase & 0xf) == 0xf)
539 r.negate = GL_TRUE;
540
541 r.negate_s = (fpsrc.NegateBase >> 3) & 1;
542
543 if ((fpsrc.NegateBase & 0x7) == 0x0) {
544 r.negate_v = 0;
545 } else if ((fpsrc.NegateBase & 0x7) == 0x7) {
546 r.negate_v = 1;
547 } else {
548 if (r.type != REG_TYPE_TEMP) {
549 n = get_temp_reg(rp);
550 emit_arith(rp, PFS_OP_MAD, n, 0x7 ^ fpsrc.NegateBase,
551 keep(r), pfs_one, pfs_zero, 0);
552 r.negate_v = 1;
553 emit_arith(rp, PFS_OP_MAD, n,
554 fpsrc.NegateBase & 0x7 | WRITEMASK_W,
555 r, pfs_one, pfs_zero, 0);
556 r.negate_v = 0;
557 r = n;
558 } else {
559 r.negate_v = 1;
560 emit_arith(rp, PFS_OP_MAD, r,
561 fpsrc.NegateBase & 0x7 | WRITEMASK_W,
562 r, pfs_one, pfs_zero, 0);
563 r.negate_v = 0;
564 }
565 }
566 #endif
567
568 return r;
569 }
570
571 static pfs_reg_t t_scalar_src(struct r300_fragment_program *rp,
572 struct prog_src_register fpsrc)
573 {
574 struct prog_src_register src = fpsrc;
575 int sc = GET_SWZ(fpsrc.Swizzle, 0); /* X */
576
577 src.Swizzle = ((sc<<0)|(sc<<3)|(sc<<6)|(sc<<9));
578
579 return t_src(rp, src);
580 }
581
582 static pfs_reg_t t_dst(struct r300_fragment_program *rp,
583 struct prog_dst_register dest) {
584 pfs_reg_t r = undef;
585
586 switch (dest.File) {
587 case PROGRAM_TEMPORARY:
588 r.index = dest.Index;
589 r.valid = GL_TRUE;
590 return r;
591 case PROGRAM_OUTPUT:
592 r.type = REG_TYPE_OUTPUT;
593 switch (dest.Index) {
594 case FRAG_RESULT_COLR:
595 case FRAG_RESULT_DEPR:
596 r.index = dest.Index;
597 r.valid = GL_TRUE;
598 return r;
599 default:
600 ERROR("Bad DstReg->Index 0x%x\n", dest.Index);
601 return r;
602 }
603 default:
604 ERROR("Bad DstReg->File 0x%x\n", dest.File);
605 return r;
606 }
607 }
608
609 static int t_hw_src(struct r300_fragment_program *rp, pfs_reg_t src,
610 GLboolean tex)
611 {
612 COMPILE_STATE;
613 int idx;
614
615 switch (src.type) {
616 case REG_TYPE_TEMP:
617 /* NOTE: if reg==-1 here, a source is being read that
618 * hasn't been written to. Undefined results */
619 if (cs->temps[src.index].reg == -1)
620 cs->temps[src.index].reg = get_hw_temp(rp);
621 idx = cs->temps[src.index].reg;
622
623 if (!src.no_use && (--cs->temps[src.index].refcount == 0))
624 free_temp(rp, src);
625 break;
626 case REG_TYPE_INPUT:
627 idx = cs->inputs[src.index].reg;
628
629 if (!src.no_use && (--cs->inputs[src.index].refcount == 0))
630 free_hw_temp(rp, cs->inputs[src.index].reg);
631 break;
632 case REG_TYPE_CONST:
633 return (src.index | SRC_CONST);
634 default:
635 ERROR("Invalid type for source reg\n");
636 return (0 | SRC_CONST);
637 }
638
639 if (!tex) cs->used_in_node |= (1 << idx);
640
641 return idx;
642 }
643
644 static int t_hw_dst(struct r300_fragment_program *rp, pfs_reg_t dest,
645 GLboolean tex)
646 {
647 COMPILE_STATE;
648 int idx;
649 assert(dest.valid);
650
651 switch (dest.type) {
652 case REG_TYPE_TEMP:
653 if (cs->temps[dest.index].reg == -1) {
654 if (!tex)
655 cs->temps[dest.index].reg = get_hw_temp(rp);
656 else
657 cs->temps[dest.index].reg = get_hw_temp_tex(rp);
658 }
659 idx = cs->temps[dest.index].reg;
660
661 if (!dest.no_use && (--cs->temps[dest.index].refcount == 0))
662 free_temp(rp, dest);
663
664 cs->dest_in_node |= (1 << idx);
665 cs->used_in_node |= (1 << idx);
666 break;
667 case REG_TYPE_OUTPUT:
668 switch (dest.index) {
669 case FRAG_RESULT_COLR:
670 rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_COLOR;
671 break;
672 case FRAG_RESULT_DEPR:
673 rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_DEPTH;
674 break;
675 }
676 return dest.index;
677 break;
678 default:
679 ERROR("invalid dest reg type %d\n", dest.type);
680 return 0;
681 }
682
683 return idx;
684 }
685
686 static void emit_nop(struct r300_fragment_program *rp, GLuint mask,
687 GLboolean sync)
688 {
689 COMPILE_STATE;
690
691 if (sync)
692 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
693
694 if (mask & WRITEMASK_XYZ) {
695 rp->alu.inst[cs->v_pos].inst0 = NOP_INST0;
696 rp->alu.inst[cs->v_pos].inst1 = NOP_INST1;
697 cs->v_pos++;
698 }
699
700 if (mask & WRITEMASK_W) {
701 rp->alu.inst[cs->s_pos].inst2 = NOP_INST2;
702 rp->alu.inst[cs->s_pos].inst3 = NOP_INST3;
703 cs->s_pos++;
704 }
705 }
706
707 static void emit_tex(struct r300_fragment_program *rp,
708 struct prog_instruction *fpi,
709 int opcode)
710 {
711 COMPILE_STATE;
712 pfs_reg_t coord = t_src(rp, fpi->SrcReg[0]);
713 pfs_reg_t dest = undef, rdest = undef;
714 GLuint din = cs->dest_in_node, uin = cs->used_in_node;
715 int unit = fpi->TexSrcUnit;
716 int hwsrc, hwdest;
717
718 /* Resolve source/dest to hardware registers */
719 hwsrc = t_hw_src(rp, coord, GL_TRUE);
720 if (opcode != R300_FPITX_OP_KIL) {
721 dest = t_dst(rp, fpi->DstReg);
722
723 /* r300 doesn't seem to be able to do TEX->output reg */
724 if (dest.type == REG_TYPE_OUTPUT) {
725 rdest = dest;
726 dest = get_temp_reg_tex(rp);
727 }
728 hwdest = t_hw_dst(rp, dest, GL_TRUE);
729
730 /* Use a temp that hasn't been used in this node, rather
731 * than causing an indirection
732 */
733 if (uin & (1 << hwdest)) {
734 free_hw_temp(rp, hwdest);
735 hwdest = get_hw_temp_tex(rp);
736 cs->temps[dest.index].reg = hwdest;
737 }
738 } else {
739 hwdest = 0;
740 unit = 0;
741 }
742
743 /* Indirection if source has been written in this node, or if the
744 * dest has been read/written in this node
745 */
746 if ((coord.type != REG_TYPE_CONST && (din & (1<<hwsrc))) ||
747 (uin & (1<<hwdest))) {
748
749 /* Finish off current node */
750 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
751 if (rp->node[rp->cur_node].alu_offset == cs->v_pos) {
752 /* No alu instructions in the node? Emit a NOP. */
753 emit_nop(rp, WRITEMASK_XYZW, GL_TRUE);
754 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
755 }
756
757 rp->node[rp->cur_node].alu_end =
758 cs->v_pos - rp->node[rp->cur_node].alu_offset - 1;
759 assert(rp->node[rp->cur_node].alu_end >= 0);
760
761 if (++rp->cur_node >= PFS_MAX_TEX_INDIRECT) {
762 ERROR("too many levels of texture indirection\n");
763 return;
764 }
765
766 /* Start new node */
767 rp->node[rp->cur_node].tex_offset = rp->tex.length;
768 rp->node[rp->cur_node].alu_offset = cs->v_pos;
769 rp->node[rp->cur_node].tex_end = -1;
770 rp->node[rp->cur_node].alu_end = -1;
771 rp->node[rp->cur_node].flags = 0;
772 cs->used_in_node = 0;
773 cs->dest_in_node = 0;
774 }
775
776 if (rp->cur_node == 0) rp->first_node_has_tex = 1;
777
778 rp->tex.inst[rp->tex.length++] = 0
779 | (hwsrc << R300_FPITX_SRC_SHIFT)
780 | (hwdest << R300_FPITX_DST_SHIFT)
781 | (unit << R300_FPITX_IMAGE_SHIFT)
782 | (opcode << R300_FPITX_OPCODE_SHIFT); /* not entirely sure about this */
783
784 cs->dest_in_node |= (1 << hwdest);
785 if (coord.type != REG_TYPE_CONST)
786 cs->used_in_node |= (1 << hwsrc);
787
788 rp->node[rp->cur_node].tex_end++;
789
790 /* Copy from temp to output if needed */
791 if (rdest.valid) {
792 emit_arith(rp, PFS_OP_MAD, rdest, WRITEMASK_XYZW, dest,
793 pfs_one, pfs_zero, 0);
794 free_temp(rp, dest);
795 }
796 }
797
798 /* Add sources to FPI1/FPI3 lists. If source is already on list,
799 * reuse the index instead of wasting a source.
800 */
801 static int add_src(struct r300_fragment_program *rp, int reg, int pos,
802 int srcmask)
803 {
804 COMPILE_STATE;
805 int csm, i;
806
807 /* Look for matches */
808 for (i=0,csm=srcmask; i<3; i++,csm=csm<<1) {
809 /* If sources have been allocated in this position(s)... */
810 if ((cs->slot[pos].umask & csm) == csm) {
811 /* ... and the register number(s) match, re-use the
812 source */
813 if (srcmask == SLOT_VECTOR &&
814 cs->slot[pos].vsrc[i] == reg)
815 return i;
816 if (srcmask == SLOT_SCALAR &&
817 cs->slot[pos].ssrc[i] == reg)
818 return i;
819 if (srcmask == SLOT_BOTH &&
820 cs->slot[pos].vsrc[i] == reg &&
821 cs->slot[pos].ssrc[i] == reg)
822 return i;
823 }
824 }
825
826 /* Look for free spaces */
827 for (i=0,csm=srcmask; i<3; i++,csm=csm<<1) {
828 /* If the position(s) haven't been allocated */
829 if ((cs->slot[pos].umask & csm) == 0) {
830 cs->slot[pos].umask |= csm;
831
832 if (srcmask & SLOT_VECTOR)
833 cs->slot[pos].vsrc[i] = reg;
834 if (srcmask & SLOT_SCALAR)
835 cs->slot[pos].ssrc[i] = reg;
836 return i;
837 }
838 }
839
840 //ERROR("Failed to allocate sources in FPI1/FPI3!\n");
841 return 0;
842 }
843
844 /* Determine whether or not to position opcode in the same ALU slot for both
845 * vector and scalar portions of an instruction.
846 *
847 * It's not necessary to force the first case, but it makes disassembled
848 * shaders easier to read.
849 */
850 static GLboolean force_same_slot(int vop, int sop,
851 GLboolean emit_vop, GLboolean emit_sop,
852 int argc, pfs_reg_t *src)
853 {
854 int i;
855
856 if (emit_vop && emit_sop)
857 return GL_TRUE;
858
859 if (emit_vop && vop == R300_FPI0_OUTC_REPL_ALPHA)
860 return GL_TRUE;
861
862 if (emit_vop) {
863 for (i=0;i<argc;i++)
864 if (src[i].v_swz == SWIZZLE_WZY)
865 return GL_TRUE;
866 }
867
868 return GL_FALSE;
869 }
870
871 static void emit_arith(struct r300_fragment_program *rp, int op,
872 pfs_reg_t dest, int mask,
873 pfs_reg_t src0, pfs_reg_t src1, pfs_reg_t src2,
874 int flags)
875 {
876 COMPILE_STATE;
877 pfs_reg_t src[3] = { src0, src1, src2 };
878 int hwsrc[3], sswz[3], vswz[3];
879 int hwdest;
880 GLboolean emit_vop = GL_FALSE, emit_sop = GL_FALSE;
881 int vop, sop, argc;
882 int vpos, spos;
883 int i;
884
885 vop = r300_fpop[op].v_op;
886 sop = r300_fpop[op].s_op;
887 argc = r300_fpop[op].argc;
888
889 if ((mask & WRITEMASK_XYZ) || vop == R300_FPI0_OUTC_DP3)
890 emit_vop = GL_TRUE;
891 if ((mask & WRITEMASK_W) || vop == R300_FPI0_OUTC_REPL_ALPHA)
892 emit_sop = GL_TRUE;
893
894 if (dest.type == REG_TYPE_OUTPUT && dest.index == FRAG_RESULT_DEPR)
895 emit_vop = GL_FALSE;
896
897 if (force_same_slot(vop, sop, emit_vop, emit_sop, argc, src)) {
898 vpos = spos = MAX2(cs->v_pos, cs->s_pos);
899 } else {
900 vpos = cs->v_pos;
901 spos = cs->s_pos;
902 /* Here is where we'd decide on where a safe place is to
903 * combine this instruction with a previous one.
904 *
905 * This is extremely simple for now.. if a source depends
906 * on the opposite stream, force the same instruction.
907 */
908 for (i=0;i<3;i++) {
909 if (emit_vop &&
910 (v_swiz[src[i].v_swz].flags & SLOT_SCALAR)) {
911 vpos = spos = MAX2(vpos, spos);
912 break;
913 }
914 if (emit_sop &&
915 (s_swiz[src[i].s_swz].flags & SLOT_VECTOR)) {
916 vpos = spos = MAX2(vpos, spos);
917 break;
918 }
919 }
920 }
921
922 /* - Convert src->hwsrc, record for FPI1/FPI3
923 * - Determine ARG parts of FPI0/FPI2, unused args are filled
924 * with ARG_ZERO.
925 */
926 for (i=0;i<3;i++) {
927 int srcpos;
928
929 if (i >= argc) {
930 vswz[i] = R300_FPI0_ARGC_ZERO;
931 sswz[i] = R300_FPI2_ARGA_ZERO;
932 continue;
933 }
934
935 hwsrc[i] = t_hw_src(rp, src[i], GL_FALSE);
936
937 if (emit_vop && vop != R300_FPI0_OUTC_REPL_ALPHA) {
938 srcpos = add_src(rp, hwsrc[i], vpos,
939 v_swiz[src[i].v_swz].flags);
940 vswz[i] = (v_swiz[src[i].v_swz].base +
941 (srcpos * v_swiz[src[i].v_swz].stride)) |
942 (src[i].negate_v ? ARG_NEG : 0) |
943 (src[i].absolute ? ARG_ABS : 0);
944 } else vswz[i] = R300_FPI0_ARGC_ZERO;
945
946 if (emit_sop) {
947 srcpos = add_src(rp, hwsrc[i], spos,
948 s_swiz[src[i].s_swz].flags);
949 sswz[i] = (s_swiz[src[i].s_swz].base +
950 (srcpos * s_swiz[src[i].s_swz].stride)) |
951 (src[i].negate_s ? ARG_NEG : 0) |
952 (src[i].absolute ? ARG_ABS : 0);
953 } else sswz[i] = R300_FPI2_ARGA_ZERO;
954 }
955 hwdest = t_hw_dst(rp, dest, GL_FALSE);
956
957 if (flags & PFS_FLAG_SAT) {
958 vop |= R300_FPI0_OUTC_SAT;
959 sop |= R300_FPI2_OUTA_SAT;
960 }
961
962 /* Throw the pieces together and get FPI0/1 */
963 rp->alu.inst[vpos].inst1 =
964 ((cs->slot[vpos].vsrc[0] << R300_FPI1_SRC0C_SHIFT) |
965 (cs->slot[vpos].vsrc[1] << R300_FPI1_SRC1C_SHIFT) |
966 (cs->slot[vpos].vsrc[2] << R300_FPI1_SRC2C_SHIFT));
967 if (emit_vop) {
968 rp->alu.inst[vpos].inst0 = vop |
969 (vswz[0] << R300_FPI0_ARG0C_SHIFT) |
970 (vswz[1] << R300_FPI0_ARG1C_SHIFT) |
971 (vswz[2] << R300_FPI0_ARG2C_SHIFT);
972
973 rp->alu.inst[vpos].inst1 |= hwdest << R300_FPI1_DSTC_SHIFT;
974 if (dest.type == REG_TYPE_OUTPUT) {
975 if (dest.index == FRAG_RESULT_COLR) {
976 rp->alu.inst[vpos].inst1 |=
977 (mask & WRITEMASK_XYZ) << R300_FPI1_DSTC_OUTPUT_MASK_SHIFT;
978 } else assert(0);
979 } else {
980 rp->alu.inst[vpos].inst1 |=
981 (mask & WRITEMASK_XYZ) << R300_FPI1_DSTC_REG_MASK_SHIFT;
982 }
983 cs->v_pos = vpos+1;
984 } else if (spos >= vpos)
985 rp->alu.inst[spos].inst0 = NOP_INST0;
986
987 /* And now FPI2/3 */
988 rp->alu.inst[spos].inst3 =
989 ((cs->slot[spos].ssrc[0] << R300_FPI3_SRC0A_SHIFT) |
990 (cs->slot[spos].ssrc[1] << R300_FPI3_SRC1A_SHIFT) |
991 (cs->slot[spos].ssrc[2] << R300_FPI3_SRC2A_SHIFT));
992 if (emit_sop) {
993 rp->alu.inst[spos].inst2 = sop |
994 sswz[0] << R300_FPI2_ARG0A_SHIFT |
995 sswz[1] << R300_FPI2_ARG1A_SHIFT |
996 sswz[2] << R300_FPI2_ARG2A_SHIFT;
997
998 if (mask & WRITEMASK_W) {
999 if (dest.type == REG_TYPE_OUTPUT) {
1000 if (dest.index == FRAG_RESULT_COLR) {
1001 rp->alu.inst[spos].inst3 |=
1002 (hwdest << R300_FPI3_DSTA_SHIFT) | R300_FPI3_DSTA_OUTPUT;
1003 } else if (dest.index == FRAG_RESULT_DEPR) {
1004 rp->alu.inst[spos].inst3 |= R300_FPI3_DSTA_DEPTH;
1005 } else assert(0);
1006 } else {
1007 rp->alu.inst[spos].inst3 |=
1008 (hwdest << R300_FPI3_DSTA_SHIFT) | R300_FPI3_DSTA_REG;
1009 }
1010 }
1011 cs->s_pos = spos+1;
1012 } else if (vpos >= spos)
1013 rp->alu.inst[vpos].inst2 = NOP_INST2;
1014
1015 return;
1016 };
1017
1018 #if 0
1019 static pfs_reg_t get_attrib(struct r300_fragment_program *rp, GLuint attr)
1020 {
1021 struct fragment_program *mp = &rp->mesa_program;
1022 pfs_reg_t r = undef;
1023
1024 if (!(mp->Base.InputsRead & (1<<attr))) {
1025 ERROR("Attribute %d was not provided!\n", attr);
1026 return undef;
1027 }
1028
1029 r.type = REG_TYPE_INPUT;
1030 r.index = attr;
1031 r.valid = GL_TRUE;
1032 return r;
1033 }
1034 #endif
1035
1036 static GLboolean parse_program(struct r300_fragment_program *rp)
1037 {
1038 struct fragment_program *mp = &rp->mesa_program;
1039 const struct prog_instruction *inst = mp->Base.Instructions;
1040 struct prog_instruction *fpi;
1041 pfs_reg_t src[3], dest, temp;
1042 int flags, mask;
1043
1044 if (!inst || inst[0].Opcode == OPCODE_END) {
1045 ERROR("empty program?\n");
1046 return GL_FALSE;
1047 }
1048
1049 for (fpi=mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
1050 if (fpi->SaturateMode == SATURATE_ZERO_ONE)
1051 flags = PFS_FLAG_SAT;
1052 else
1053 flags = 0;
1054
1055 if (fpi->Opcode != OPCODE_KIL) {
1056 dest = t_dst(rp, fpi->DstReg);
1057 mask = fpi->DstReg.WriteMask;
1058 }
1059
1060 switch (fpi->Opcode) {
1061 case OPCODE_ABS:
1062 src[0] = t_src(rp, fpi->SrcReg[0]);
1063 emit_arith(rp, PFS_OP_MAD, dest, mask,
1064 absolute(src[0]), pfs_one, pfs_zero,
1065 flags);
1066 break;
1067 case OPCODE_ADD:
1068 src[0] = t_src(rp, fpi->SrcReg[0]);
1069 src[1] = t_src(rp, fpi->SrcReg[1]);
1070 emit_arith(rp, PFS_OP_MAD, dest, mask,
1071 src[0], pfs_one, src[1],
1072 flags);
1073 break;
1074 case OPCODE_CMP:
1075 src[0] = t_src(rp, fpi->SrcReg[0]);
1076 src[1] = t_src(rp, fpi->SrcReg[1]);
1077 src[2] = t_src(rp, fpi->SrcReg[2]);
1078 /* ARB_f_p - if src0.c < 0.0 ? src1.c : src2.c
1079 * r300 - if src2.c < 0.0 ? src1.c : src0.c
1080 */
1081 emit_arith(rp, PFS_OP_CMP, dest, mask,
1082 src[2], src[1], src[0],
1083 flags);
1084 break;
1085 case OPCODE_COS:
1086 ERROR("COS not implemented\n");
1087 break;
1088 case OPCODE_DP3:
1089 src[0] = t_src(rp, fpi->SrcReg[0]);
1090 src[1] = t_src(rp, fpi->SrcReg[1]);
1091 emit_arith(rp, PFS_OP_DP3, dest, mask,
1092 src[0], src[1], undef,
1093 flags);
1094 break;
1095 case OPCODE_DP4:
1096 src[0] = t_src(rp, fpi->SrcReg[0]);
1097 src[1] = t_src(rp, fpi->SrcReg[1]);
1098 emit_arith(rp, PFS_OP_DP4, dest, mask,
1099 src[0], src[1], undef,
1100 flags);
1101 break;
1102 case OPCODE_DPH:
1103 src[0] = t_src(rp, fpi->SrcReg[0]);
1104 src[1] = t_src(rp, fpi->SrcReg[1]);
1105 /* src0.xyz1 -> temp
1106 * DP4 dest, temp, src1
1107 */
1108 #if 0
1109 temp = get_temp_reg(rp);
1110 src[0].s_swz = SWIZZLE_ONE;
1111 emit_arith(rp, PFS_OP_MAD, temp, mask,
1112 src[0], pfs_one, pfs_zero,
1113 0);
1114 emit_arith(rp, PFS_OP_DP4, dest, mask,
1115 temp, src[1], undef,
1116 flags);
1117 free_temp(rp, temp);
1118 #else
1119 emit_arith(rp, PFS_OP_DP4, dest, mask,
1120 swizzle(src[0], X, Y, Z, ONE), src[1],
1121 undef, flags);
1122 #endif
1123 break;
1124 case OPCODE_DST:
1125 src[0] = t_src(rp, fpi->SrcReg[0]);
1126 src[1] = t_src(rp, fpi->SrcReg[1]);
1127 /* dest.y = src0.y * src1.y */
1128 if (mask & WRITEMASK_Y)
1129 emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Y,
1130 keep(src[0]), keep(src[1]),
1131 pfs_zero, flags);
1132 /* dest.z = src0.z */
1133 if (mask & WRITEMASK_Z)
1134 emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Z,
1135 src[0], pfs_one, pfs_zero, flags);
1136 /* result.x = 1.0
1137 * result.w = src1.w */
1138 if (mask & WRITEMASK_XW) {
1139 src[1].v_swz = SWIZZLE_111; /* Cheat.. */
1140 emit_arith(rp, PFS_OP_MAD, dest,
1141 mask & WRITEMASK_XW,
1142 src[1], pfs_one, pfs_zero,
1143 flags);
1144 }
1145 break;
1146 case OPCODE_EX2:
1147 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1148 emit_arith(rp, PFS_OP_EX2, dest, mask,
1149 src[0], undef, undef,
1150 flags);
1151 break;
1152 case OPCODE_FLR:
1153 src[0] = t_src(rp, fpi->SrcReg[0]);
1154 temp = get_temp_reg(rp);
1155 /* FRC temp, src0
1156 * MAD dest, src0, 1.0, -temp
1157 */
1158 emit_arith(rp, PFS_OP_FRC, temp, mask,
1159 keep(src[0]), undef, undef,
1160 0);
1161 emit_arith(rp, PFS_OP_MAD, dest, mask,
1162 src[0], pfs_one, negate(temp),
1163 flags);
1164 free_temp(rp, temp);
1165 break;
1166 case OPCODE_FRC:
1167 src[0] = t_src(rp, fpi->SrcReg[0]);
1168 emit_arith(rp, PFS_OP_FRC, dest, mask,
1169 src[0], undef, undef,
1170 flags);
1171 break;
1172 case OPCODE_KIL:
1173 emit_tex(rp, fpi, R300_FPITX_OP_KIL);
1174 break;
1175 case OPCODE_LG2:
1176 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1177 emit_arith(rp, PFS_OP_LG2, dest, mask,
1178 src[0], undef, undef,
1179 flags);
1180 break;
1181 case OPCODE_LIT:
1182 ERROR("LIT not implemented\n");
1183 break;
1184 case OPCODE_LRP:
1185 src[0] = t_src(rp, fpi->SrcReg[0]);
1186 src[1] = t_src(rp, fpi->SrcReg[1]);
1187 src[2] = t_src(rp, fpi->SrcReg[2]);
1188 /* result = tmp0tmp1 + (1 - tmp0)tmp2
1189 * = tmp0tmp1 + tmp2 + (-tmp0)tmp2
1190 * MAD temp, -tmp0, tmp2, tmp2
1191 * MAD result, tmp0, tmp1, temp
1192 */
1193 temp = get_temp_reg(rp);
1194 emit_arith(rp, PFS_OP_MAD, temp, mask,
1195 negate(keep(src[0])), keep(src[2]), src[2],
1196 0);
1197 emit_arith(rp, PFS_OP_MAD, dest, mask,
1198 src[0], src[1], temp,
1199 flags);
1200 free_temp(rp, temp);
1201 break;
1202 case OPCODE_MAD:
1203 src[0] = t_src(rp, fpi->SrcReg[0]);
1204 src[1] = t_src(rp, fpi->SrcReg[1]);
1205 src[2] = t_src(rp, fpi->SrcReg[2]);
1206 emit_arith(rp, PFS_OP_MAD, dest, mask,
1207 src[0], src[1], src[2],
1208 flags);
1209 break;
1210 case OPCODE_MAX:
1211 src[0] = t_src(rp, fpi->SrcReg[0]);
1212 src[1] = t_src(rp, fpi->SrcReg[1]);
1213 emit_arith(rp, PFS_OP_MAX, dest, mask,
1214 src[0], src[1], undef,
1215 flags);
1216 break;
1217 case OPCODE_MIN:
1218 src[0] = t_src(rp, fpi->SrcReg[0]);
1219 src[1] = t_src(rp, fpi->SrcReg[1]);
1220 emit_arith(rp, PFS_OP_MIN, dest, mask,
1221 src[0], src[1], undef,
1222 flags);
1223 break;
1224 case OPCODE_MOV:
1225 case OPCODE_SWZ:
1226 src[0] = t_src(rp, fpi->SrcReg[0]);
1227 emit_arith(rp, PFS_OP_MAD, dest, mask,
1228 src[0], pfs_one, pfs_zero,
1229 flags);
1230 break;
1231 case OPCODE_MUL:
1232 src[0] = t_src(rp, fpi->SrcReg[0]);
1233 src[1] = t_src(rp, fpi->SrcReg[1]);
1234 emit_arith(rp, PFS_OP_MAD, dest, mask,
1235 src[0], src[1], pfs_zero,
1236 flags);
1237 break;
1238 case OPCODE_POW:
1239 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1240 src[1] = t_scalar_src(rp, fpi->SrcReg[1]);
1241 temp = get_temp_reg(rp);
1242 emit_arith(rp, PFS_OP_LG2, temp, WRITEMASK_W,
1243 src[0], undef, undef,
1244 0);
1245 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_W,
1246 temp, src[1], pfs_zero,
1247 0);
1248 emit_arith(rp, PFS_OP_EX2, dest, fpi->DstReg.WriteMask,
1249 temp, undef, undef,
1250 0);
1251 free_temp(rp, temp);
1252 break;
1253 case OPCODE_RCP:
1254 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1255 emit_arith(rp, PFS_OP_RCP, dest, mask,
1256 src[0], undef, undef,
1257 flags);
1258 break;
1259 case OPCODE_RSQ:
1260 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1261 emit_arith(rp, PFS_OP_RSQ, dest, mask,
1262 absolute(src[0]), pfs_zero, pfs_zero,
1263 flags);
1264 break;
1265 case OPCODE_SCS:
1266 ERROR("SCS not implemented\n");
1267 break;
1268 case OPCODE_SGE:
1269 src[0] = t_src(rp, fpi->SrcReg[0]);
1270 src[1] = t_src(rp, fpi->SrcReg[1]);
1271 temp = get_temp_reg(rp);
1272 /* temp = src0 - src1
1273 * dest.c = (temp.c < 0.0) ? 0 : 1
1274 */
1275 emit_arith(rp, PFS_OP_MAD, temp, mask,
1276 src[0], pfs_one, negate(src[1]),
1277 0);
1278 emit_arith(rp, PFS_OP_CMP, dest, mask,
1279 pfs_one, pfs_zero, temp,
1280 0);
1281 free_temp(rp, temp);
1282 break;
1283 case OPCODE_SIN:
1284 ERROR("SIN not implemented\n");
1285 break;
1286 case OPCODE_SLT:
1287 src[0] = t_src(rp, fpi->SrcReg[0]);
1288 src[1] = t_src(rp, fpi->SrcReg[1]);
1289 temp = get_temp_reg(rp);
1290 /* temp = src0 - src1
1291 * dest.c = (temp.c < 0.0) ? 1 : 0
1292 */
1293 emit_arith(rp, PFS_OP_MAD, temp, mask,
1294 src[0], pfs_one, negate(src[1]),
1295 0);
1296 emit_arith(rp, PFS_OP_CMP, dest, mask,
1297 pfs_zero, pfs_one, temp,
1298 0);
1299 free_temp(rp, temp);
1300 break;
1301 case OPCODE_SUB:
1302 src[0] = t_src(rp, fpi->SrcReg[0]);
1303 src[1] = t_src(rp, fpi->SrcReg[1]);
1304 emit_arith(rp, PFS_OP_MAD, dest, mask,
1305 src[0], pfs_one, negate(src[1]),
1306 flags);
1307 break;
1308 case OPCODE_TEX:
1309 emit_tex(rp, fpi, R300_FPITX_OP_TEX);
1310 break;
1311 case OPCODE_TXB:
1312 emit_tex(rp, fpi, R300_FPITX_OP_TXB);
1313 break;
1314 case OPCODE_TXP:
1315 emit_tex(rp, fpi, R300_FPITX_OP_TXP);
1316 break;
1317 case OPCODE_XPD: {
1318 src[0] = t_src(rp, fpi->SrcReg[0]);
1319 src[1] = t_src(rp, fpi->SrcReg[1]);
1320 temp = get_temp_reg(rp);
1321 /* temp = src0.zxy * src1.yzx */
1322 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_XYZ,
1323 swizzle(keep(src[0]), Z, X, Y, W),
1324 swizzle(keep(src[1]), Y, Z, X, W),
1325 pfs_zero,
1326 0);
1327 /* dest.xyz = src0.yzx * src1.zxy - temp
1328 * dest.w = undefined
1329 * */
1330 emit_arith(rp, PFS_OP_MAD, dest, mask & WRITEMASK_XYZ,
1331 swizzle(src[0], Y, Z, X, W),
1332 swizzle(src[1], Z, X, Y, W),
1333 negate(temp),
1334 flags);
1335 /* cleanup */
1336 free_temp(rp, temp);
1337 break;
1338 }
1339 default:
1340 ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
1341 break;
1342 }
1343
1344 if (rp->error)
1345 return GL_FALSE;
1346
1347 }
1348
1349 return GL_TRUE;
1350 }
1351
1352 /* - Init structures
1353 * - Determine what hwregs each input corresponds to
1354 */
1355 static void init_program(struct r300_fragment_program *rp)
1356 {
1357 struct r300_pfs_compile_state *cs = NULL;
1358 struct fragment_program *mp = &rp->mesa_program;
1359 struct prog_instruction *fpi;
1360 GLuint InputsRead = mp->Base.InputsRead;
1361 GLuint temps_used = 0; /* for rp->temps[] */
1362 int i,j;
1363
1364 /* New compile, reset tracking data */
1365 rp->translated = GL_FALSE;
1366 rp->error = GL_FALSE;
1367 rp->cs = cs = &(R300_CONTEXT(rp->ctx)->state.pfs_compile);
1368 rp->tex.length = 0;
1369 rp->cur_node = 0;
1370 rp->first_node_has_tex = 0;
1371 rp->const_nr = 0;
1372 rp->param_nr = 0;
1373 rp->params_uptodate = GL_FALSE;
1374 rp->max_temp_idx = 0;
1375 rp->node[0].alu_end = -1;
1376 rp->node[0].tex_end = -1;
1377
1378 _mesa_memset(cs, 0, sizeof(*rp->cs));
1379 for (i=0;i<PFS_MAX_ALU_INST;i++) {
1380 for (j=0;j<3;j++) {
1381 cs->slot[i].vsrc[j] = SRC_CONST;
1382 cs->slot[i].ssrc[j] = SRC_CONST;
1383 }
1384 }
1385
1386 /* Work out what temps the Mesa inputs correspond to, this must match
1387 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
1388 * configures itself based on the fragprog's InputsRead
1389 *
1390 * NOTE: this depends on get_hw_temp() allocating registers in order,
1391 * starting from register 0.
1392 */
1393
1394 /* Texcoords come first */
1395 for (i=0;i<rp->ctx->Const.MaxTextureUnits;i++) {
1396 if (InputsRead & (FRAG_BIT_TEX0 << i)) {
1397 cs->inputs[FRAG_ATTRIB_TEX0+i].refcount = 0;
1398 cs->inputs[FRAG_ATTRIB_TEX0+i].reg = get_hw_temp(rp);
1399 }
1400 }
1401 InputsRead &= ~FRAG_BITS_TEX_ANY;
1402
1403 /* Then primary colour */
1404 if (InputsRead & FRAG_BIT_COL0) {
1405 cs->inputs[FRAG_ATTRIB_COL0].refcount = 0;
1406 cs->inputs[FRAG_ATTRIB_COL0].reg = get_hw_temp(rp);
1407 }
1408 InputsRead &= ~FRAG_BIT_COL0;
1409
1410 /* Secondary color */
1411 if (InputsRead & FRAG_BIT_COL1) {
1412 cs->inputs[FRAG_ATTRIB_COL1].refcount = 0;
1413 cs->inputs[FRAG_ATTRIB_COL1].reg = get_hw_temp(rp);
1414 }
1415 InputsRead &= ~FRAG_BIT_COL1;
1416
1417 /* Anything else */
1418 if (InputsRead) {
1419 WARN_ONCE("Don't know how to handle inputs 0x%x\n",
1420 InputsRead);
1421 /* force read from hwreg 0 for now */
1422 for (i=0;i<32;i++)
1423 if (InputsRead & (1<<i)) cs->inputs[i].reg = 0;
1424 }
1425
1426 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
1427 * That way, we can free up the reg when it's no longer needed
1428 */
1429 if (!mp->Base.Instructions) {
1430 ERROR("No instructions found in program\n");
1431 return;
1432 }
1433
1434 for (fpi=mp->Base.Instructions;fpi->Opcode != OPCODE_END; fpi++) {
1435 int idx;
1436
1437 for (i=0;i<3;i++) {
1438 idx = fpi->SrcReg[i].Index;
1439 switch (fpi->SrcReg[i].File) {
1440 case PROGRAM_TEMPORARY:
1441 if (!(temps_used & (1<<idx))) {
1442 cs->temps[idx].reg = -1;
1443 cs->temps[idx].refcount = 1;
1444 temps_used |= (1 << idx);
1445 } else
1446 cs->temps[idx].refcount++;
1447 break;
1448 case PROGRAM_INPUT:
1449 cs->inputs[idx].refcount++;
1450 break;
1451 default: break;
1452 }
1453 }
1454
1455 idx = fpi->DstReg.Index;
1456 if (fpi->DstReg.File == PROGRAM_TEMPORARY) {
1457 if (!(temps_used & (1<<idx))) {
1458 cs->temps[idx].reg = -1;
1459 cs->temps[idx].refcount = 1;
1460 temps_used |= (1 << idx);
1461 } else
1462 cs->temps[idx].refcount++;
1463 }
1464 }
1465 cs->temp_in_use = temps_used;
1466 }
1467
1468 static void update_params(struct r300_fragment_program *rp)
1469 {
1470 struct fragment_program *mp = &rp->mesa_program;
1471 int i;
1472
1473 /* Ask Mesa nicely to fill in ParameterValues for us */
1474 if (rp->param_nr)
1475 _mesa_load_state_parameters(rp->ctx, mp->Base.Parameters);
1476
1477 for (i=0;i<rp->param_nr;i++)
1478 COPY_4V(rp->constant[rp->param[i].idx], rp->param[i].values);
1479
1480 rp->params_uptodate = GL_TRUE;
1481 }
1482
1483 void r300_translate_fragment_shader(struct r300_fragment_program *rp)
1484 {
1485 struct r300_pfs_compile_state *cs = NULL;
1486
1487 if (!rp->translated) {
1488
1489 init_program(rp);
1490 cs = rp->cs;
1491
1492 if (parse_program(rp) == GL_FALSE) {
1493 dump_program(rp);
1494 return;
1495 }
1496
1497 /* Finish off */
1498 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
1499 rp->node[rp->cur_node].alu_end =
1500 cs->v_pos - rp->node[rp->cur_node].alu_offset - 1;
1501 if (rp->node[rp->cur_node].tex_end < 0)
1502 rp->node[rp->cur_node].tex_end = 0;
1503 rp->alu_offset = 0;
1504 rp->alu_end = cs->v_pos - 1;
1505 rp->tex_offset = 0;
1506 rp->tex_end = rp->tex.length ? rp->tex.length - 1 : 0;
1507 assert(rp->node[rp->cur_node].alu_end >= 0);
1508 assert(rp->alu_end >= 0);
1509
1510 rp->translated = GL_TRUE;
1511 if (0) dump_program(rp);
1512 }
1513
1514 update_params(rp);
1515 }
1516
1517 /* just some random things... */
1518 static void dump_program(struct r300_fragment_program *rp)
1519 {
1520 int i;
1521 static int pc = 0;
1522
1523 fprintf(stderr, "pc=%d*************************************\n", pc++);
1524
1525 fprintf(stderr, "Mesa program:\n");
1526 fprintf(stderr, "-------------\n");
1527 _mesa_print_program(&rp->mesa_program.Base);
1528 fflush(stdout);
1529
1530 fprintf(stderr, "Hardware program\n");
1531 fprintf(stderr, "----------------\n");
1532
1533 fprintf(stderr, "tex:\n");
1534
1535 for(i=0;i<rp->tex.length;i++) {
1536 fprintf(stderr, "%08x\n", rp->tex.inst[i]);
1537 }
1538
1539 for (i=0;i<(rp->cur_node+1);i++) {
1540 fprintf(stderr, "NODE %d: alu_offset: %d, tex_offset: %d, "\
1541 "alu_end: %d, tex_end: %d\n", i,
1542 rp->node[i].alu_offset,
1543 rp->node[i].tex_offset,
1544 rp->node[i].alu_end,
1545 rp->node[i].tex_end);
1546 }
1547
1548 fprintf(stderr, "%08x\n",
1549 ((rp->tex_end << 16) | (R300_PFS_TEXI_0 >> 2)));
1550 for (i=0;i<=rp->tex_end;i++)
1551 fprintf(stderr, "%08x\n", rp->tex.inst[i]);
1552
1553 /* dump program in pretty_print_command_stream.tcl-readable format */
1554 fprintf(stderr, "%08x\n",
1555 ((rp->alu_end << 16) | (R300_PFS_INSTR0_0 >> 2)));
1556 for (i=0;i<=rp->alu_end;i++)
1557 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst0);
1558
1559 fprintf(stderr, "%08x\n",
1560 ((rp->alu_end << 16) | (R300_PFS_INSTR1_0 >> 2)));
1561 for (i=0;i<=rp->alu_end;i++)
1562 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst1);
1563
1564 fprintf(stderr, "%08x\n",
1565 ((rp->alu_end << 16) | (R300_PFS_INSTR2_0 >> 2)));
1566 for (i=0;i<=rp->alu_end;i++)
1567 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst2);
1568
1569 fprintf(stderr, "%08x\n",
1570 ((rp->alu_end << 16) | (R300_PFS_INSTR3_0 >> 2)));
1571 for (i=0;i<=rp->alu_end;i++)
1572 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst3);
1573
1574 fprintf(stderr, "00000000\n");
1575 }