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[mesa.git] / src / mesa / drivers / dri / r300 / r300_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /*
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 * Jerome Glisse <j.glisse@gmail.com>
32 */
33
34 /*TODO'S
35 *
36 * - COS/SIN/SCS instructions
37 * - Depth write, WPOS/FOGC inputs
38 * - FogOption
39 * - Verify results of opcodes for accuracy, I've only checked them
40 * in specific cases.
41 * - and more...
42 */
43
44 #include "glheader.h"
45 #include "macros.h"
46 #include "enums.h"
47
48 #include "program.h"
49 #include "program_instruction.h"
50 #include "r300_context.h"
51 #include "r300_fragprog.h"
52 #include "r300_reg.h"
53
54 /*
55 * Usefull macros and values
56 */
57 #define ERROR(fmt, args...) do { \
58 fprintf(stderr, "%s::%s(): " fmt "\n", \
59 __FILE__, __func__, ##args); \
60 rp->error = GL_TRUE; \
61 } while(0)
62
63 #define PFS_INVAL 0xFFFFFFFF
64 #define COMPILE_STATE struct r300_pfs_compile_state *cs = rp->cs
65
66 #define SWIZZLE_XYZ 0
67 #define SWIZZLE_XXX 1
68 #define SWIZZLE_YYY 2
69 #define SWIZZLE_ZZZ 3
70 #define SWIZZLE_WWW 4
71 #define SWIZZLE_YZX 5
72 #define SWIZZLE_ZXY 6
73 #define SWIZZLE_WZY 7
74 #define SWIZZLE_111 8
75 #define SWIZZLE_000 9
76 #define SWIZZLE_HHH 10
77
78 #define swizzle(r, x, y, z, w) do_swizzle(rp, r, \
79 ((SWIZZLE_##x<<0)| \
80 (SWIZZLE_##y<<3)| \
81 (SWIZZLE_##z<<6)| \
82 (SWIZZLE_##w<<9)), \
83 0)
84
85 #define REG_TYPE_INPUT 0
86 #define REG_TYPE_OUTPUT 1
87 #define REG_TYPE_TEMP 2
88 #define REG_TYPE_CONST 3
89
90 #define REG_TYPE_SHIFT 0
91 #define REG_INDEX_SHIFT 2
92 #define REG_VSWZ_SHIFT 8
93 #define REG_SSWZ_SHIFT 13
94 #define REG_NEGV_SHIFT 18
95 #define REG_NEGS_SHIFT 19
96 #define REG_ABS_SHIFT 20
97 #define REG_NO_USE_SHIFT 21
98 #define REG_VALID_SHIFT 22
99
100 #define REG_TYPE_MASK (0x03 << REG_TYPE_SHIFT)
101 #define REG_INDEX_MASK (0x3F << REG_INDEX_SHIFT)
102 #define REG_VSWZ_MASK (0x1F << REG_VSWZ_SHIFT)
103 #define REG_SSWZ_MASK (0x1F << REG_SSWZ_SHIFT)
104 #define REG_NEGV_MASK (0x01 << REG_NEGV_SHIFT)
105 #define REG_NEGS_MASK (0x01 << REG_NEGS_SHIFT)
106 #define REG_ABS_MASK (0x01 << REG_ABS_SHIFT)
107 #define REG_NO_USE_MASK (0x01 << REG_NO_USE_SHIFT)
108 #define REG_VALID_MASK (0x01 << REG_VALID_SHIFT)
109
110 #define REG(type, index, vswz, sswz, nouse, valid) \
111 (((type << REG_TYPE_SHIFT) & REG_TYPE_MASK) | \
112 ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK) | \
113 ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK) | \
114 ((valid << REG_VALID_SHIFT) & REG_VALID_MASK) | \
115 ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK) | \
116 ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK))
117 #define REG_GET_TYPE(reg) \
118 ((reg & REG_TYPE_MASK) >> REG_TYPE_SHIFT)
119 #define REG_GET_INDEX(reg) \
120 ((reg & REG_INDEX_MASK) >> REG_INDEX_SHIFT)
121 #define REG_GET_VSWZ(reg) \
122 ((reg & REG_VSWZ_MASK) >> REG_VSWZ_SHIFT)
123 #define REG_GET_SSWZ(reg) \
124 ((reg & REG_SSWZ_MASK) >> REG_SSWZ_SHIFT)
125 #define REG_GET_NO_USE(reg) \
126 ((reg & REG_NO_USE_MASK) >> REG_NO_USE_SHIFT)
127 #define REG_GET_VALID(reg) \
128 ((reg & REG_VALID_MASK) >> REG_VALID_SHIFT)
129 #define REG_SET_TYPE(reg, type) \
130 reg = ((reg & ~REG_TYPE_MASK) | \
131 ((type << REG_TYPE_SHIFT) & REG_TYPE_MASK))
132 #define REG_SET_INDEX(reg, index) \
133 reg = ((reg & ~REG_INDEX_MASK) | \
134 ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK))
135 #define REG_SET_VSWZ(reg, vswz) \
136 reg = ((reg & ~REG_VSWZ_MASK) | \
137 ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK))
138 #define REG_SET_SSWZ(reg, sswz) \
139 reg = ((reg & ~REG_SSWZ_MASK) | \
140 ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK))
141 #define REG_SET_NO_USE(reg, nouse) \
142 reg = ((reg & ~REG_NO_USE_MASK) | \
143 ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK))
144 #define REG_SET_VALID(reg, valid) \
145 reg = ((reg & ~REG_VALID_MASK) | \
146 ((valid << REG_VALID_SHIFT) & REG_VALID_MASK))
147 #define REG_ABS(reg) \
148 reg = (reg | REG_ABS_MASK)
149 #define REG_NEGV(reg) \
150 reg = (reg | REG_NEGV_MASK)
151 #define REG_NEGS(reg) \
152 reg = (reg | REG_NEGS_MASK)
153
154
155 /*
156 * Datas structures for fragment program generation
157 */
158
159 /* description of r300 native hw instructions */
160 static const struct {
161 const char *name;
162 int argc;
163 int v_op;
164 int s_op;
165 } r300_fpop[] = {
166 { "MAD", 3, R300_FPI0_OUTC_MAD, R300_FPI2_OUTA_MAD },
167 { "DP3", 2, R300_FPI0_OUTC_DP3, R300_FPI2_OUTA_DP4 },
168 { "DP4", 2, R300_FPI0_OUTC_DP4, R300_FPI2_OUTA_DP4 },
169 { "MIN", 2, R300_FPI0_OUTC_MIN, R300_FPI2_OUTA_MIN },
170 { "MAX", 2, R300_FPI0_OUTC_MAX, R300_FPI2_OUTA_MAX },
171 { "CMP", 3, R300_FPI0_OUTC_CMP, R300_FPI2_OUTA_CMP },
172 { "FRC", 1, R300_FPI0_OUTC_FRC, R300_FPI2_OUTA_FRC },
173 { "EX2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_EX2 },
174 { "LG2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_LG2 },
175 { "RCP", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RCP },
176 { "RSQ", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RSQ },
177 { "REPL_ALPHA", 1, R300_FPI0_OUTC_REPL_ALPHA, PFS_INVAL },
178 { "CMPH", 3, R300_FPI0_OUTC_CMPH, PFS_INVAL },
179 };
180
181
182 /* vector swizzles r300 can support natively, with a couple of
183 * cases we handle specially
184 *
185 * REG_VSWZ/REG_SSWZ is an index into this table
186 */
187 #define SLOT_VECTOR (1<<0)
188 #define SLOT_SCALAR (1<<3)
189 #define SLOT_BOTH (SLOT_VECTOR | SLOT_SCALAR)
190 #define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \
191 SWIZZLE_##y, \
192 SWIZZLE_##z, \
193 SWIZZLE_ZERO))
194 static const struct r300_pfs_swizzle {
195 GLuint hash; /* swizzle value this matches */
196 GLuint base; /* base value for hw swizzle */
197 GLuint stride; /* difference in base between arg0/1/2 */
198 GLuint flags;
199 } v_swiz[] = {
200 /* native swizzles */
201 { MAKE_SWZ3(X, Y, Z), R300_FPI0_ARGC_SRC0C_XYZ, 4, SLOT_VECTOR },
202 { MAKE_SWZ3(X, X, X), R300_FPI0_ARGC_SRC0C_XXX, 4, SLOT_VECTOR },
203 { MAKE_SWZ3(Y, Y, Y), R300_FPI0_ARGC_SRC0C_YYY, 4, SLOT_VECTOR },
204 { MAKE_SWZ3(Z, Z, Z), R300_FPI0_ARGC_SRC0C_ZZZ, 4, SLOT_VECTOR },
205 { MAKE_SWZ3(W, W, W), R300_FPI0_ARGC_SRC0A, 1, SLOT_SCALAR },
206 { MAKE_SWZ3(Y, Z, X), R300_FPI0_ARGC_SRC0C_YZX, 1, SLOT_VECTOR },
207 { MAKE_SWZ3(Z, X, Y), R300_FPI0_ARGC_SRC0C_ZXY, 1, SLOT_VECTOR },
208 { MAKE_SWZ3(W, Z, Y), R300_FPI0_ARGC_SRC0CA_WZY, 1, SLOT_BOTH },
209 { MAKE_SWZ3(ONE, ONE, ONE), R300_FPI0_ARGC_ONE, 0, 0},
210 { MAKE_SWZ3(ZERO, ZERO, ZERO), R300_FPI0_ARGC_ZERO, 0, 0},
211 { PFS_INVAL, R300_FPI0_ARGC_HALF, 0, 0},
212 { PFS_INVAL, 0, 0, 0},
213 };
214
215 /* used during matching of non-native swizzles */
216 #define SWZ_X_MASK (7 << 0)
217 #define SWZ_Y_MASK (7 << 3)
218 #define SWZ_Z_MASK (7 << 6)
219 #define SWZ_W_MASK (7 << 9)
220 static const struct {
221 GLuint hash; /* used to mask matching swizzle components */
222 int mask; /* actual outmask */
223 int count; /* count of components matched */
224 } s_mask[] = {
225 { SWZ_X_MASK|SWZ_Y_MASK|SWZ_Z_MASK, 1|2|4, 3},
226 { SWZ_X_MASK|SWZ_Y_MASK, 1|2, 2},
227 { SWZ_X_MASK|SWZ_Z_MASK, 1|4, 2},
228 { SWZ_Y_MASK|SWZ_Z_MASK, 2|4, 2},
229 { SWZ_X_MASK, 1, 1},
230 { SWZ_Y_MASK, 2, 1},
231 { SWZ_Z_MASK, 4, 1},
232 { PFS_INVAL, PFS_INVAL, PFS_INVAL}
233 };
234
235 /* mapping from SWIZZLE_* to r300 native values for scalar insns */
236 #define SWIZZLE_HALF 6
237 static const struct {
238 int base; /* hw value of swizzle */
239 int stride; /* difference between SRC0/1/2 */
240 GLuint flags;
241 } s_swiz[] = {
242 { R300_FPI2_ARGA_SRC0C_X, 3, SLOT_VECTOR },
243 { R300_FPI2_ARGA_SRC0C_Y, 3, SLOT_VECTOR },
244 { R300_FPI2_ARGA_SRC0C_Z, 3, SLOT_VECTOR },
245 { R300_FPI2_ARGA_SRC0A , 1, SLOT_SCALAR },
246 { R300_FPI2_ARGA_ZERO , 0, 0 },
247 { R300_FPI2_ARGA_ONE , 0, 0 },
248 { R300_FPI2_ARGA_HALF , 0, 0 }
249 };
250
251 /* boiler-plate reg, for convenience */
252 static const GLuint undef = REG(REG_TYPE_TEMP,
253 0,
254 SWIZZLE_XYZ,
255 SWIZZLE_W,
256 GL_FALSE,
257 GL_FALSE);
258
259 /* constant one source */
260 static const GLuint pfs_one = REG(REG_TYPE_TEMP,
261 0,
262 SWIZZLE_111,
263 SWIZZLE_ONE,
264 GL_FALSE,
265 GL_TRUE);
266
267 /* constant half source */
268 static const GLuint pfs_half = REG(REG_TYPE_TEMP,
269 0,
270 SWIZZLE_HHH,
271 SWIZZLE_HALF,
272 GL_FALSE,
273 GL_TRUE);
274
275 /* constant zero source */
276 static const GLuint pfs_zero = REG(REG_TYPE_TEMP,
277 0,
278 SWIZZLE_000,
279 SWIZZLE_ZERO,
280 GL_FALSE,
281 GL_TRUE);
282
283 /*
284 * Common functions prototypes
285 */
286 static void dump_program(struct r300_fragment_program *rp);
287 static void emit_arith(struct r300_fragment_program *rp, int op,
288 GLuint dest, int mask,
289 GLuint src0, GLuint src1, GLuint src2,
290 int flags);
291
292 /*
293 * Helper functions prototypes
294 */
295 static int get_hw_temp(struct r300_fragment_program *rp)
296 {
297 COMPILE_STATE;
298 int r = ffs(~cs->hwreg_in_use);
299 if (!r) {
300 ERROR("Out of hardware temps\n");
301 return 0;
302 }
303
304 cs->hwreg_in_use |= (1 << --r);
305 if (r > rp->max_temp_idx)
306 rp->max_temp_idx = r;
307
308 return r;
309 }
310
311 static int get_hw_temp_tex(struct r300_fragment_program *rp)
312 {
313 COMPILE_STATE;
314 int r;
315
316 r = ffs(~(cs->hwreg_in_use | cs->used_in_node));
317 if (!r)
318 return get_hw_temp(rp); /* Will cause an indirection */
319
320 cs->hwreg_in_use |= (1 << --r);
321 if (r > rp->max_temp_idx)
322 rp->max_temp_idx = r;
323
324 return r;
325 }
326
327 static void free_hw_temp(struct r300_fragment_program *rp, int idx)
328 {
329 COMPILE_STATE;
330 cs->hwreg_in_use &= ~(1<<idx);
331 }
332
333 static GLuint get_temp_reg(struct r300_fragment_program *rp)
334 {
335 COMPILE_STATE;
336 GLuint r = undef;
337 GLuint index;
338
339 index = ffs(~cs->temp_in_use);
340 if (!index) {
341 ERROR("Out of program temps\n");
342 return r;
343 }
344
345 cs->temp_in_use |= (1 << --index);
346 cs->temps[index].refcount = 0xFFFFFFFF;
347 cs->temps[index].reg = -1;
348
349 REG_SET_TYPE(r, REG_TYPE_TEMP);
350 REG_SET_INDEX(r, index);
351 REG_SET_VALID(r, GL_TRUE);
352 return r;
353 }
354
355 static GLuint get_temp_reg_tex(struct r300_fragment_program *rp)
356 {
357 COMPILE_STATE;
358 GLuint r = undef;
359 GLuint index;
360
361 index = ffs(~cs->temp_in_use);
362 if (!index) {
363 ERROR("Out of program temps\n");
364 return r;
365 }
366
367 cs->temp_in_use |= (1 << --index);
368 cs->temps[index].refcount = 0xFFFFFFFF;
369 cs->temps[index].reg = get_hw_temp_tex(rp);
370
371 REG_SET_TYPE(r, REG_TYPE_TEMP);
372 REG_SET_INDEX(r, index);
373 REG_SET_VALID(r, GL_TRUE);
374 return r;
375 }
376
377 static void free_temp(struct r300_fragment_program *rp, GLuint r)
378 {
379 COMPILE_STATE;
380 GLuint index = REG_GET_INDEX(r);
381
382 if (!(cs->temp_in_use & (1 << index)))
383 return;
384
385 if (REG_GET_TYPE(r) == REG_TYPE_TEMP) {
386 free_hw_temp(rp, cs->temps[index].reg);
387 cs->temps[index].reg = -1;
388 cs->temp_in_use &= ~(1 << index);
389 } else if (REG_GET_TYPE(r) == REG_TYPE_INPUT) {
390 free_hw_temp(rp, cs->inputs[index].reg);
391 cs->inputs[index].reg = -1;
392 }
393 }
394
395 static GLuint emit_param4fv(struct r300_fragment_program *rp,
396 GLfloat *values)
397 {
398 GLuint r = undef;
399 GLuint index;
400 int pidx;
401
402 pidx = rp->param_nr++;
403 index = rp->const_nr++;
404 if (pidx >= PFS_NUM_CONST_REGS || index >= PFS_NUM_CONST_REGS) {
405 ERROR("Out of const/param slots!\n");
406 return r;
407 }
408
409 rp->param[pidx].idx = index;
410 rp->param[pidx].values = values;
411 rp->params_uptodate = GL_FALSE;
412
413 REG_SET_TYPE(r, REG_TYPE_CONST);
414 REG_SET_INDEX(r, index);
415 REG_SET_VALID(r, GL_TRUE);
416 return r;
417 }
418
419 static GLuint emit_const4fv(struct r300_fragment_program *rp, GLfloat *cp)
420 {
421 GLuint r = undef;
422 GLuint index;
423
424 index = rp->const_nr++;
425 if (index >= PFS_NUM_CONST_REGS) {
426 ERROR("Out of hw constants!\n");
427 return r;
428 }
429
430 COPY_4V(rp->constant[index], cp);
431
432 REG_SET_TYPE(r, REG_TYPE_CONST);
433 REG_SET_INDEX(r, index);
434 REG_SET_VALID(r, GL_TRUE);
435 return r;
436 }
437
438 static inline GLuint negate(GLuint r)
439 {
440 REG_NEGS(r);
441 REG_NEGV(r);
442 return r;
443 }
444
445 /* Hack, to prevent clobbering sources used multiple times when
446 * emulating non-native instructions
447 */
448 static inline GLuint keep(GLuint r)
449 {
450 REG_SET_NO_USE(r, GL_TRUE);
451 return r;
452 }
453
454 static inline GLuint absolute(GLuint r)
455 {
456 REG_ABS(r);
457 return r;
458 }
459
460 static int swz_native(struct r300_fragment_program *rp,
461 GLuint src,
462 GLuint *r,
463 GLuint arbneg)
464 {
465 /* Native swizzle, handle negation */
466 src |= ((arbneg >> 3) & 1) << REG_NEGS_SHIFT;
467
468 if ((arbneg & 0x7) == 0x0) {
469 src = src & ~REG_NEGV_MASK;
470 *r = src;
471 } else if ((arbneg & 0x7) == 0x7) {
472 src |= REG_NEGV_MASK;
473 *r = src;
474 } else {
475 if (!REG_GET_VALID(*r))
476 *r = get_temp_reg(rp);
477 src |= REG_NEGV_MASK;
478 emit_arith(rp,
479 PFS_OP_MAD,
480 *r,
481 arbneg & 0x7,
482 keep(src),
483 pfs_one,
484 pfs_zero,
485 0);
486 src = src & ~REG_NEGV_MASK;
487 emit_arith(rp,
488 PFS_OP_MAD,
489 *r,
490 (arbneg ^ 0x7) | WRITEMASK_W,
491 src,
492 pfs_one,
493 pfs_zero,
494 0);
495 }
496
497 return 3;
498 }
499
500 static int swz_emit_partial(struct r300_fragment_program *rp,
501 GLuint src,
502 GLuint *r,
503 int mask,
504 int mc,
505 GLuint arbneg)
506 {
507 GLuint tmp;
508 GLuint wmask = 0;
509
510 if (!REG_GET_VALID(*r))
511 *r = get_temp_reg(rp);
512
513 /* A partial match, VSWZ/mask define what parts of the
514 * desired swizzle we match
515 */
516 if (mc + s_mask[mask].count == 3) {
517 wmask = WRITEMASK_W;
518 src |= ((arbneg >> 3) & 1) << REG_NEGS_SHIFT;
519 }
520
521 tmp = arbneg & s_mask[mask].mask;
522 if (tmp) {
523 tmp = tmp ^ s_mask[mask].mask;
524 if (tmp) {
525 emit_arith(rp,
526 PFS_OP_MAD,
527 *r,
528 arbneg & s_mask[mask].mask,
529 keep(src) | REG_NEGV_MASK,
530 pfs_one,
531 pfs_zero,
532 0);
533 if (!wmask) {
534 REG_SET_NO_USE(src, GL_TRUE);
535 } else {
536 REG_SET_NO_USE(src, GL_FALSE);
537 }
538 emit_arith(rp,
539 PFS_OP_MAD,
540 *r,
541 tmp | wmask,
542 src,
543 pfs_one,
544 pfs_zero,
545 0);
546 } else {
547 if (!wmask) {
548 REG_SET_NO_USE(src, GL_TRUE);
549 } else {
550 REG_SET_NO_USE(src, GL_FALSE);
551 }
552 emit_arith(rp,
553 PFS_OP_MAD,
554 *r,
555 (arbneg & s_mask[mask].mask) | wmask,
556 src | REG_NEGV_MASK,
557 pfs_one,
558 pfs_zero,
559 0);
560 }
561 } else {
562 if (!wmask) {
563 REG_SET_NO_USE(src, GL_TRUE);
564 } else {
565 REG_SET_NO_USE(src, GL_FALSE);
566 }
567 emit_arith(rp, PFS_OP_MAD,
568 *r,
569 s_mask[mask].mask | wmask,
570 src,
571 pfs_one,
572 pfs_zero,
573 0);
574 }
575
576 return s_mask[mask].count;
577 }
578
579 static GLuint do_swizzle(struct r300_fragment_program *rp,
580 GLuint src,
581 GLuint arbswz,
582 GLuint arbneg)
583 {
584 GLuint r = undef;
585 GLuint vswz;
586 int c_mask = 0;
587 int v_match = 0;
588
589 /* If swizzling from something without an XYZW native swizzle,
590 * emit result to a temp, and do new swizzle from the temp.
591 */
592 if (REG_GET_VSWZ(src) != SWIZZLE_XYZ ||
593 REG_GET_SSWZ(src) != SWIZZLE_W) {
594 GLuint temp = get_temp_reg(rp);
595 emit_arith(rp,
596 PFS_OP_MAD,
597 temp,
598 WRITEMASK_XYZW,
599 src,
600 pfs_one,
601 pfs_zero,
602 0);
603 src = temp;
604 }
605
606 /* set scalar swizzling */
607 REG_SET_SSWZ(src, GET_SWZ(arbswz, 3));
608
609 do {
610 vswz = REG_GET_VSWZ(src);
611 do {
612 int chash;
613
614 REG_SET_VSWZ(src, vswz);
615 chash = v_swiz[REG_GET_VSWZ(src)].hash &
616 s_mask[c_mask].hash;
617
618 if (chash == (arbswz & s_mask[c_mask].hash)) {
619 if (s_mask[c_mask].count == 3) {
620 v_match += swz_native(rp,
621 src,
622 &r,
623 arbneg);
624 } else {
625 v_match += swz_emit_partial(rp,
626 src,
627 &r,
628 c_mask,
629 v_match,
630 arbneg);
631 }
632
633 if (v_match == 3)
634 return r;
635
636 /* Fill with something invalid.. all 0's was
637 * wrong before, matched SWIZZLE_X. So all
638 * 1's will be okay for now
639 */
640 arbswz |= (PFS_INVAL & s_mask[c_mask].hash);
641 }
642 } while(v_swiz[++vswz].hash != PFS_INVAL);
643 REG_SET_VSWZ(src, SWIZZLE_XYZ);
644 } while (s_mask[++c_mask].hash != PFS_INVAL);
645
646 ERROR("should NEVER get here\n");
647 return r;
648 }
649
650 static GLuint t_src(struct r300_fragment_program *rp,
651 struct prog_src_register fpsrc)
652 {
653 GLuint r = undef;
654
655 switch (fpsrc.File) {
656 case PROGRAM_TEMPORARY:
657 REG_SET_INDEX(r, fpsrc.Index);
658 REG_SET_VALID(r, GL_TRUE);
659 REG_SET_TYPE(r, REG_TYPE_TEMP);
660 break;
661 case PROGRAM_INPUT:
662 REG_SET_INDEX(r, fpsrc.Index);
663 REG_SET_VALID(r, GL_TRUE);
664 REG_SET_TYPE(r, REG_TYPE_INPUT);
665 break;
666 case PROGRAM_LOCAL_PARAM:
667 r = emit_param4fv(rp,
668 rp->mesa_program.Base.LocalParams[fpsrc.Index]);
669 break;
670 case PROGRAM_ENV_PARAM:
671 r = emit_param4fv(rp,
672 rp->ctx->FragmentProgram.Parameters[fpsrc.Index]);
673 break;
674 case PROGRAM_STATE_VAR:
675 case PROGRAM_NAMED_PARAM:
676 r = emit_param4fv(rp,
677 rp->mesa_program.Base.Parameters->ParameterValues[fpsrc.Index]);
678 break;
679 default:
680 ERROR("unknown SrcReg->File %x\n", fpsrc.File);
681 return r;
682 }
683
684 /* no point swizzling ONE/ZERO/HALF constants... */
685 if (REG_GET_VSWZ(r) < SWIZZLE_111 || REG_GET_SSWZ(r) < SWIZZLE_ZERO)
686 r = do_swizzle(rp, r, fpsrc.Swizzle, fpsrc.NegateBase);
687 return r;
688 }
689
690 static GLuint t_scalar_src(struct r300_fragment_program *rp,
691 struct prog_src_register fpsrc)
692 {
693 struct prog_src_register src = fpsrc;
694 int sc = GET_SWZ(fpsrc.Swizzle, 0); /* X */
695
696 src.Swizzle = ((sc<<0)|(sc<<3)|(sc<<6)|(sc<<9));
697
698 return t_src(rp, src);
699 }
700
701 static GLuint t_dst(struct r300_fragment_program *rp,
702 struct prog_dst_register dest)
703 {
704 GLuint r = undef;
705
706 switch (dest.File) {
707 case PROGRAM_TEMPORARY:
708 REG_SET_INDEX(r, dest.Index);
709 REG_SET_VALID(r, GL_TRUE);
710 REG_SET_TYPE(r, REG_TYPE_TEMP);
711 return r;
712 case PROGRAM_OUTPUT:
713 REG_SET_TYPE(r, REG_TYPE_OUTPUT);
714 switch (dest.Index) {
715 case FRAG_RESULT_COLR:
716 case FRAG_RESULT_DEPR:
717 REG_SET_INDEX(r, dest.Index);
718 REG_SET_VALID(r, GL_TRUE);
719 return r;
720 default:
721 ERROR("Bad DstReg->Index 0x%x\n", dest.Index);
722 return r;
723 }
724 default:
725 ERROR("Bad DstReg->File 0x%x\n", dest.File);
726 return r;
727 }
728 }
729
730 static int t_hw_src(struct r300_fragment_program *rp,
731 GLuint src,
732 GLboolean tex)
733 {
734 COMPILE_STATE;
735 int idx;
736 int index = REG_GET_INDEX(src);
737
738 switch(REG_GET_TYPE(src)) {
739 case REG_TYPE_TEMP:
740 /* NOTE: if reg==-1 here, a source is being read that
741 * hasn't been written to. Undefined results
742 */
743 if (cs->temps[index].reg == -1)
744 cs->temps[index].reg = get_hw_temp(rp);
745
746 idx = cs->temps[index].reg;
747
748 if (!REG_GET_NO_USE(src) &&
749 (--cs->temps[index].refcount == 0))
750 free_temp(rp, src);
751 break;
752 case REG_TYPE_INPUT:
753 idx = cs->inputs[index].reg;
754
755 if (!REG_GET_NO_USE(src) &&
756 (--cs->inputs[index].refcount == 0))
757 free_hw_temp(rp, cs->inputs[index].reg);
758 break;
759 case REG_TYPE_CONST:
760 return (index | SRC_CONST);
761 default:
762 ERROR("Invalid type for source reg\n");
763 return (0 | SRC_CONST);
764 }
765
766 if (!tex)
767 cs->used_in_node |= (1 << idx);
768
769 return idx;
770 }
771
772 static int t_hw_dst(struct r300_fragment_program *rp,
773 GLuint dest,
774 GLboolean tex)
775 {
776 COMPILE_STATE;
777 int idx;
778 GLuint index = REG_GET_INDEX(dest);
779 assert(REG_GET_VALID(dest));
780
781 switch(REG_GET_TYPE(dest)) {
782 case REG_TYPE_TEMP:
783 if (cs->temps[REG_GET_INDEX(dest)].reg == -1) {
784 if (!tex) {
785 cs->temps[index].reg = get_hw_temp(rp);
786 } else {
787 cs->temps[index].reg = get_hw_temp_tex(rp);
788 }
789 }
790 idx = cs->temps[index].reg;
791
792 if (!REG_GET_NO_USE(dest) &&
793 (--cs->temps[index].refcount == 0))
794 free_temp(rp, dest);
795
796 cs->dest_in_node |= (1 << idx);
797 cs->used_in_node |= (1 << idx);
798 break;
799 case REG_TYPE_OUTPUT:
800 switch(index) {
801 case FRAG_RESULT_COLR:
802 rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_COLOR;
803 break;
804 case FRAG_RESULT_DEPR:
805 rp->node[rp->cur_node].flags |= R300_PFS_NODE_OUTPUT_DEPTH;
806 break;
807 }
808 return index;
809 break;
810 default:
811 ERROR("invalid dest reg type %d\n", REG_GET_TYPE(dest));
812 return 0;
813 }
814
815 return idx;
816 }
817
818 static void emit_nop(struct r300_fragment_program *rp,
819 GLuint mask,
820 GLboolean sync)
821 {
822 COMPILE_STATE;
823
824 if (sync)
825 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
826
827 if (mask & WRITEMASK_XYZ) {
828 rp->alu.inst[cs->v_pos].inst0 = NOP_INST0;
829 rp->alu.inst[cs->v_pos].inst1 = NOP_INST1;
830 cs->v_pos++;
831 }
832
833 if (mask & WRITEMASK_W) {
834 rp->alu.inst[cs->s_pos].inst2 = NOP_INST2;
835 rp->alu.inst[cs->s_pos].inst3 = NOP_INST3;
836 cs->s_pos++;
837 }
838 }
839
840 static void emit_tex(struct r300_fragment_program *rp,
841 struct prog_instruction *fpi,
842 int opcode)
843 {
844 COMPILE_STATE;
845 GLuint coord = t_src(rp, fpi->SrcReg[0]);
846 GLuint dest = undef, rdest = undef;
847 GLuint din = cs->dest_in_node, uin = cs->used_in_node;
848 int unit = fpi->TexSrcUnit;
849 int hwsrc, hwdest;
850
851 /* Resolve source/dest to hardware registers */
852 hwsrc = t_hw_src(rp, coord, GL_TRUE);
853 if (opcode != R300_FPITX_OP_KIL) {
854 dest = t_dst(rp, fpi->DstReg);
855
856 /* r300 doesn't seem to be able to do TEX->output reg */
857 if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) {
858 rdest = dest;
859 dest = get_temp_reg_tex(rp);
860 }
861 hwdest = t_hw_dst(rp, dest, GL_TRUE);
862
863 /* Use a temp that hasn't been used in this node, rather
864 * than causing an indirection
865 */
866 if (uin & (1 << hwdest)) {
867 free_hw_temp(rp, hwdest);
868 hwdest = get_hw_temp_tex(rp);
869 cs->temps[REG_GET_INDEX(dest)].reg = hwdest;
870 }
871 } else {
872 hwdest = 0;
873 unit = 0;
874 }
875
876 /* Indirection if source has been written in this node, or if the
877 * dest has been read/written in this node
878 */
879 if ((REG_GET_TYPE(coord) != REG_TYPE_CONST &&
880 (din & (1<<hwsrc))) || (uin & (1<<hwdest))) {
881
882 /* Finish off current node */
883 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
884 if (rp->node[rp->cur_node].alu_offset == cs->v_pos) {
885 /* No alu instructions in the node? Emit a NOP. */
886 emit_nop(rp, WRITEMASK_XYZW, GL_TRUE);
887 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
888 }
889
890 rp->node[rp->cur_node].alu_end =
891 cs->v_pos - rp->node[rp->cur_node].alu_offset - 1;
892 assert(rp->node[rp->cur_node].alu_end >= 0);
893
894 if (++rp->cur_node >= PFS_MAX_TEX_INDIRECT) {
895 ERROR("too many levels of texture indirection\n");
896 return;
897 }
898
899 /* Start new node */
900 rp->node[rp->cur_node].tex_offset = rp->tex.length;
901 rp->node[rp->cur_node].alu_offset = cs->v_pos;
902 rp->node[rp->cur_node].tex_end = -1;
903 rp->node[rp->cur_node].alu_end = -1;
904 rp->node[rp->cur_node].flags = 0;
905 cs->used_in_node = 0;
906 cs->dest_in_node = 0;
907 }
908
909 if (rp->cur_node == 0)
910 rp->first_node_has_tex = 1;
911
912 rp->tex.inst[rp->tex.length++] = 0
913 | (hwsrc << R300_FPITX_SRC_SHIFT)
914 | (hwdest << R300_FPITX_DST_SHIFT)
915 | (unit << R300_FPITX_IMAGE_SHIFT)
916 /* not entirely sure about this */
917 | (opcode << R300_FPITX_OPCODE_SHIFT);
918
919 cs->dest_in_node |= (1 << hwdest);
920 if (REG_GET_TYPE(coord) != REG_TYPE_CONST)
921 cs->used_in_node |= (1 << hwsrc);
922
923 rp->node[rp->cur_node].tex_end++;
924
925 /* Copy from temp to output if needed */
926 if (REG_GET_VALID(rdest)) {
927 emit_arith(rp, PFS_OP_MAD, rdest, WRITEMASK_XYZW, dest,
928 pfs_one, pfs_zero, 0);
929 free_temp(rp, dest);
930 }
931 }
932
933 /* Add sources to FPI1/FPI3 lists. If source is already on list,
934 * reuse the index instead of wasting a source.
935 */
936 static int add_src(struct r300_fragment_program *rp,
937 int reg,
938 int pos,
939 int srcmask)
940 {
941 COMPILE_STATE;
942 int csm, i;
943
944 /* Look for matches */
945 for (i=0,csm=srcmask; i<3; i++,csm=csm<<1) {
946 /* If sources have been allocated in this position(s)... */
947 if ((cs->slot[pos].umask & csm) == csm) {
948 /* ... and the register number(s) match, re-use the
949 source */
950 if (srcmask == SLOT_VECTOR &&
951 cs->slot[pos].vsrc[i] == reg)
952 return i;
953 if (srcmask == SLOT_SCALAR &&
954 cs->slot[pos].ssrc[i] == reg)
955 return i;
956 if (srcmask == SLOT_BOTH &&
957 cs->slot[pos].vsrc[i] == reg &&
958 cs->slot[pos].ssrc[i] == reg)
959 return i;
960 }
961 }
962
963 /* Look for free spaces */
964 for (i=0,csm=srcmask; i<3; i++,csm=csm<<1) {
965 /* If the position(s) haven't been allocated */
966 if ((cs->slot[pos].umask & csm) == 0) {
967 cs->slot[pos].umask |= csm;
968
969 if (srcmask & SLOT_VECTOR)
970 cs->slot[pos].vsrc[i] = reg;
971 if (srcmask & SLOT_SCALAR)
972 cs->slot[pos].ssrc[i] = reg;
973 return i;
974 }
975 }
976
977 //ERROR("Failed to allocate sources in FPI1/FPI3!\n");
978 return 0;
979 }
980
981 /* Determine whether or not to position opcode in the same ALU slot for both
982 * vector and scalar portions of an instruction.
983 *
984 * It's not necessary to force the first case, but it makes disassembled
985 * shaders easier to read.
986 */
987 static GLboolean force_same_slot(int vop,
988 int sop,
989 GLboolean emit_vop,
990 GLboolean emit_sop,
991 int argc,
992 GLuint *src)
993 {
994 int i;
995
996 if (emit_vop && emit_sop)
997 return GL_TRUE;
998
999 if (emit_vop && vop == R300_FPI0_OUTC_REPL_ALPHA)
1000 return GL_TRUE;
1001
1002 if (emit_vop) {
1003 for (i=0;i<argc;i++)
1004 if (REG_GET_VSWZ(src[i]) == SWIZZLE_WZY)
1005 return GL_TRUE;
1006 }
1007
1008 return GL_FALSE;
1009 }
1010
1011 static void emit_arith(struct r300_fragment_program *rp,
1012 int op,
1013 GLuint dest,
1014 int mask,
1015 GLuint src0,
1016 GLuint src1,
1017 GLuint src2,
1018 int flags)
1019 {
1020 COMPILE_STATE;
1021 GLuint src[3] = { src0, src1, src2 };
1022 int hwsrc[3], sswz[3], vswz[3];
1023 int hwdest;
1024 GLboolean emit_vop = GL_FALSE, emit_sop = GL_FALSE;
1025 int vop, sop, argc;
1026 int vpos, spos;
1027 int i;
1028
1029 vop = r300_fpop[op].v_op;
1030 sop = r300_fpop[op].s_op;
1031 argc = r300_fpop[op].argc;
1032
1033 if ((mask & WRITEMASK_XYZ) || vop == R300_FPI0_OUTC_DP3)
1034 emit_vop = GL_TRUE;
1035 if ((mask & WRITEMASK_W) || vop == R300_FPI0_OUTC_REPL_ALPHA)
1036 emit_sop = GL_TRUE;
1037
1038 if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT &&
1039 REG_GET_INDEX(dest) == FRAG_RESULT_DEPR)
1040 emit_vop = GL_FALSE;
1041
1042 if (force_same_slot(vop, sop, emit_vop, emit_sop, argc, src)) {
1043 vpos = spos = MAX2(cs->v_pos, cs->s_pos);
1044 } else {
1045 vpos = cs->v_pos;
1046 spos = cs->s_pos;
1047 /* Here is where we'd decide on where a safe place is to
1048 * combine this instruction with a previous one.
1049 *
1050 * This is extremely simple for now.. if a source depends
1051 * on the opposite stream, force the same instruction.
1052 */
1053 for (i=0;i<3;i++) {
1054 if (emit_vop &&
1055 (v_swiz[REG_GET_VSWZ(src[i])].flags & SLOT_SCALAR)) {
1056 vpos = spos = MAX2(vpos, spos);
1057 break;
1058 }
1059 if (emit_sop &&
1060 (s_swiz[REG_GET_VSWZ(src[i])].flags & SLOT_VECTOR)) {
1061 vpos = spos = MAX2(vpos, spos);
1062 break;
1063 }
1064 }
1065 }
1066
1067 /* - Convert src->hwsrc, record for FPI1/FPI3
1068 * - Determine ARG parts of FPI0/FPI2, unused args are filled
1069 * with ARG_ZERO.
1070 */
1071 for (i=0;i<3;i++) {
1072 int srcpos;
1073
1074 if (i >= argc) {
1075 vswz[i] = R300_FPI0_ARGC_ZERO;
1076 sswz[i] = R300_FPI2_ARGA_ZERO;
1077 continue;
1078 }
1079
1080 hwsrc[i] = t_hw_src(rp, src[i], GL_FALSE);
1081
1082 if (emit_vop && vop != R300_FPI0_OUTC_REPL_ALPHA) {
1083 srcpos = add_src(rp, hwsrc[i], vpos,
1084 v_swiz[REG_GET_VSWZ(src[i])].flags);
1085 vswz[i] = (v_swiz[REG_GET_VSWZ(src[i])].base +
1086 (srcpos *
1087 v_swiz[REG_GET_VSWZ(src[i])].stride)) |
1088 ((src[i] & REG_NEGV_MASK) ? ARG_NEG : 0) |
1089 ((src[i] & REG_ABS_MASK) ? ARG_ABS : 0);
1090 } else vswz[i] = R300_FPI0_ARGC_ZERO;
1091
1092 if (emit_sop) {
1093 srcpos = add_src(rp, hwsrc[i], spos,
1094 s_swiz[REG_GET_SSWZ(src[i])].flags);
1095 sswz[i] = (s_swiz[REG_GET_SSWZ(src[i])].base +
1096 (srcpos *
1097 s_swiz[REG_GET_SSWZ(src[i])].stride)) |
1098 ((src[i] & REG_NEGS_MASK) ? ARG_NEG : 0) |
1099 ((src[i] & REG_ABS_MASK) ? ARG_ABS : 0);
1100 } else sswz[i] = R300_FPI2_ARGA_ZERO;
1101 }
1102 hwdest = t_hw_dst(rp, dest, GL_FALSE);
1103
1104 if (flags & PFS_FLAG_SAT) {
1105 vop |= R300_FPI0_OUTC_SAT;
1106 sop |= R300_FPI2_OUTA_SAT;
1107 }
1108
1109 /* Throw the pieces together and get FPI0/1 */
1110 rp->alu.inst[vpos].inst1 =
1111 ((cs->slot[vpos].vsrc[0] << R300_FPI1_SRC0C_SHIFT) |
1112 (cs->slot[vpos].vsrc[1] << R300_FPI1_SRC1C_SHIFT) |
1113 (cs->slot[vpos].vsrc[2] << R300_FPI1_SRC2C_SHIFT));
1114 if (emit_vop) {
1115 rp->alu.inst[vpos].inst0 = vop |
1116 (vswz[0] << R300_FPI0_ARG0C_SHIFT) |
1117 (vswz[1] << R300_FPI0_ARG1C_SHIFT) |
1118 (vswz[2] << R300_FPI0_ARG2C_SHIFT);
1119
1120 rp->alu.inst[vpos].inst1 |= hwdest << R300_FPI1_DSTC_SHIFT;
1121 if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) {
1122 if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) {
1123 rp->alu.inst[vpos].inst1 |=
1124 (mask & WRITEMASK_XYZ) << R300_FPI1_DSTC_OUTPUT_MASK_SHIFT;
1125 } else assert(0);
1126 } else {
1127 rp->alu.inst[vpos].inst1 |=
1128 (mask & WRITEMASK_XYZ) << R300_FPI1_DSTC_REG_MASK_SHIFT;
1129 }
1130 cs->v_pos = vpos+1;
1131 } else if (spos >= vpos)
1132 rp->alu.inst[spos].inst0 = NOP_INST0;
1133
1134 /* And now FPI2/3 */
1135 rp->alu.inst[spos].inst3 =
1136 ((cs->slot[spos].ssrc[0] << R300_FPI3_SRC0A_SHIFT) |
1137 (cs->slot[spos].ssrc[1] << R300_FPI3_SRC1A_SHIFT) |
1138 (cs->slot[spos].ssrc[2] << R300_FPI3_SRC2A_SHIFT));
1139 if (emit_sop) {
1140 rp->alu.inst[spos].inst2 = sop |
1141 sswz[0] << R300_FPI2_ARG0A_SHIFT |
1142 sswz[1] << R300_FPI2_ARG1A_SHIFT |
1143 sswz[2] << R300_FPI2_ARG2A_SHIFT;
1144
1145 if (mask & WRITEMASK_W) {
1146 if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) {
1147 if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) {
1148 rp->alu.inst[spos].inst3 |=
1149 (hwdest << R300_FPI3_DSTA_SHIFT) | R300_FPI3_DSTA_OUTPUT;
1150 } else if (REG_GET_INDEX(dest) == FRAG_RESULT_DEPR) {
1151 rp->alu.inst[spos].inst3 |= R300_FPI3_DSTA_DEPTH;
1152 } else assert(0);
1153 } else {
1154 rp->alu.inst[spos].inst3 |=
1155 (hwdest << R300_FPI3_DSTA_SHIFT) | R300_FPI3_DSTA_REG;
1156 }
1157 }
1158 cs->s_pos = spos+1;
1159 } else if (vpos >= spos)
1160 rp->alu.inst[vpos].inst2 = NOP_INST2;
1161
1162 return;
1163 }
1164
1165 #if 0
1166 static GLuint get_attrib(struct r300_fragment_program *rp, GLuint attr)
1167 {
1168 struct gl_fragment_program *mp = &rp->mesa_program;
1169 GLuint r = undef;
1170
1171 if (!(mp->Base.InputsRead & (1<<attr))) {
1172 ERROR("Attribute %d was not provided!\n", attr);
1173 return undef;
1174 }
1175
1176 REG_SET_TYPE(r, REG_TYPE_INPUT);
1177 REG_SET_INDEX(r, attr);
1178 REG_SET_VALID(r, GL_TRUE);
1179 return r;
1180 }
1181 #endif
1182
1183 static GLboolean parse_program(struct r300_fragment_program *rp)
1184 {
1185 struct gl_fragment_program *mp = &rp->mesa_program;
1186 const struct prog_instruction *inst = mp->Base.Instructions;
1187 struct prog_instruction *fpi;
1188 GLuint src[3], dest, temp;
1189 GLuint cnst;
1190 int flags, mask = 0;
1191 GLfloat cnstv[4] = {0.0, 0.0, 0.0, 0.0};
1192
1193 if (!inst || inst[0].Opcode == OPCODE_END) {
1194 ERROR("empty program?\n");
1195 return GL_FALSE;
1196 }
1197
1198 for (fpi=mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
1199 if (fpi->SaturateMode == SATURATE_ZERO_ONE)
1200 flags = PFS_FLAG_SAT;
1201 else
1202 flags = 0;
1203
1204 if (fpi->Opcode != OPCODE_KIL) {
1205 dest = t_dst(rp, fpi->DstReg);
1206 mask = fpi->DstReg.WriteMask;
1207 }
1208
1209 switch (fpi->Opcode) {
1210 case OPCODE_ABS:
1211 src[0] = t_src(rp, fpi->SrcReg[0]);
1212 emit_arith(rp, PFS_OP_MAD, dest, mask,
1213 absolute(src[0]), pfs_one, pfs_zero,
1214 flags);
1215 break;
1216 case OPCODE_ADD:
1217 src[0] = t_src(rp, fpi->SrcReg[0]);
1218 src[1] = t_src(rp, fpi->SrcReg[1]);
1219 emit_arith(rp, PFS_OP_MAD, dest, mask,
1220 src[0], pfs_one, src[1],
1221 flags);
1222 break;
1223 case OPCODE_CMP:
1224 src[0] = t_src(rp, fpi->SrcReg[0]);
1225 src[1] = t_src(rp, fpi->SrcReg[1]);
1226 src[2] = t_src(rp, fpi->SrcReg[2]);
1227 /* ARB_f_p - if src0.c < 0.0 ? src1.c : src2.c
1228 * r300 - if src2.c < 0.0 ? src1.c : src0.c
1229 */
1230 emit_arith(rp, PFS_OP_CMP, dest, mask,
1231 src[2], src[1], src[0],
1232 flags);
1233 break;
1234 case OPCODE_COS:
1235 /*
1236 * cos using taylor serie:
1237 * cos(x) = 1 - x^2/2! + x^4/4! - x^6/6!
1238 */
1239 temp = get_temp_reg(rp);
1240 cnstv[0] = 0.5;
1241 cnstv[1] = 0.041666667;
1242 cnstv[2] = 0.001388889;
1243 cnstv[4] = 0.0;
1244 cnst = emit_const4fv(rp, cnstv);
1245 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1246
1247 emit_arith(rp, PFS_OP_MAD, temp,
1248 WRITEMASK_XYZ,
1249 src[0],
1250 src[0],
1251 pfs_zero,
1252 flags);
1253 emit_arith(rp, PFS_OP_MAD, temp,
1254 WRITEMASK_Y | WRITEMASK_Z,
1255 temp, temp,
1256 pfs_zero,
1257 flags);
1258 emit_arith(rp, PFS_OP_MAD, temp,
1259 WRITEMASK_Z,
1260 temp,
1261 swizzle(temp, X, X, X, W),
1262 pfs_zero,
1263 flags);
1264 emit_arith(rp, PFS_OP_MAD, temp,
1265 WRITEMASK_XYZ,
1266 temp, cnst,
1267 pfs_zero,
1268 flags);
1269 emit_arith(rp, PFS_OP_MAD, temp,
1270 WRITEMASK_X,
1271 pfs_one,
1272 pfs_one,
1273 negate(temp),
1274 flags);
1275 emit_arith(rp, PFS_OP_MAD, temp,
1276 WRITEMASK_X,
1277 temp,
1278 pfs_one,
1279 swizzle(temp, Y, Y, Y, W),
1280 flags);
1281 emit_arith(rp, PFS_OP_MAD, temp,
1282 WRITEMASK_X,
1283 temp,
1284 pfs_one,
1285 negate(swizzle(temp, Z, Z, Z, W)),
1286 flags);
1287 emit_arith(rp, PFS_OP_MAD, dest, mask,
1288 swizzle(temp, X, X, X, X),
1289 pfs_one,
1290 pfs_zero,
1291 flags);
1292 free_temp(rp, temp);
1293 break;
1294 case OPCODE_DP3:
1295 src[0] = t_src(rp, fpi->SrcReg[0]);
1296 src[1] = t_src(rp, fpi->SrcReg[1]);
1297 emit_arith(rp, PFS_OP_DP3, dest, mask,
1298 src[0], src[1], undef,
1299 flags);
1300 break;
1301 case OPCODE_DP4:
1302 src[0] = t_src(rp, fpi->SrcReg[0]);
1303 src[1] = t_src(rp, fpi->SrcReg[1]);
1304 emit_arith(rp, PFS_OP_DP4, dest, mask,
1305 src[0], src[1], undef,
1306 flags);
1307 break;
1308 case OPCODE_DPH:
1309 src[0] = t_src(rp, fpi->SrcReg[0]);
1310 src[1] = t_src(rp, fpi->SrcReg[1]);
1311 /* src0.xyz1 -> temp
1312 * DP4 dest, temp, src1
1313 */
1314 #if 0
1315 temp = get_temp_reg(rp);
1316 src[0].s_swz = SWIZZLE_ONE;
1317 emit_arith(rp, PFS_OP_MAD, temp, mask,
1318 src[0], pfs_one, pfs_zero,
1319 0);
1320 emit_arith(rp, PFS_OP_DP4, dest, mask,
1321 temp, src[1], undef,
1322 flags);
1323 free_temp(rp, temp);
1324 #else
1325 emit_arith(rp, PFS_OP_DP4, dest, mask,
1326 swizzle(src[0], X, Y, Z, ONE), src[1],
1327 undef, flags);
1328 #endif
1329 break;
1330 case OPCODE_DST:
1331 src[0] = t_src(rp, fpi->SrcReg[0]);
1332 src[1] = t_src(rp, fpi->SrcReg[1]);
1333 /* dest.y = src0.y * src1.y */
1334 if (mask & WRITEMASK_Y)
1335 emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Y,
1336 keep(src[0]), keep(src[1]),
1337 pfs_zero, flags);
1338 /* dest.z = src0.z */
1339 if (mask & WRITEMASK_Z)
1340 emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Z,
1341 src[0], pfs_one, pfs_zero, flags);
1342 /* result.x = 1.0
1343 * result.w = src1.w */
1344 if (mask & WRITEMASK_XW) {
1345 REG_SET_VSWZ(src[1], SWIZZLE_111); /*Cheat*/
1346 emit_arith(rp, PFS_OP_MAD, dest,
1347 mask & WRITEMASK_XW,
1348 src[1], pfs_one, pfs_zero,
1349 flags);
1350 }
1351 break;
1352 case OPCODE_EX2:
1353 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1354 emit_arith(rp, PFS_OP_EX2, dest, mask,
1355 src[0], undef, undef,
1356 flags);
1357 break;
1358 case OPCODE_FLR:
1359 src[0] = t_src(rp, fpi->SrcReg[0]);
1360 temp = get_temp_reg(rp);
1361 /* FRC temp, src0
1362 * MAD dest, src0, 1.0, -temp
1363 */
1364 emit_arith(rp, PFS_OP_FRC, temp, mask,
1365 keep(src[0]), undef, undef,
1366 0);
1367 emit_arith(rp, PFS_OP_MAD, dest, mask,
1368 src[0], pfs_one, negate(temp),
1369 flags);
1370 free_temp(rp, temp);
1371 break;
1372 case OPCODE_FRC:
1373 src[0] = t_src(rp, fpi->SrcReg[0]);
1374 emit_arith(rp, PFS_OP_FRC, dest, mask,
1375 src[0], undef, undef,
1376 flags);
1377 break;
1378 case OPCODE_KIL:
1379 emit_tex(rp, fpi, R300_FPITX_OP_KIL);
1380 break;
1381 case OPCODE_LG2:
1382 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1383 emit_arith(rp, PFS_OP_LG2, dest, mask,
1384 src[0], undef, undef,
1385 flags);
1386 break;
1387 case OPCODE_LIT:
1388 /* LIT
1389 * if (s.x < 0) t.x = 0; else t.x = s.x;
1390 * if (s.y < 0) t.y = 0; else t.y = s.y;
1391 * if (s.w > 128.0) t.w = 128.0; else t.w = s.w;
1392 * if (s.w < -128.0) t.w = -128.0; else t.w = s.w;
1393 * r.x = 1.0
1394 * if (t.x > 0) r.y = pow(t.y, t.w); else r.y = 0;
1395 * Also r.y = 0 if t.y < 0
1396 * For the t.x > 0 FGLRX use the CMPH opcode which
1397 * change the compare to (t.x + 0.5) > 0.5 we may
1398 * save one instruction by doing CMP -t.x
1399 */
1400 cnstv[0] = cnstv[1] = cnstv[2] = cnstv[4] = 0.50001;
1401 src[0] = t_src(rp, fpi->SrcReg[0]);
1402 temp = get_temp_reg(rp);
1403 cnst = emit_const4fv(rp, cnstv);
1404 emit_arith(rp, PFS_OP_CMP, temp,
1405 WRITEMASK_X | WRITEMASK_Y,
1406 src[0], pfs_zero, src[0], flags);
1407 emit_arith(rp, PFS_OP_MIN, temp, WRITEMASK_Z,
1408 swizzle(keep(src[0]), W, W, W, W),
1409 cnst, undef, flags);
1410 emit_arith(rp, PFS_OP_LG2, temp, WRITEMASK_W,
1411 swizzle(temp, Y, Y, Y, Y),
1412 undef, undef, flags);
1413 emit_arith(rp, PFS_OP_MAX, temp, WRITEMASK_Z,
1414 temp, negate(cnst), undef, flags);
1415 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_W,
1416 temp, swizzle(temp, Z, Z, Z, Z),
1417 pfs_zero, flags);
1418 emit_arith(rp, PFS_OP_EX2, temp, WRITEMASK_W,
1419 temp, undef, undef, flags);
1420 emit_arith(rp, PFS_OP_MAD, dest, WRITEMASK_Y,
1421 swizzle(keep(temp), X, X, X, X),
1422 pfs_one, pfs_zero, flags);
1423 #if 0
1424 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X,
1425 temp, pfs_one, pfs_half, flags);
1426 emit_arith(rp, PFS_OP_CMPH, temp, WRITEMASK_Z,
1427 swizzle(keep(temp), W, W, W, W),
1428 pfs_zero, swizzle(keep(temp), X, X, X, X),
1429 flags);
1430 #else
1431 emit_arith(rp, PFS_OP_CMP, temp, WRITEMASK_Z,
1432 pfs_zero,
1433 swizzle(keep(temp), W, W, W, W),
1434 negate(swizzle(keep(temp), X, X, X, X)),
1435 flags);
1436 #endif
1437 emit_arith(rp, PFS_OP_CMP, dest, WRITEMASK_Z,
1438 pfs_zero, temp,
1439 negate(swizzle(keep(temp), Y, Y, Y, Y)),
1440 flags);
1441 emit_arith(rp, PFS_OP_MAD, dest,
1442 WRITEMASK_X | WRITEMASK_W,
1443 pfs_one,
1444 pfs_one,
1445 pfs_zero,
1446 flags);
1447 free_temp(rp, temp);
1448 break;
1449 case OPCODE_LRP:
1450 src[0] = t_src(rp, fpi->SrcReg[0]);
1451 src[1] = t_src(rp, fpi->SrcReg[1]);
1452 src[2] = t_src(rp, fpi->SrcReg[2]);
1453 /* result = tmp0tmp1 + (1 - tmp0)tmp2
1454 * = tmp0tmp1 + tmp2 + (-tmp0)tmp2
1455 * MAD temp, -tmp0, tmp2, tmp2
1456 * MAD result, tmp0, tmp1, temp
1457 */
1458 temp = get_temp_reg(rp);
1459 emit_arith(rp, PFS_OP_MAD, temp, mask,
1460 negate(keep(src[0])), keep(src[2]), src[2],
1461 0);
1462 emit_arith(rp, PFS_OP_MAD, dest, mask,
1463 src[0], src[1], temp,
1464 flags);
1465 free_temp(rp, temp);
1466 break;
1467 case OPCODE_MAD:
1468 src[0] = t_src(rp, fpi->SrcReg[0]);
1469 src[1] = t_src(rp, fpi->SrcReg[1]);
1470 src[2] = t_src(rp, fpi->SrcReg[2]);
1471 emit_arith(rp, PFS_OP_MAD, dest, mask,
1472 src[0], src[1], src[2],
1473 flags);
1474 break;
1475 case OPCODE_MAX:
1476 src[0] = t_src(rp, fpi->SrcReg[0]);
1477 src[1] = t_src(rp, fpi->SrcReg[1]);
1478 emit_arith(rp, PFS_OP_MAX, dest, mask,
1479 src[0], src[1], undef,
1480 flags);
1481 break;
1482 case OPCODE_MIN:
1483 src[0] = t_src(rp, fpi->SrcReg[0]);
1484 src[1] = t_src(rp, fpi->SrcReg[1]);
1485 emit_arith(rp, PFS_OP_MIN, dest, mask,
1486 src[0], src[1], undef,
1487 flags);
1488 break;
1489 case OPCODE_MOV:
1490 case OPCODE_SWZ:
1491 src[0] = t_src(rp, fpi->SrcReg[0]);
1492 emit_arith(rp, PFS_OP_MAD, dest, mask,
1493 src[0], pfs_one, pfs_zero,
1494 flags);
1495 break;
1496 case OPCODE_MUL:
1497 src[0] = t_src(rp, fpi->SrcReg[0]);
1498 src[1] = t_src(rp, fpi->SrcReg[1]);
1499 emit_arith(rp, PFS_OP_MAD, dest, mask,
1500 src[0], src[1], pfs_zero,
1501 flags);
1502 break;
1503 case OPCODE_POW:
1504 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1505 src[1] = t_scalar_src(rp, fpi->SrcReg[1]);
1506 temp = get_temp_reg(rp);
1507 emit_arith(rp, PFS_OP_LG2, temp, WRITEMASK_W,
1508 src[0], undef, undef,
1509 0);
1510 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_W,
1511 temp, src[1], pfs_zero,
1512 0);
1513 emit_arith(rp, PFS_OP_EX2, dest, fpi->DstReg.WriteMask,
1514 temp, undef, undef,
1515 0);
1516 free_temp(rp, temp);
1517 break;
1518 case OPCODE_RCP:
1519 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1520 emit_arith(rp, PFS_OP_RCP, dest, mask,
1521 src[0], undef, undef,
1522 flags);
1523 break;
1524 case OPCODE_RSQ:
1525 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1526 emit_arith(rp, PFS_OP_RSQ, dest, mask,
1527 absolute(src[0]), pfs_zero, pfs_zero,
1528 flags);
1529 break;
1530 case OPCODE_SCS:
1531 ERROR("SCS not implemented\n");
1532 break;
1533 case OPCODE_SGE:
1534 src[0] = t_src(rp, fpi->SrcReg[0]);
1535 src[1] = t_src(rp, fpi->SrcReg[1]);
1536 temp = get_temp_reg(rp);
1537 /* temp = src0 - src1
1538 * dest.c = (temp.c < 0.0) ? 0 : 1
1539 */
1540 emit_arith(rp, PFS_OP_MAD, temp, mask,
1541 src[0], pfs_one, negate(src[1]),
1542 0);
1543 emit_arith(rp, PFS_OP_CMP, dest, mask,
1544 pfs_one, pfs_zero, temp,
1545 0);
1546 free_temp(rp, temp);
1547 break;
1548 case OPCODE_SIN:
1549 /*
1550 * sin using taylor serie:
1551 * sin(x) = x - x^3/3! + x^5/5! - x^7/7!
1552 */
1553 temp = get_temp_reg(rp);
1554 cnstv[0] = 0.333333333;
1555 cnstv[1] = 0.008333333;
1556 cnstv[2] = 0.000198413;
1557 cnstv[4] = 0.0;
1558 cnst = emit_const4fv(rp, cnstv);
1559 src[0] = t_scalar_src(rp, fpi->SrcReg[0]);
1560
1561 emit_arith(rp, PFS_OP_MAD, temp,
1562 WRITEMASK_XYZ,
1563 src[0],
1564 src[0],
1565 pfs_zero,
1566 flags);
1567 emit_arith(rp, PFS_OP_MAD, temp,
1568 WRITEMASK_Y | WRITEMASK_Z,
1569 temp, temp,
1570 pfs_zero,
1571 flags);
1572 emit_arith(rp, PFS_OP_MAD, temp,
1573 WRITEMASK_Z,
1574 temp,
1575 swizzle(temp, X, X, X, W),
1576 pfs_zero,
1577 flags);
1578 emit_arith(rp, PFS_OP_MAD, temp,
1579 WRITEMASK_XYZ,
1580 src[0],
1581 temp,
1582 pfs_zero,
1583 flags);
1584 emit_arith(rp, PFS_OP_MAD, temp,
1585 WRITEMASK_XYZ,
1586 temp, cnst,
1587 pfs_zero,
1588 flags);
1589 emit_arith(rp, PFS_OP_MAD, temp,
1590 WRITEMASK_X,
1591 src[0],
1592 pfs_one,
1593 negate(temp),
1594 flags);
1595 emit_arith(rp, PFS_OP_MAD, temp,
1596 WRITEMASK_X,
1597 temp,
1598 pfs_one,
1599 swizzle(temp, Y, Y, Y, W),
1600 flags);
1601 emit_arith(rp, PFS_OP_MAD, temp,
1602 WRITEMASK_X,
1603 temp,
1604 pfs_one,
1605 negate(swizzle(temp, Z, Z, Z, W)),
1606 flags);
1607 emit_arith(rp, PFS_OP_MAD, dest, mask,
1608 swizzle(temp, X, X, X, X),
1609 pfs_one,
1610 pfs_zero,
1611 flags);
1612 free_temp(rp, temp);
1613 break;
1614 case OPCODE_SLT:
1615 src[0] = t_src(rp, fpi->SrcReg[0]);
1616 src[1] = t_src(rp, fpi->SrcReg[1]);
1617 temp = get_temp_reg(rp);
1618 /* temp = src0 - src1
1619 * dest.c = (temp.c < 0.0) ? 1 : 0
1620 */
1621 emit_arith(rp, PFS_OP_MAD, temp, mask,
1622 src[0], pfs_one, negate(src[1]),
1623 0);
1624 emit_arith(rp, PFS_OP_CMP, dest, mask,
1625 pfs_zero, pfs_one, temp,
1626 0);
1627 free_temp(rp, temp);
1628 break;
1629 case OPCODE_SUB:
1630 src[0] = t_src(rp, fpi->SrcReg[0]);
1631 src[1] = t_src(rp, fpi->SrcReg[1]);
1632 emit_arith(rp, PFS_OP_MAD, dest, mask,
1633 src[0], pfs_one, negate(src[1]),
1634 flags);
1635 break;
1636 case OPCODE_TEX:
1637 emit_tex(rp, fpi, R300_FPITX_OP_TEX);
1638 break;
1639 case OPCODE_TXB:
1640 emit_tex(rp, fpi, R300_FPITX_OP_TXB);
1641 break;
1642 case OPCODE_TXP:
1643 emit_tex(rp, fpi, R300_FPITX_OP_TXP);
1644 break;
1645 case OPCODE_XPD: {
1646 src[0] = t_src(rp, fpi->SrcReg[0]);
1647 src[1] = t_src(rp, fpi->SrcReg[1]);
1648 temp = get_temp_reg(rp);
1649 /* temp = src0.zxy * src1.yzx */
1650 emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_XYZ,
1651 swizzle(keep(src[0]), Z, X, Y, W),
1652 swizzle(keep(src[1]), Y, Z, X, W),
1653 pfs_zero,
1654 0);
1655 /* dest.xyz = src0.yzx * src1.zxy - temp
1656 * dest.w = undefined
1657 * */
1658 emit_arith(rp, PFS_OP_MAD, dest, mask & WRITEMASK_XYZ,
1659 swizzle(src[0], Y, Z, X, W),
1660 swizzle(src[1], Z, X, Y, W),
1661 negate(temp),
1662 flags);
1663 /* cleanup */
1664 free_temp(rp, temp);
1665 break;
1666 }
1667 default:
1668 ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
1669 break;
1670 }
1671
1672 if (rp->error)
1673 return GL_FALSE;
1674
1675 }
1676
1677 return GL_TRUE;
1678 }
1679
1680 /* - Init structures
1681 * - Determine what hwregs each input corresponds to
1682 */
1683 static void init_program(struct r300_fragment_program *rp)
1684 {
1685 struct r300_pfs_compile_state *cs = NULL;
1686 struct gl_fragment_program *mp = &rp->mesa_program;
1687 struct prog_instruction *fpi;
1688 GLuint InputsRead = mp->Base.InputsRead;
1689 GLuint temps_used = 0; /* for rp->temps[] */
1690 int i,j;
1691
1692 /* New compile, reset tracking data */
1693 rp->translated = GL_FALSE;
1694 rp->error = GL_FALSE;
1695 rp->cs = cs = &(R300_CONTEXT(rp->ctx)->state.pfs_compile);
1696 rp->tex.length = 0;
1697 rp->cur_node = 0;
1698 rp->first_node_has_tex = 0;
1699 rp->const_nr = 0;
1700 rp->param_nr = 0;
1701 rp->params_uptodate = GL_FALSE;
1702 rp->max_temp_idx = 0;
1703 rp->node[0].alu_end = -1;
1704 rp->node[0].tex_end = -1;
1705
1706 _mesa_memset(cs, 0, sizeof(*rp->cs));
1707 for (i=0;i<PFS_MAX_ALU_INST;i++) {
1708 for (j=0;j<3;j++) {
1709 cs->slot[i].vsrc[j] = SRC_CONST;
1710 cs->slot[i].ssrc[j] = SRC_CONST;
1711 }
1712 }
1713
1714 /* Work out what temps the Mesa inputs correspond to, this must match
1715 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
1716 * configures itself based on the fragprog's InputsRead
1717 *
1718 * NOTE: this depends on get_hw_temp() allocating registers in order,
1719 * starting from register 0.
1720 */
1721
1722 /* Texcoords come first */
1723 for (i=0;i<rp->ctx->Const.MaxTextureUnits;i++) {
1724 if (InputsRead & (FRAG_BIT_TEX0 << i)) {
1725 cs->inputs[FRAG_ATTRIB_TEX0+i].refcount = 0;
1726 cs->inputs[FRAG_ATTRIB_TEX0+i].reg = get_hw_temp(rp);
1727 }
1728 }
1729 InputsRead &= ~FRAG_BITS_TEX_ANY;
1730
1731 /* fragment position treated as a texcoord */
1732 if (InputsRead & FRAG_BIT_WPOS) {
1733 cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0;
1734 cs->inputs[FRAG_ATTRIB_WPOS].reg = get_hw_temp(rp);
1735 }
1736 InputsRead &= ~FRAG_BIT_WPOS;
1737
1738 /* Then primary colour */
1739 if (InputsRead & FRAG_BIT_COL0) {
1740 cs->inputs[FRAG_ATTRIB_COL0].refcount = 0;
1741 cs->inputs[FRAG_ATTRIB_COL0].reg = get_hw_temp(rp);
1742 }
1743 InputsRead &= ~FRAG_BIT_COL0;
1744
1745 /* Secondary color */
1746 if (InputsRead & FRAG_BIT_COL1) {
1747 cs->inputs[FRAG_ATTRIB_COL1].refcount = 0;
1748 cs->inputs[FRAG_ATTRIB_COL1].reg = get_hw_temp(rp);
1749 }
1750 InputsRead &= ~FRAG_BIT_COL1;
1751
1752 /* Anything else */
1753 if (InputsRead) {
1754 WARN_ONCE("Don't know how to handle inputs 0x%x\n",
1755 InputsRead);
1756 /* force read from hwreg 0 for now */
1757 for (i=0;i<32;i++)
1758 if (InputsRead & (1<<i)) cs->inputs[i].reg = 0;
1759 }
1760
1761 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
1762 * That way, we can free up the reg when it's no longer needed
1763 */
1764 if (!mp->Base.Instructions) {
1765 ERROR("No instructions found in program\n");
1766 return;
1767 }
1768
1769 for (fpi=mp->Base.Instructions;fpi->Opcode != OPCODE_END; fpi++) {
1770 int idx;
1771
1772 for (i=0;i<3;i++) {
1773 idx = fpi->SrcReg[i].Index;
1774 switch (fpi->SrcReg[i].File) {
1775 case PROGRAM_TEMPORARY:
1776 if (!(temps_used & (1<<idx))) {
1777 cs->temps[idx].reg = -1;
1778 cs->temps[idx].refcount = 1;
1779 temps_used |= (1 << idx);
1780 } else
1781 cs->temps[idx].refcount++;
1782 break;
1783 case PROGRAM_INPUT:
1784 cs->inputs[idx].refcount++;
1785 break;
1786 default: break;
1787 }
1788 }
1789
1790 idx = fpi->DstReg.Index;
1791 if (fpi->DstReg.File == PROGRAM_TEMPORARY) {
1792 if (!(temps_used & (1<<idx))) {
1793 cs->temps[idx].reg = -1;
1794 cs->temps[idx].refcount = 1;
1795 temps_used |= (1 << idx);
1796 } else
1797 cs->temps[idx].refcount++;
1798 }
1799 }
1800 cs->temp_in_use = temps_used;
1801 }
1802
1803 static void update_params(struct r300_fragment_program *rp)
1804 {
1805 struct gl_fragment_program *mp = &rp->mesa_program;
1806 int i;
1807
1808 /* Ask Mesa nicely to fill in ParameterValues for us */
1809 if (rp->param_nr)
1810 _mesa_load_state_parameters(rp->ctx, mp->Base.Parameters);
1811
1812 for (i=0;i<rp->param_nr;i++)
1813 COPY_4V(rp->constant[rp->param[i].idx], rp->param[i].values);
1814
1815 rp->params_uptodate = GL_TRUE;
1816 }
1817
1818 void r300_translate_fragment_shader(struct r300_fragment_program *rp)
1819 {
1820 struct r300_pfs_compile_state *cs = NULL;
1821
1822 if (!rp->translated) {
1823
1824 init_program(rp);
1825 cs = rp->cs;
1826
1827 if (parse_program(rp) == GL_FALSE) {
1828 dump_program(rp);
1829 return;
1830 }
1831
1832 /* Finish off */
1833 cs->v_pos = cs->s_pos = MAX2(cs->v_pos, cs->s_pos);
1834 rp->node[rp->cur_node].alu_end =
1835 cs->v_pos - rp->node[rp->cur_node].alu_offset - 1;
1836 if (rp->node[rp->cur_node].tex_end < 0)
1837 rp->node[rp->cur_node].tex_end = 0;
1838 rp->alu_offset = 0;
1839 rp->alu_end = cs->v_pos - 1;
1840 rp->tex_offset = 0;
1841 rp->tex_end = rp->tex.length ? rp->tex.length - 1 : 0;
1842 assert(rp->node[rp->cur_node].alu_end >= 0);
1843 assert(rp->alu_end >= 0);
1844
1845 rp->translated = GL_TRUE;
1846 if (0) dump_program(rp);
1847 }
1848
1849 update_params(rp);
1850 }
1851
1852 /* just some random things... */
1853 static void dump_program(struct r300_fragment_program *rp)
1854 {
1855 int i;
1856 static int pc = 0;
1857
1858 fprintf(stderr, "pc=%d*************************************\n", pc++);
1859
1860 fprintf(stderr, "Mesa program:\n");
1861 fprintf(stderr, "-------------\n");
1862 _mesa_print_program(&rp->mesa_program.Base);
1863 fflush(stdout);
1864
1865 fprintf(stderr, "Hardware program\n");
1866 fprintf(stderr, "----------------\n");
1867
1868 fprintf(stderr, "tex:\n");
1869
1870 for(i=0;i<rp->tex.length;i++) {
1871 fprintf(stderr, "%08x\n", rp->tex.inst[i]);
1872 }
1873
1874 for (i=0;i<(rp->cur_node+1);i++) {
1875 fprintf(stderr, "NODE %d: alu_offset: %d, tex_offset: %d, "\
1876 "alu_end: %d, tex_end: %d\n", i,
1877 rp->node[i].alu_offset,
1878 rp->node[i].tex_offset,
1879 rp->node[i].alu_end,
1880 rp->node[i].tex_end);
1881 }
1882
1883 fprintf(stderr, "%08x\n",
1884 ((rp->tex_end << 16) | (R300_PFS_TEXI_0 >> 2)));
1885 for (i=0;i<=rp->tex_end;i++)
1886 fprintf(stderr, "%08x\n", rp->tex.inst[i]);
1887
1888 /* dump program in pretty_print_command_stream.tcl-readable format */
1889 fprintf(stderr, "%08x\n",
1890 ((rp->alu_end << 16) | (R300_PFS_INSTR0_0 >> 2)));
1891 for (i=0;i<=rp->alu_end;i++)
1892 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst0);
1893
1894 fprintf(stderr, "%08x\n",
1895 ((rp->alu_end << 16) | (R300_PFS_INSTR1_0 >> 2)));
1896 for (i=0;i<=rp->alu_end;i++)
1897 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst1);
1898
1899 fprintf(stderr, "%08x\n",
1900 ((rp->alu_end << 16) | (R300_PFS_INSTR2_0 >> 2)));
1901 for (i=0;i<=rp->alu_end;i++)
1902 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst2);
1903
1904 fprintf(stderr, "%08x\n",
1905 ((rp->alu_end << 16) | (R300_PFS_INSTR3_0 >> 2)));
1906 for (i=0;i<=rp->alu_end;i++)
1907 fprintf(stderr, "%08x\n", rp->alu.inst[i].inst3);
1908
1909 fprintf(stderr, "00000000\n");
1910 }