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[mesa.git] / src / mesa / drivers / dri / r300 / r300_ioctl.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Keith Whitwell <keith@tungstengraphics.com>
36 *
37 * \author Nicolai Haehnle <prefect_@gmx.net>
38 */
39
40 #include <sched.h>
41 #include <errno.h>
42
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
48
49 #include "radeon_common.h"
50 #include "radeon_lock.h"
51 #include "r300_context.h"
52 #include "r300_ioctl.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_state.h"
55 #include "r300_vertprog.h"
56 #include "radeon_reg.h"
57 #include "r300_emit.h"
58 #include "r300_context.h"
59
60 #include "vblank.h"
61
62 #define R200_3D_DRAW_IMMD_2 0xC0003500
63
64 #define CLEARBUFFER_COLOR 0x1
65 #define CLEARBUFFER_DEPTH 0x2
66 #define CLEARBUFFER_STENCIL 0x4
67
68 #if 1
69
70 /**
71 * Fragment program helper macros
72 */
73
74 /* Produce unshifted source selectors */
75 #define FP_TMP(idx) (idx)
76 #define FP_CONST(idx) ((idx) | (1 << 5))
77
78 /* Produce source/dest selector dword */
79 #define FP_SELC_MASK_NO 0
80 #define FP_SELC_MASK_X 1
81 #define FP_SELC_MASK_Y 2
82 #define FP_SELC_MASK_XY 3
83 #define FP_SELC_MASK_Z 4
84 #define FP_SELC_MASK_XZ 5
85 #define FP_SELC_MASK_YZ 6
86 #define FP_SELC_MASK_XYZ 7
87
88 #define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
89 (((destidx) << R300_ALU_DSTC_SHIFT) | \
90 (FP_SELC_MASK_##regmask << 23) | \
91 (FP_SELC_MASK_##outmask << 26) | \
92 ((src0) << R300_ALU_SRC0C_SHIFT) | \
93 ((src1) << R300_ALU_SRC1C_SHIFT) | \
94 ((src2) << R300_ALU_SRC2C_SHIFT))
95
96 #define FP_SELA_MASK_NO 0
97 #define FP_SELA_MASK_W 1
98
99 #define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
100 (((destidx) << R300_ALU_DSTA_SHIFT) | \
101 (FP_SELA_MASK_##regmask << 23) | \
102 (FP_SELA_MASK_##outmask << 24) | \
103 ((src0) << R300_ALU_SRC0A_SHIFT) | \
104 ((src1) << R300_ALU_SRC1A_SHIFT) | \
105 ((src2) << R300_ALU_SRC2A_SHIFT))
106
107 /* Produce unshifted argument selectors */
108 #define FP_ARGC(source) R300_ALU_ARGC_##source
109 #define FP_ARGA(source) R300_ALU_ARGA_##source
110 #define FP_ABS(arg) ((arg) | (1 << 6))
111 #define FP_NEG(arg) ((arg) ^ (1 << 5))
112
113 /* Produce instruction dword */
114 #define FP_INSTRC(opcode,arg0,arg1,arg2) \
115 (R300_ALU_OUTC_##opcode | \
116 ((arg0) << R300_ALU_ARG0C_SHIFT) | \
117 ((arg1) << R300_ALU_ARG1C_SHIFT) | \
118 ((arg2) << R300_ALU_ARG2C_SHIFT))
119
120 #define FP_INSTRA(opcode,arg0,arg1,arg2) \
121 (R300_ALU_OUTA_##opcode | \
122 ((arg0) << R300_ALU_ARG0A_SHIFT) | \
123 ((arg1) << R300_ALU_ARG1A_SHIFT) | \
124 ((arg2) << R300_ALU_ARG2A_SHIFT))
125
126 #endif
127
128 static void r300EmitClearState(GLcontext * ctx);
129
130 static void r300ClearBuffer(r300ContextPtr r300, int flags,
131 struct radeon_renderbuffer *rrb,
132 struct radeon_renderbuffer *rrbd)
133 {
134 BATCH_LOCALS(&r300->radeon);
135 GLcontext *ctx = r300->radeon.glCtx;
136 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
137 GLuint cbpitch = 0;
138 r300ContextPtr rmesa = r300;
139
140 if (RADEON_DEBUG & DEBUG_IOCTL)
141 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
142 __FUNCTION__, rrb, dPriv->x, dPriv->y,
143 dPriv->w, dPriv->h);
144
145 if (rrb) {
146 cbpitch = (rrb->pitch / rrb->cpp);
147 if (rrb->cpp == 4)
148 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
149 else
150 cbpitch |= R300_COLOR_FORMAT_RGB565;
151
152 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
153 cbpitch |= R300_COLOR_TILE_ENABLE;
154 }
155 }
156
157 /* TODO in bufmgr */
158 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
159 end_3d(&rmesa->radeon);
160
161 if (flags & CLEARBUFFER_COLOR) {
162 assert(rrb != 0);
163 BEGIN_BATCH_NO_AUTOSTATE(6);
164 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
165 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
166 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
167 END_BATCH();
168 }
169 #if 1
170 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
171 assert(rrbd != 0);
172 cbpitch = (rrbd->pitch / rrbd->cpp);
173 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
174 cbpitch |= R300_DEPTHMACROTILE_ENABLE;
175 }
176 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
177 cbpitch |= R300_DEPTHMICROTILE_TILED;
178 }
179 BEGIN_BATCH_NO_AUTOSTATE(6);
180 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
181 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
182 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
183 END_BATCH();
184 }
185 #endif
186 BEGIN_BATCH_NO_AUTOSTATE(6);
187 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
188 if (flags & CLEARBUFFER_COLOR) {
189 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
190 (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
191 (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
192 (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
193 } else {
194 OUT_BATCH(0);
195 }
196
197
198 {
199 uint32_t t1, t2;
200
201 t1 = 0x0;
202 t2 = 0x0;
203
204 if (flags & CLEARBUFFER_DEPTH) {
205 t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
206 t2 |=
207 (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
208 }
209
210 if (flags & CLEARBUFFER_STENCIL) {
211 t1 |= R300_STENCIL_ENABLE;
212 t2 |=
213 (R300_ZS_ALWAYS <<
214 R300_S_FRONT_FUNC_SHIFT) |
215 (R300_ZS_REPLACE <<
216 R300_S_FRONT_SFAIL_OP_SHIFT) |
217 (R300_ZS_REPLACE <<
218 R300_S_FRONT_ZPASS_OP_SHIFT) |
219 (R300_ZS_REPLACE <<
220 R300_S_FRONT_ZFAIL_OP_SHIFT);
221 }
222
223 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
224 OUT_BATCH(t1);
225 OUT_BATCH(t2);
226 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
227 R300_STENCILWRITEMASK_SHIFT) |
228 (ctx->Stencil.Clear & R300_STENCILREF_MASK));
229 END_BATCH();
230 }
231
232 if (!rmesa->radeon.radeonScreen->kernel_mm) {
233 BEGIN_BATCH_NO_AUTOSTATE(9);
234 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
235 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
236 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
237 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
238 OUT_BATCH_FLOAT32(1.0);
239 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
240 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
241 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
242 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
243 END_BATCH();
244 } else {
245 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
246 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
247 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
248 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
249 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
250 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
251 OUT_BATCH_FLOAT32(1.0);
252 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
253 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
254 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
255 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
256 }
257
258 r300EmitCacheFlush(rmesa);
259 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
260
261 R300_STATECHANGE(r300, cb);
262 R300_STATECHANGE(r300, cmk);
263 R300_STATECHANGE(r300, zs);
264 }
265
266 static void r300EmitClearState(GLcontext * ctx)
267 {
268 r300ContextPtr r300 = R300_CONTEXT(ctx);
269 BATCH_LOCALS(&r300->radeon);
270 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
271 int i;
272 int has_tcl;
273 int is_r500 = 0;
274 GLuint vap_cntl;
275
276 has_tcl = r300->options.hw_tcl_enabled;
277
278 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
279 is_r500 = 1;
280
281 /* State atom dirty tracking is a little subtle here.
282 *
283 * On the one hand, we need to make sure base state is emitted
284 * here if we start with an empty batch buffer, otherwise clear
285 * works incorrectly with multiple processes. Therefore, the first
286 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
287 *
288 * On the other hand, implicit state emission clears the state atom
289 * dirty bits, so we have to call R300_STATECHANGE later than the
290 * first BEGIN_BATCH.
291 *
292 * The final trickiness is that, because we change state, we need
293 * to ensure that any stored swtcl primitives are flushed properly
294 * before we start changing state. See the R300_NEWPRIM in r300Clear
295 * for this.
296 */
297 BEGIN_BATCH(31);
298 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
299 if (!has_tcl)
300 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
301 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
302 else
303 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
304 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
305
306 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
307 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
308 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
309 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
310 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
311 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
312 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
313 << R300_SWIZZLE0_SHIFT) |
314 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
315 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
316 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
317 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
318 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
319 << R300_SWIZZLE1_SHIFT)));
320
321 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
322 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
323 OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
324 OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
325
326 /* comes from fglrx startup of clear */
327 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
328 OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
329 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
330 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
331 R300_VPORT_Z_OFFSET_ENA);
332 OUT_BATCH(0x8);
333
334 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
335
336 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
337 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
338 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
339 OUT_BATCH(0); /* no textures */
340
341 OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
342
343 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
344 OUT_BATCH_FLOAT32(1.0);
345 OUT_BATCH_FLOAT32(dPriv->x);
346 OUT_BATCH_FLOAT32(1.0);
347 OUT_BATCH_FLOAT32(dPriv->y);
348 OUT_BATCH_FLOAT32(1.0);
349 OUT_BATCH_FLOAT32(0.0);
350
351 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
352
353 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
354 OUT_BATCH(0x0);
355 OUT_BATCH(0x0);
356 END_BATCH();
357
358 R300_STATECHANGE(r300, vir[0]);
359 R300_STATECHANGE(r300, fogs);
360 R300_STATECHANGE(r300, vir[1]);
361 R300_STATECHANGE(r300, vic);
362 R300_STATECHANGE(r300, vte);
363 R300_STATECHANGE(r300, vof);
364 R300_STATECHANGE(r300, txe);
365 R300_STATECHANGE(r300, vpt);
366 R300_STATECHANGE(r300, at);
367 R300_STATECHANGE(r300, bld);
368 R300_STATECHANGE(r300, ps);
369
370 if (has_tcl) {
371 R300_STATECHANGE(r300, vap_clip_cntl);
372
373 BEGIN_BATCH_NO_AUTOSTATE(2);
374 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
375 END_BATCH();
376 }
377
378 BEGIN_BATCH_NO_AUTOSTATE(2);
379 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
380 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
381 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
382 END_BATCH();
383
384 if (!is_r500) {
385 R300_STATECHANGE(r300, ri);
386 R300_STATECHANGE(r300, rc);
387 R300_STATECHANGE(r300, rr);
388
389 BEGIN_BATCH(14);
390 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
391 for (i = 0; i < 8; ++i)
392 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
393
394 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
395 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
396 OUT_BATCH(0x0);
397
398 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
399 END_BATCH();
400 } else {
401 R300_STATECHANGE(r300, ri);
402 R300_STATECHANGE(r300, rc);
403 R300_STATECHANGE(r300, rr);
404
405 BEGIN_BATCH(14);
406 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
407 for (i = 0; i < 8; ++i) {
408 OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
409 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
410 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
411 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
412 }
413
414 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
415 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
416 OUT_BATCH(0x0);
417
418 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
419 END_BATCH();
420 }
421
422 if (!is_r500) {
423 R300_STATECHANGE(r300, fp);
424 R300_STATECHANGE(r300, fpi[0]);
425 R300_STATECHANGE(r300, fpi[1]);
426 R300_STATECHANGE(r300, fpi[2]);
427 R300_STATECHANGE(r300, fpi[3]);
428
429 BEGIN_BATCH(17);
430 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
431 OUT_BATCH(0x0);
432 OUT_BATCH(0x0);
433 OUT_BATCH(0x0);
434 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
435 OUT_BATCH(0x0);
436 OUT_BATCH(0x0);
437 OUT_BATCH(0x0);
438 OUT_BATCH(R300_RGBA_OUT);
439
440 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
441 FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
442 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
443 FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
444 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
445 FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
446 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
447 FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
448 END_BATCH();
449 } else {
450 struct radeon_state_atom r500fp;
451 uint32_t _cmd[10];
452
453 R300_STATECHANGE(r300, fp);
454 R300_STATECHANGE(r300, r500fp);
455
456 BEGIN_BATCH(7);
457 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
458 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
459 OUT_BATCH(0x0);
460 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
461 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
462 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
463 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
464 END_BATCH();
465
466 r500fp.check = check_r500fp;
467 r500fp.cmd = _cmd;
468 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
469 r500fp.cmd[1] = R500_INST_TYPE_OUT |
470 R500_INST_TEX_SEM_WAIT |
471 R500_INST_LAST |
472 R500_INST_RGB_OMASK_R |
473 R500_INST_RGB_OMASK_G |
474 R500_INST_RGB_OMASK_B |
475 R500_INST_ALPHA_OMASK |
476 R500_INST_RGB_CLAMP |
477 R500_INST_ALPHA_CLAMP;
478 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
479 R500_RGB_ADDR1(0) |
480 R500_RGB_ADDR1_CONST |
481 R500_RGB_ADDR2(0) |
482 R500_RGB_ADDR2_CONST;
483 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
484 R500_ALPHA_ADDR1(0) |
485 R500_ALPHA_ADDR1_CONST |
486 R500_ALPHA_ADDR2(0) |
487 R500_ALPHA_ADDR2_CONST;
488 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
489 R500_ALU_RGB_R_SWIZ_A_R |
490 R500_ALU_RGB_G_SWIZ_A_G |
491 R500_ALU_RGB_B_SWIZ_A_B |
492 R500_ALU_RGB_SEL_B_SRC0 |
493 R500_ALU_RGB_R_SWIZ_B_R |
494 R500_ALU_RGB_B_SWIZ_B_G |
495 R500_ALU_RGB_G_SWIZ_B_B;
496 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
497 R500_ALPHA_SWIZ_A_A |
498 R500_ALPHA_SWIZ_B_A;
499 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
500 R500_ALU_RGBA_R_SWIZ_0 |
501 R500_ALU_RGBA_G_SWIZ_0 |
502 R500_ALU_RGBA_B_SWIZ_0 |
503 R500_ALU_RGBA_A_SWIZ_0;
504
505 r500fp.cmd[7] = 0;
506 emit_r500fp(ctx, &r500fp);
507 }
508
509 BEGIN_BATCH(2);
510 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
511 END_BATCH();
512
513 if (has_tcl) {
514 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
515 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
516 (12 << R300_VF_MAX_VTX_NUM_SHIFT));
517 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
518 vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
519 } else {
520 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
521 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
522 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
523 }
524
525 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
526 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
527 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
528 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
529 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
530 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
531 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
532 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
533 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
534 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
535 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
536 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
537 else
538 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
539
540 R300_STATECHANGE(r300, vap_cntl);
541
542 BEGIN_BATCH(2);
543 OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
544 END_BATCH();
545
546 if (has_tcl) {
547 struct radeon_state_atom vpu;
548 uint32_t _cmd[10];
549 R300_STATECHANGE(r300, pvs);
550 R300_STATECHANGE(r300, vpi);
551
552 BEGIN_BATCH(4);
553 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
554 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
555 (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
556 (1 << R300_PVS_LAST_INST_SHIFT));
557 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
558 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
559 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
560 END_BATCH();
561
562 vpu.check = check_vpu;
563 vpu.cmd = _cmd;
564 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
565
566 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
567 0, 0xf, PVS_DST_REG_OUT);
568 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
569 PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
570 PVS_SRC_REG_INPUT, NEGATE_NONE);
571 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
572 PVS_SRC_SELECT_FORCE_0,
573 PVS_SRC_SELECT_FORCE_0,
574 PVS_SRC_SELECT_FORCE_0,
575 PVS_SRC_REG_INPUT, NEGATE_NONE);
576 vpu.cmd[4] = 0x0;
577
578 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
579 PVS_DST_REG_OUT);
580 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
581 PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
582 PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
583 NEGATE_NONE);
584 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
585 PVS_SRC_SELECT_FORCE_0,
586 PVS_SRC_SELECT_FORCE_0,
587 PVS_SRC_SELECT_FORCE_0,
588 PVS_SRC_REG_INPUT, NEGATE_NONE);
589 vpu.cmd[8] = 0x0;
590
591 r300->vap_flush_needed = GL_TRUE;
592 emit_vpu(ctx, &vpu);
593 }
594 }
595
596 static int r300KernelClear(GLcontext *ctx, GLuint flags)
597 {
598 r300ContextPtr r300 = R300_CONTEXT(ctx);
599 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
600 struct radeon_framebuffer *rfb = dPriv->driverPrivate;
601 struct radeon_renderbuffer *rrb;
602 struct radeon_renderbuffer *rrbd;
603 int bits = 0, ret;
604
605 /* Make sure it fits there. */
606 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
607
608 if (flags & BUFFER_BIT_COLOR0) {
609 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
610 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
611 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
612 }
613
614 if (flags & BUFFER_BIT_FRONT_LEFT) {
615 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
616 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
617 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
618 }
619
620 if (flags & BUFFER_BIT_BACK_LEFT) {
621 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
622 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
623 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
624 }
625
626 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
627 if (rrbd) {
628 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
629 rrbd->bo, 0, RADEON_GEM_DOMAIN_VRAM);
630 }
631
632 ret = radeon_cs_space_check(r300->radeon.cmdbuf.cs);
633 if (ret)
634 return -1;
635
636 rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
637 if (flags || bits)
638 r300EmitClearState(ctx);
639
640 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
641 if (rrbd && (flags & BUFFER_BIT_DEPTH))
642 bits |= CLEARBUFFER_DEPTH;
643
644 if (rrbd && (flags & BUFFER_BIT_STENCIL))
645 bits |= CLEARBUFFER_STENCIL;
646
647 if (flags & BUFFER_BIT_COLOR0) {
648 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
649 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
650 bits = 0;
651 }
652
653 if (flags & BUFFER_BIT_FRONT_LEFT) {
654 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
655 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
656 bits = 0;
657 }
658
659 if (flags & BUFFER_BIT_BACK_LEFT) {
660 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
661 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
662 bits = 0;
663 }
664
665 if (bits)
666 r300ClearBuffer(r300, bits, NULL, rrbd);
667
668 COMMIT_BATCH();
669 return 0;
670 }
671
672 /**
673 * Buffer clear
674 */
675 static void r300Clear(GLcontext * ctx, GLbitfield mask)
676 {
677 r300ContextPtr r300 = R300_CONTEXT(ctx);
678 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
679 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
680 GLbitfield swrast_mask = 0, tri_mask = 0;
681 int i, ret;
682 struct gl_framebuffer *fb = ctx->DrawBuffer;
683
684 if (RADEON_DEBUG & DEBUG_IOCTL)
685 fprintf(stderr, "r300Clear\n");
686
687 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
688 LOCK_HARDWARE(&r300->radeon);
689 UNLOCK_HARDWARE(&r300->radeon);
690 if (dPriv->numClipRects == 0)
691 return;
692 }
693
694 /* Flush swtcl vertices if necessary, because we will change hardware
695 * state during clear. See also the state-related comment in
696 * r300EmitClearState.
697 */
698 R300_NEWPRIM(r300);
699
700 if (colorMask == ~0)
701 tri_mask |= (mask & BUFFER_BITS_COLOR);
702 else
703 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
704
705
706 /* HW stencil */
707 if (mask & BUFFER_BIT_STENCIL) {
708 tri_mask |= BUFFER_BIT_STENCIL;
709 }
710
711 /* HW depth */
712 if (mask & BUFFER_BIT_DEPTH) {
713 tri_mask |= BUFFER_BIT_DEPTH;
714 }
715
716 /* If we're doing a tri pass for depth/stencil, include a likely color
717 * buffer with it.
718 */
719
720 for (i = 0; i < BUFFER_COUNT; i++) {
721 GLuint bufBit = 1 << i;
722 if ((tri_mask) & bufBit) {
723 if (!fb->Attachment[i].Renderbuffer->ClassID) {
724 tri_mask &= ~bufBit;
725 swrast_mask |= bufBit;
726 }
727 }
728 }
729
730 /* SW fallback clearing */
731 swrast_mask = mask & ~tri_mask;
732
733 ret = 0;
734 if (tri_mask) {
735 if (r300->radeon.radeonScreen->kernel_mm)
736 radeonUserClear(ctx, tri_mask);
737 else {
738 /* if kernel clear fails due to size restraints fallback */
739 ret = r300KernelClear(ctx, tri_mask);
740 if (ret < 0)
741 swrast_mask |= tri_mask;
742 }
743 }
744
745 if (swrast_mask) {
746 if (RADEON_DEBUG & DEBUG_FALLBACKS)
747 fprintf(stderr, "%s: swrast clear, mask: %x\n",
748 __FUNCTION__, swrast_mask);
749 _swrast_Clear(ctx, swrast_mask);
750 }
751 }
752
753
754 void r300InitIoctlFuncs(struct dd_function_table *functions)
755 {
756 functions->Clear = r300Clear;
757 functions->Finish = radeonFinish;
758 functions->Flush = radeonFlush;
759 }