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Merge branch 'mesa_7_6_branch'
[mesa.git] / src / mesa / drivers / dri / r300 / r300_ioctl.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Keith Whitwell <keith@tungstengraphics.com>
36 *
37 * \author Nicolai Haehnle <prefect_@gmx.net>
38 */
39
40 #include <sched.h>
41 #include <errno.h>
42
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "main/simple_list.h"
48 #include "swrast/swrast.h"
49
50 #include "radeon_common.h"
51 #include "radeon_lock.h"
52 #include "r300_context.h"
53 #include "r300_ioctl.h"
54 #include "r300_cmdbuf.h"
55 #include "r300_state.h"
56 #include "r300_vertprog.h"
57 #include "radeon_reg.h"
58 #include "r300_emit.h"
59 #include "r300_context.h"
60
61 #include "vblank.h"
62
63 #define R200_3D_DRAW_IMMD_2 0xC0003500
64
65 #define CLEARBUFFER_COLOR 0x1
66 #define CLEARBUFFER_DEPTH 0x2
67 #define CLEARBUFFER_STENCIL 0x4
68
69 #if 1
70
71 /**
72 * Fragment program helper macros
73 */
74
75 /* Produce unshifted source selectors */
76 #define FP_TMP(idx) (idx)
77 #define FP_CONST(idx) ((idx) | (1 << 5))
78
79 /* Produce source/dest selector dword */
80 #define FP_SELC_MASK_NO 0
81 #define FP_SELC_MASK_X 1
82 #define FP_SELC_MASK_Y 2
83 #define FP_SELC_MASK_XY 3
84 #define FP_SELC_MASK_Z 4
85 #define FP_SELC_MASK_XZ 5
86 #define FP_SELC_MASK_YZ 6
87 #define FP_SELC_MASK_XYZ 7
88
89 #define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
90 (((destidx) << R300_ALU_DSTC_SHIFT) | \
91 (FP_SELC_MASK_##regmask << 23) | \
92 (FP_SELC_MASK_##outmask << 26) | \
93 ((src0) << R300_ALU_SRC0C_SHIFT) | \
94 ((src1) << R300_ALU_SRC1C_SHIFT) | \
95 ((src2) << R300_ALU_SRC2C_SHIFT))
96
97 #define FP_SELA_MASK_NO 0
98 #define FP_SELA_MASK_W 1
99
100 #define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
101 (((destidx) << R300_ALU_DSTA_SHIFT) | \
102 (FP_SELA_MASK_##regmask << 23) | \
103 (FP_SELA_MASK_##outmask << 24) | \
104 ((src0) << R300_ALU_SRC0A_SHIFT) | \
105 ((src1) << R300_ALU_SRC1A_SHIFT) | \
106 ((src2) << R300_ALU_SRC2A_SHIFT))
107
108 /* Produce unshifted argument selectors */
109 #define FP_ARGC(source) R300_ALU_ARGC_##source
110 #define FP_ARGA(source) R300_ALU_ARGA_##source
111 #define FP_ABS(arg) ((arg) | (1 << 6))
112 #define FP_NEG(arg) ((arg) ^ (1 << 5))
113
114 /* Produce instruction dword */
115 #define FP_INSTRC(opcode,arg0,arg1,arg2) \
116 (R300_ALU_OUTC_##opcode | \
117 ((arg0) << R300_ALU_ARG0C_SHIFT) | \
118 ((arg1) << R300_ALU_ARG1C_SHIFT) | \
119 ((arg2) << R300_ALU_ARG2C_SHIFT))
120
121 #define FP_INSTRA(opcode,arg0,arg1,arg2) \
122 (R300_ALU_OUTA_##opcode | \
123 ((arg0) << R300_ALU_ARG0A_SHIFT) | \
124 ((arg1) << R300_ALU_ARG1A_SHIFT) | \
125 ((arg2) << R300_ALU_ARG2A_SHIFT))
126
127 #endif
128
129 static void r300EmitClearState(GLcontext * ctx);
130
131 static void r300ClearBuffer(r300ContextPtr r300, int flags,
132 struct radeon_renderbuffer *rrb,
133 struct radeon_renderbuffer *rrbd)
134 {
135 BATCH_LOCALS(&r300->radeon);
136 GLcontext *ctx = r300->radeon.glCtx;
137 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
138 GLuint cbpitch = 0;
139 r300ContextPtr rmesa = r300;
140
141 if (RADEON_DEBUG & RADEON_IOCTL)
142 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
143 __FUNCTION__, rrb, dPriv->x, dPriv->y,
144 dPriv->w, dPriv->h);
145
146 if (rrb) {
147 cbpitch = (rrb->pitch / rrb->cpp);
148 if (rrb->cpp == 4)
149 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
150 else
151 cbpitch |= R300_COLOR_FORMAT_RGB565;
152
153 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
154 cbpitch |= R300_COLOR_TILE_ENABLE;
155 }
156 }
157
158 /* TODO in bufmgr */
159 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
160 end_3d(&rmesa->radeon);
161
162 if (flags & CLEARBUFFER_COLOR) {
163 assert(rrb != 0);
164 BEGIN_BATCH_NO_AUTOSTATE(6);
165 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
166 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
167 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
168 END_BATCH();
169 }
170 #if 1
171 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
172 uint32_t zbpitch = (rrbd->pitch / rrbd->cpp);
173 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
174 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
175 }
176 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
177 zbpitch |= R300_DEPTHMICROTILE_TILED;
178 }
179 BEGIN_BATCH_NO_AUTOSTATE(6);
180 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
181 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
182 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
183 if (!r300->radeon.radeonScreen->kernel_mm)
184 OUT_BATCH(zbpitch);
185 else
186 OUT_BATCH_RELOC(zbpitch, rrbd->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
187 END_BATCH();
188 }
189 #endif
190 BEGIN_BATCH_NO_AUTOSTATE(6);
191 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
192 if (flags & CLEARBUFFER_COLOR) {
193 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
194 (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
195 (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
196 (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
197 } else {
198 OUT_BATCH(0);
199 }
200
201
202 {
203 uint32_t t1, t2;
204
205 t1 = 0x0;
206 t2 = 0x0;
207
208 if (flags & CLEARBUFFER_DEPTH) {
209 t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
210 t2 |=
211 (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
212 }
213
214 if (flags & CLEARBUFFER_STENCIL) {
215 t1 |= R300_STENCIL_ENABLE;
216 t2 |=
217 (R300_ZS_ALWAYS <<
218 R300_S_FRONT_FUNC_SHIFT) |
219 (R300_ZS_REPLACE <<
220 R300_S_FRONT_SFAIL_OP_SHIFT) |
221 (R300_ZS_REPLACE <<
222 R300_S_FRONT_ZPASS_OP_SHIFT) |
223 (R300_ZS_REPLACE <<
224 R300_S_FRONT_ZFAIL_OP_SHIFT);
225 }
226
227 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
228 OUT_BATCH(t1);
229 OUT_BATCH(t2);
230 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
231 R300_STENCILWRITEMASK_SHIFT) |
232 (ctx->Stencil.Clear & R300_STENCILREF_MASK));
233 END_BATCH();
234 }
235
236 if (!rmesa->radeon.radeonScreen->kernel_mm) {
237 BEGIN_BATCH_NO_AUTOSTATE(9);
238 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
239 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
240 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
241 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
242 OUT_BATCH_FLOAT32(1.0);
243 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
244 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
245 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
246 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
247 END_BATCH();
248 } else {
249 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
250 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
251 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
252 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
253 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
254 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
255 OUT_BATCH_FLOAT32(1.0);
256 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
257 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
258 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
259 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
260 }
261
262 r300EmitCacheFlush(rmesa);
263 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
264
265 R300_STATECHANGE(r300, cb);
266 R300_STATECHANGE(r300, cmk);
267 R300_STATECHANGE(r300, zs);
268 }
269
270 static void r300EmitClearState(GLcontext * ctx)
271 {
272 r300ContextPtr r300 = R300_CONTEXT(ctx);
273 BATCH_LOCALS(&r300->radeon);
274 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
275 int i;
276 int has_tcl;
277 int is_r500 = 0;
278 GLuint vap_cntl;
279
280 has_tcl = r300->options.hw_tcl_enabled;
281
282 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
283 is_r500 = 1;
284
285 /* State atom dirty tracking is a little subtle here.
286 *
287 * On the one hand, we need to make sure base state is emitted
288 * here if we start with an empty batch buffer, otherwise clear
289 * works incorrectly with multiple processes. Therefore, the first
290 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
291 *
292 * On the other hand, implicit state emission clears the state atom
293 * dirty bits, so we have to call R300_STATECHANGE later than the
294 * first BEGIN_BATCH.
295 *
296 * The final trickiness is that, because we change state, we need
297 * to ensure that any stored swtcl primitives are flushed properly
298 * before we start changing state. See the R300_NEWPRIM in r300Clear
299 * for this.
300 */
301 BEGIN_BATCH(31);
302 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
303 if (!has_tcl)
304 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
305 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
306 else
307 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
308 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
309
310 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
311 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
312 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
313 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
314 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
315 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
316 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
317 << R300_SWIZZLE0_SHIFT) |
318 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
319 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
320 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
321 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
322 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
323 << R300_SWIZZLE1_SHIFT)));
324
325 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
326 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
327 OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
328 OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
329
330 /* comes from fglrx startup of clear */
331 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
332 OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
333 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
334 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
335 R300_VPORT_Z_OFFSET_ENA);
336 OUT_BATCH(0x8);
337
338 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
339
340 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
341 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
342 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
343 OUT_BATCH(0); /* no textures */
344
345 OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
346
347 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
348 OUT_BATCH_FLOAT32(1.0);
349 OUT_BATCH_FLOAT32(dPriv->x);
350 OUT_BATCH_FLOAT32(1.0);
351 OUT_BATCH_FLOAT32(dPriv->y);
352 OUT_BATCH_FLOAT32(1.0);
353 OUT_BATCH_FLOAT32(0.0);
354
355 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
356
357 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
358 OUT_BATCH(0x0);
359 OUT_BATCH(0x0);
360 END_BATCH();
361
362 R300_STATECHANGE(r300, vir[0]);
363 R300_STATECHANGE(r300, fogs);
364 R300_STATECHANGE(r300, vir[1]);
365 R300_STATECHANGE(r300, vic);
366 R300_STATECHANGE(r300, vte);
367 R300_STATECHANGE(r300, vof);
368 R300_STATECHANGE(r300, txe);
369 R300_STATECHANGE(r300, vpt);
370 R300_STATECHANGE(r300, at);
371 R300_STATECHANGE(r300, bld);
372 R300_STATECHANGE(r300, ps);
373
374 if (has_tcl) {
375 R300_STATECHANGE(r300, vap_clip_cntl);
376
377 BEGIN_BATCH_NO_AUTOSTATE(2);
378 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
379 END_BATCH();
380 }
381
382 BEGIN_BATCH_NO_AUTOSTATE(2);
383 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
384 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
385 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
386 END_BATCH();
387
388 if (!is_r500) {
389 R300_STATECHANGE(r300, ri);
390 R300_STATECHANGE(r300, rc);
391 R300_STATECHANGE(r300, rr);
392
393 BEGIN_BATCH(14);
394 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
395 for (i = 0; i < 8; ++i)
396 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
397
398 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
399 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
400 OUT_BATCH(0x0);
401
402 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
403 END_BATCH();
404 } else {
405 R300_STATECHANGE(r300, ri);
406 R300_STATECHANGE(r300, rc);
407 R300_STATECHANGE(r300, rr);
408
409 BEGIN_BATCH(14);
410 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
411 for (i = 0; i < 8; ++i) {
412 OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
413 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
414 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
415 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
416 }
417
418 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
419 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
420 OUT_BATCH(0x0);
421
422 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
423 END_BATCH();
424 }
425
426 if (!is_r500) {
427 R300_STATECHANGE(r300, fp);
428 R300_STATECHANGE(r300, fpi[0]);
429 R300_STATECHANGE(r300, fpi[1]);
430 R300_STATECHANGE(r300, fpi[2]);
431 R300_STATECHANGE(r300, fpi[3]);
432
433 BEGIN_BATCH(17);
434 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
435 OUT_BATCH(0x0);
436 OUT_BATCH(0x0);
437 OUT_BATCH(0x0);
438 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
439 OUT_BATCH(0x0);
440 OUT_BATCH(0x0);
441 OUT_BATCH(0x0);
442 OUT_BATCH(R300_RGBA_OUT);
443
444 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
445 FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
446 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
447 FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
448 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
449 FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
450 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
451 FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
452 END_BATCH();
453 } else {
454 struct radeon_state_atom r500fp;
455 uint32_t _cmd[10];
456
457 R300_STATECHANGE(r300, fp);
458 R300_STATECHANGE(r300, r500fp);
459
460 BEGIN_BATCH(7);
461 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
462 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
463 OUT_BATCH(0x0);
464 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
465 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
466 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
467 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
468 END_BATCH();
469
470 r500fp.check = check_r500fp;
471 r500fp.cmd = _cmd;
472 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
473 r500fp.cmd[1] = R500_INST_TYPE_OUT |
474 R500_INST_TEX_SEM_WAIT |
475 R500_INST_LAST |
476 R500_INST_RGB_OMASK_R |
477 R500_INST_RGB_OMASK_G |
478 R500_INST_RGB_OMASK_B |
479 R500_INST_ALPHA_OMASK |
480 R500_INST_RGB_CLAMP |
481 R500_INST_ALPHA_CLAMP;
482 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
483 R500_RGB_ADDR1(0) |
484 R500_RGB_ADDR1_CONST |
485 R500_RGB_ADDR2(0) |
486 R500_RGB_ADDR2_CONST;
487 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
488 R500_ALPHA_ADDR1(0) |
489 R500_ALPHA_ADDR1_CONST |
490 R500_ALPHA_ADDR2(0) |
491 R500_ALPHA_ADDR2_CONST;
492 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
493 R500_ALU_RGB_R_SWIZ_A_R |
494 R500_ALU_RGB_G_SWIZ_A_G |
495 R500_ALU_RGB_B_SWIZ_A_B |
496 R500_ALU_RGB_SEL_B_SRC0 |
497 R500_ALU_RGB_R_SWIZ_B_R |
498 R500_ALU_RGB_B_SWIZ_B_G |
499 R500_ALU_RGB_G_SWIZ_B_B;
500 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
501 R500_ALPHA_SWIZ_A_A |
502 R500_ALPHA_SWIZ_B_A;
503 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
504 R500_ALU_RGBA_R_SWIZ_0 |
505 R500_ALU_RGBA_G_SWIZ_0 |
506 R500_ALU_RGBA_B_SWIZ_0 |
507 R500_ALU_RGBA_A_SWIZ_0;
508
509 r500fp.cmd[7] = 0;
510 if (r300->radeon.radeonScreen->kernel_mm) {
511 emit_r500fp(ctx, &r500fp);
512 } else {
513 int dwords = r500fp.check(ctx,&r500fp);
514 BEGIN_BATCH_NO_AUTOSTATE(dwords);
515 OUT_BATCH_TABLE(r500fp.cmd, dwords);
516 END_BATCH();
517 }
518
519 }
520
521 BEGIN_BATCH(2);
522 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
523 END_BATCH();
524
525 if (has_tcl) {
526 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
527 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
528 (12 << R300_VF_MAX_VTX_NUM_SHIFT));
529 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
530 vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
531 } else {
532 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
533 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
534 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
535 }
536
537 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
538 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
539 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
540 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
541 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
542 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
543 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
544 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
545 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
546 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
547 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
548 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
549 else
550 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
551
552 R300_STATECHANGE(r300, vap_cntl);
553
554 BEGIN_BATCH(2);
555 OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
556 END_BATCH();
557
558 if (has_tcl) {
559 struct radeon_state_atom vpu;
560 uint32_t _cmd[10];
561 R300_STATECHANGE(r300, pvs);
562 R300_STATECHANGE(r300, vap_flush);
563 R300_STATECHANGE(r300, vpi);
564
565 BEGIN_BATCH(4);
566 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
567 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
568 (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
569 (1 << R300_PVS_LAST_INST_SHIFT));
570 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
571 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
572 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
573 END_BATCH();
574
575 vpu.check = check_vpu;
576 vpu.cmd = _cmd;
577 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
578
579 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
580 0, 0xf, PVS_DST_REG_OUT);
581 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
582 PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
583 PVS_SRC_REG_INPUT, NEGATE_NONE);
584 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
585 PVS_SRC_SELECT_FORCE_0,
586 PVS_SRC_SELECT_FORCE_0,
587 PVS_SRC_SELECT_FORCE_0,
588 PVS_SRC_REG_INPUT, NEGATE_NONE);
589 vpu.cmd[4] = 0x0;
590
591 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
592 PVS_DST_REG_OUT);
593 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
594 PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
595 PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
596 NEGATE_NONE);
597 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
598 PVS_SRC_SELECT_FORCE_0,
599 PVS_SRC_SELECT_FORCE_0,
600 PVS_SRC_SELECT_FORCE_0,
601 PVS_SRC_REG_INPUT, NEGATE_NONE);
602 vpu.cmd[8] = 0x0;
603
604 if (r300->radeon.radeonScreen->kernel_mm) {
605 int dwords = r300->hw.vap_flush.check(ctx,&r300->hw.vap_flush);
606 BEGIN_BATCH_NO_AUTOSTATE(dwords);
607 OUT_BATCH_TABLE(r300->hw.vap_flush.cmd, dwords);
608 END_BATCH();
609 emit_vpu(ctx, &vpu);
610 } else {
611 int dwords = vpu.check(ctx,&vpu);
612 BEGIN_BATCH_NO_AUTOSTATE(dwords);
613 OUT_BATCH_TABLE(vpu.cmd, dwords);
614 END_BATCH();
615 }
616
617 }
618 }
619
620 static int r300KernelClear(GLcontext *ctx, GLuint flags)
621 {
622 r300ContextPtr r300 = R300_CONTEXT(ctx);
623 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
624 struct radeon_framebuffer *rfb = dPriv->driverPrivate;
625 struct radeon_renderbuffer *rrb;
626 struct radeon_renderbuffer *rrbd;
627 int bits = 0, ret;
628
629 /* Make sure it fits there. */
630 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
631
632 if (flags & BUFFER_BIT_COLOR0) {
633 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
634 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
635 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
636 }
637
638 if (flags & BUFFER_BIT_FRONT_LEFT) {
639 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
640 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
641 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
642 }
643
644 if (flags & BUFFER_BIT_BACK_LEFT) {
645 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
646 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
647 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
648 }
649
650 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
651 if (rrbd) {
652 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
653 rrbd->bo, 0, RADEON_GEM_DOMAIN_VRAM);
654 }
655
656 ret = radeon_cs_space_check(r300->radeon.cmdbuf.cs);
657 if (ret)
658 return -1;
659
660 rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
661 if (flags || bits)
662 r300EmitClearState(ctx);
663
664 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
665 if (rrbd && (flags & BUFFER_BIT_DEPTH))
666 bits |= CLEARBUFFER_DEPTH;
667
668 if (rrbd && (flags & BUFFER_BIT_STENCIL))
669 bits |= CLEARBUFFER_STENCIL;
670
671 if (flags & BUFFER_BIT_COLOR0) {
672 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
673 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
674 bits = 0;
675 }
676
677 if (flags & BUFFER_BIT_FRONT_LEFT) {
678 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
679 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
680 bits = 0;
681 }
682
683 if (flags & BUFFER_BIT_BACK_LEFT) {
684 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
685 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
686 bits = 0;
687 }
688
689 if (bits)
690 r300ClearBuffer(r300, bits, NULL, rrbd);
691
692 COMMIT_BATCH();
693 return 0;
694 }
695
696 /**
697 * Buffer clear
698 */
699 static void r300Clear(GLcontext * ctx, GLbitfield mask)
700 {
701 r300ContextPtr r300 = R300_CONTEXT(ctx);
702 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
703 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
704 GLbitfield swrast_mask = 0, tri_mask = 0;
705 int i, ret;
706 struct gl_framebuffer *fb = ctx->DrawBuffer;
707
708 if (RADEON_DEBUG & RADEON_IOCTL)
709 fprintf(stderr, "r300Clear\n");
710
711 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
712 LOCK_HARDWARE(&r300->radeon);
713 UNLOCK_HARDWARE(&r300->radeon);
714 if (dPriv->numClipRects == 0)
715 return;
716 }
717
718 /* Flush swtcl vertices if necessary, because we will change hardware
719 * state during clear. See also the state-related comment in
720 * r300EmitClearState.
721 */
722 R300_NEWPRIM(r300);
723
724 if (colorMask == ~0)
725 tri_mask |= (mask & BUFFER_BITS_COLOR);
726 else
727 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
728
729
730 /* HW stencil */
731 if (mask & BUFFER_BIT_STENCIL) {
732 tri_mask |= BUFFER_BIT_STENCIL;
733 }
734
735 /* HW depth */
736 if (mask & BUFFER_BIT_DEPTH) {
737 tri_mask |= BUFFER_BIT_DEPTH;
738 }
739
740 /* If we're doing a tri pass for depth/stencil, include a likely color
741 * buffer with it.
742 */
743
744 for (i = 0; i < BUFFER_COUNT; i++) {
745 GLuint bufBit = 1 << i;
746 if ((tri_mask) & bufBit) {
747 if (!fb->Attachment[i].Renderbuffer->ClassID) {
748 tri_mask &= ~bufBit;
749 swrast_mask |= bufBit;
750 }
751 }
752 }
753
754 /* SW fallback clearing */
755 swrast_mask = mask & ~tri_mask;
756
757 ret = 0;
758 if (tri_mask) {
759 if (r300->radeon.radeonScreen->kernel_mm)
760 radeonUserClear(ctx, tri_mask);
761 else {
762 /* if kernel clear fails due to size restraints fallback */
763 ret = r300KernelClear(ctx, tri_mask);
764 if (ret < 0)
765 swrast_mask |= tri_mask;
766 }
767 }
768
769 if (swrast_mask) {
770 if (RADEON_DEBUG & RADEON_FALLBACKS)
771 fprintf(stderr, "%s: swrast clear, mask: %x\n",
772 __FUNCTION__, swrast_mask);
773 _swrast_Clear(ctx, swrast_mask);
774 }
775 }
776
777 void r300InitIoctlFuncs(struct dd_function_table *functions)
778 {
779 functions->Clear = r300Clear;
780 functions->Finish = radeonFinish;
781 functions->Flush = radeonFlush;
782 }