2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 **************************************************************************/
35 * \author Keith Whitwell <keith@tungstengraphics.com>
37 * \author Nicolai Haehnle <prefect_@gmx.net>
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
49 #include "radeon_common.h"
50 #include "radeon_lock.h"
51 #include "r300_context.h"
52 #include "r300_ioctl.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_state.h"
55 #include "r300_vertprog.h"
56 #include "radeon_reg.h"
57 #include "r300_emit.h"
58 #include "r300_fragprog.h"
59 #include "r300_context.h"
63 #define R200_3D_DRAW_IMMD_2 0xC0003500
65 #define CLEARBUFFER_COLOR 0x1
66 #define CLEARBUFFER_DEPTH 0x2
67 #define CLEARBUFFER_STENCIL 0x4
69 static void r300EmitClearState(GLcontext
* ctx
);
71 static void r300UserClear(GLcontext
*ctx
, GLuint mask
)
73 radeon_clear_tris(ctx
, mask
);
76 static void r300ClearBuffer(r300ContextPtr r300
, int flags
,
77 struct radeon_renderbuffer
*rrb
,
78 struct radeon_renderbuffer
*rrbd
)
80 BATCH_LOCALS(&r300
->radeon
);
81 GLcontext
*ctx
= r300
->radeon
.glCtx
;
82 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
84 r300ContextPtr rmesa
= r300
;
86 if (RADEON_DEBUG
& DEBUG_IOCTL
)
87 fprintf(stderr
, "%s: buffer %p (%i,%i %ix%i)\n",
88 __FUNCTION__
, rrb
, dPriv
->x
, dPriv
->y
,
92 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
94 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
96 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
98 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
){
99 cbpitch
|= R300_COLOR_TILE_ENABLE
;
104 cp_wait(&r300
->radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
105 end_3d(&rmesa
->radeon
);
107 if (flags
& CLEARBUFFER_COLOR
) {
109 BEGIN_BATCH_NO_AUTOSTATE(6);
110 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
111 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
112 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0
, cbpitch
);
116 if (flags
& (CLEARBUFFER_DEPTH
| CLEARBUFFER_STENCIL
)) {
118 cbpitch
= (rrbd
->pitch
/ rrbd
->cpp
);
119 if (rrbd
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
){
120 cbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
122 if (rrbd
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
123 cbpitch
|= R300_DEPTHMICROTILE_TILED
;
125 BEGIN_BATCH_NO_AUTOSTATE(6);
126 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
127 OUT_BATCH_RELOC(0, rrbd
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
128 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH
, cbpitch
);
132 BEGIN_BATCH_NO_AUTOSTATE(6);
133 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK
, 1);
134 if (flags
& CLEARBUFFER_COLOR
) {
135 OUT_BATCH((ctx
->Color
.ColorMask
[BCOMP
] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0
: 0) |
136 (ctx
->Color
.ColorMask
[GCOMP
] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0
: 0) |
137 (ctx
->Color
.ColorMask
[RCOMP
] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0
: 0) |
138 (ctx
->Color
.ColorMask
[ACOMP
] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0
: 0));
150 if (flags
& CLEARBUFFER_DEPTH
) {
151 t1
|= R300_Z_ENABLE
| R300_Z_WRITE_ENABLE
;
153 (R300_ZS_ALWAYS
<< R300_Z_FUNC_SHIFT
);
156 if (flags
& CLEARBUFFER_STENCIL
) {
157 t1
|= R300_STENCIL_ENABLE
;
160 R300_S_FRONT_FUNC_SHIFT
) |
162 R300_S_FRONT_SFAIL_OP_SHIFT
) |
164 R300_S_FRONT_ZPASS_OP_SHIFT
) |
166 R300_S_FRONT_ZFAIL_OP_SHIFT
);
169 OUT_BATCH_REGSEQ(R300_ZB_CNTL
, 3);
172 OUT_BATCH(((ctx
->Stencil
.WriteMask
[0] & R300_STENCILREF_MASK
) <<
173 R300_STENCILWRITEMASK_SHIFT
) |
174 (ctx
->Stencil
.Clear
& R300_STENCILREF_MASK
));
178 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
179 BEGIN_BATCH_NO_AUTOSTATE(9);
180 OUT_BATCH(cmdpacket3(r300
->radeon
.radeonScreen
, R300_CMD_PACKET3_CLEAR
));
181 OUT_BATCH_FLOAT32(dPriv
->w
/ 2.0);
182 OUT_BATCH_FLOAT32(dPriv
->h
/ 2.0);
183 OUT_BATCH_FLOAT32(ctx
->Depth
.Clear
);
184 OUT_BATCH_FLOAT32(1.0);
185 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[0]);
186 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[1]);
187 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[2]);
188 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[3]);
191 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2
, 8));
192 OUT_BATCH(R300_PRIM_TYPE_POINT
| R300_PRIM_WALK_RING
|
193 (1 << R300_PRIM_NUM_VERTICES_SHIFT
));
194 OUT_BATCH_FLOAT32(dPriv
->w
/ 2.0);
195 OUT_BATCH_FLOAT32(dPriv
->h
/ 2.0);
196 OUT_BATCH_FLOAT32(ctx
->Depth
.Clear
);
197 OUT_BATCH_FLOAT32(1.0);
198 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[0]);
199 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[1]);
200 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[2]);
201 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[3]);
204 r300EmitCacheFlush(rmesa
);
205 cp_wait(&r300
->radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
207 R300_STATECHANGE(r300
, cb
);
208 R300_STATECHANGE(r300
, cmk
);
209 R300_STATECHANGE(r300
, zs
);
212 static void r300EmitClearState(GLcontext
* ctx
)
214 r300ContextPtr r300
= R300_CONTEXT(ctx
);
215 BATCH_LOCALS(&r300
->radeon
);
216 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
222 if (!(r300
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
))
225 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
228 /* State atom dirty tracking is a little subtle here.
230 * On the one hand, we need to make sure base state is emitted
231 * here if we start with an empty batch buffer, otherwise clear
232 * works incorrectly with multiple processes. Therefore, the first
233 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
235 * On the other hand, implicit state emission clears the state atom
236 * dirty bits, so we have to call R300_STATECHANGE later than the
239 * The final trickiness is that, because we change state, we need
240 * to ensure that any stored swtcl primitives are flushed properly
241 * before we start changing state. See the R300_NEWPRIM in r300Clear
245 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0
, 1);
247 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
248 ((R300_LAST_VEC
| (2 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
250 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
251 ((R300_LAST_VEC
| (1 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
253 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND
, 0);
254 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0
,
255 ((((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
256 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
257 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
258 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
259 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
260 << R300_SWIZZLE0_SHIFT
) |
261 (((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
262 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
263 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
264 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
265 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
266 << R300_SWIZZLE1_SHIFT
)));
268 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
269 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL
, 2);
270 OUT_BATCH((R300_SEL_USER_COLOR_0
<< R300_COLOR_0_ASSEMBLY_SHIFT
));
271 OUT_BATCH(R300_INPUT_CNTL_POS
| R300_INPUT_CNTL_COLOR
| R300_INPUT_CNTL_TC0
);
273 /* comes from fglrx startup of clear */
274 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL
, 2);
275 OUT_BATCH(R300_VTX_W0_FMT
| R300_VPORT_X_SCALE_ENA
|
276 R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Y_SCALE_ENA
|
277 R300_VPORT_Y_OFFSET_ENA
| R300_VPORT_Z_SCALE_ENA
|
278 R300_VPORT_Z_OFFSET_ENA
);
281 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL
, 0xaaaaaaaa);
283 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
284 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
|
285 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
);
286 OUT_BATCH(0); /* no textures */
288 OUT_BATCH_REGVAL(R300_TX_ENABLE
, 0);
290 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE
, 6);
291 OUT_BATCH_FLOAT32(1.0);
292 OUT_BATCH_FLOAT32(dPriv
->x
);
293 OUT_BATCH_FLOAT32(1.0);
294 OUT_BATCH_FLOAT32(dPriv
->y
);
295 OUT_BATCH_FLOAT32(1.0);
296 OUT_BATCH_FLOAT32(0.0);
298 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC
, 0);
300 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND
, 2);
305 R300_STATECHANGE(r300
, vir
[0]);
306 R300_STATECHANGE(r300
, fogs
);
307 R300_STATECHANGE(r300
, vir
[1]);
308 R300_STATECHANGE(r300
, vic
);
309 R300_STATECHANGE(r300
, vte
);
310 R300_STATECHANGE(r300
, vof
);
311 R300_STATECHANGE(r300
, txe
);
312 R300_STATECHANGE(r300
, vpt
);
313 R300_STATECHANGE(r300
, at
);
314 R300_STATECHANGE(r300
, bld
);
315 R300_STATECHANGE(r300
, ps
);
318 R300_STATECHANGE(r300
, vap_clip_cntl
);
320 BEGIN_BATCH_NO_AUTOSTATE(2);
321 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL
, R300_PS_UCP_MODE_CLIP_AS_TRIFAN
| R300_CLIP_DISABLE
);
325 BEGIN_BATCH_NO_AUTOSTATE(2);
326 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE
,
327 ((dPriv
->w
* 6) << R300_POINTSIZE_X_SHIFT
) |
328 ((dPriv
->h
* 6) << R300_POINTSIZE_Y_SHIFT
));
332 R300_STATECHANGE(r300
, ri
);
333 R300_STATECHANGE(r300
, rc
);
334 R300_STATECHANGE(r300
, rr
);
337 OUT_BATCH_REGSEQ(R300_RS_IP_0
, 8);
338 for (i
= 0; i
< 8; ++i
)
339 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
341 OUT_BATCH_REGSEQ(R300_RS_COUNT
, 2);
342 OUT_BATCH((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
345 OUT_BATCH_REGVAL(R300_RS_INST_0
, R300_RS_INST_COL_CN_WRITE
);
348 R300_STATECHANGE(r300
, ri
);
349 R300_STATECHANGE(r300
, rc
);
350 R300_STATECHANGE(r300
, rr
);
353 OUT_BATCH_REGSEQ(R500_RS_IP_0
, 8);
354 for (i
= 0; i
< 8; ++i
) {
355 OUT_BATCH((R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_S_SHIFT
) |
356 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_T_SHIFT
) |
357 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_R_SHIFT
) |
358 (R500_RS_IP_PTR_K1
<< R500_RS_IP_TEX_PTR_Q_SHIFT
));
361 OUT_BATCH_REGSEQ(R300_RS_COUNT
, 2);
362 OUT_BATCH((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
365 OUT_BATCH_REGVAL(R500_RS_INST_0
, R500_RS_INST_COL_CN_WRITE
);
370 R300_STATECHANGE(r300
, fp
);
371 R300_STATECHANGE(r300
, fpi
[0]);
372 R300_STATECHANGE(r300
, fpi
[1]);
373 R300_STATECHANGE(r300
, fpi
[2]);
374 R300_STATECHANGE(r300
, fpi
[3]);
377 OUT_BATCH_REGSEQ(R300_US_CONFIG
, 3);
381 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0
, 4);
385 OUT_BATCH(R300_RGBA_OUT
);
387 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0
,
388 FP_INSTRC(MAD
, FP_ARGC(SRC0C_XYZ
), FP_ARGC(ONE
), FP_ARGC(ZERO
)));
389 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0
,
390 FP_SELC(0, NO
, XYZ
, FP_TMP(0), 0, 0));
391 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0
,
392 FP_INSTRA(MAD
, FP_ARGA(SRC0A
), FP_ARGA(ONE
), FP_ARGA(ZERO
)));
393 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0
,
394 FP_SELA(0, NO
, W
, FP_TMP(0), 0, 0));
397 struct radeon_state_atom r500fp
;
400 R300_STATECHANGE(r300
, fp
);
401 R300_STATECHANGE(r300
, r500fp
);
404 OUT_BATCH_REGSEQ(R500_US_CONFIG
, 2);
405 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
407 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR
, 3);
408 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
409 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
410 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
413 r500fp
.check
= check_r500fp
;
415 r500fp
.cmd
[0] = cmdr500fp(r300
->radeon
.radeonScreen
, 0, 1, 0, 0);
416 r500fp
.cmd
[1] = R500_INST_TYPE_OUT
|
417 R500_INST_TEX_SEM_WAIT
|
419 R500_INST_RGB_OMASK_R
|
420 R500_INST_RGB_OMASK_G
|
421 R500_INST_RGB_OMASK_B
|
422 R500_INST_ALPHA_OMASK
|
423 R500_INST_RGB_CLAMP
|
424 R500_INST_ALPHA_CLAMP
;
425 r500fp
.cmd
[2] = R500_RGB_ADDR0(0) |
427 R500_RGB_ADDR1_CONST
|
429 R500_RGB_ADDR2_CONST
;
430 r500fp
.cmd
[3] = R500_ALPHA_ADDR0(0) |
431 R500_ALPHA_ADDR1(0) |
432 R500_ALPHA_ADDR1_CONST
|
433 R500_ALPHA_ADDR2(0) |
434 R500_ALPHA_ADDR2_CONST
;
435 r500fp
.cmd
[4] = R500_ALU_RGB_SEL_A_SRC0
|
436 R500_ALU_RGB_R_SWIZ_A_R
|
437 R500_ALU_RGB_G_SWIZ_A_G
|
438 R500_ALU_RGB_B_SWIZ_A_B
|
439 R500_ALU_RGB_SEL_B_SRC0
|
440 R500_ALU_RGB_R_SWIZ_B_R
|
441 R500_ALU_RGB_B_SWIZ_B_G
|
442 R500_ALU_RGB_G_SWIZ_B_B
;
443 r500fp
.cmd
[5] = R500_ALPHA_OP_CMP
|
444 R500_ALPHA_SWIZ_A_A
|
446 r500fp
.cmd
[6] = R500_ALU_RGBA_OP_CMP
|
447 R500_ALU_RGBA_R_SWIZ_0
|
448 R500_ALU_RGBA_G_SWIZ_0
|
449 R500_ALU_RGBA_B_SWIZ_0
|
450 R500_ALU_RGBA_A_SWIZ_0
;
453 emit_r500fp(ctx
, &r500fp
);
457 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
461 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
462 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
463 (12 << R300_VF_MAX_VTX_NUM_SHIFT
));
464 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
465 vap_cntl
|= R500_TCL_STATE_OPTIMIZATION
;
467 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
468 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
469 (5 << R300_VF_MAX_VTX_NUM_SHIFT
));
472 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV515
)
473 vap_cntl
|= (2 << R300_PVS_NUM_FPUS_SHIFT
);
474 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) ||
475 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV560
) ||
476 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV570
))
477 vap_cntl
|= (5 << R300_PVS_NUM_FPUS_SHIFT
);
478 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV410
) ||
479 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R420
))
480 vap_cntl
|= (6 << R300_PVS_NUM_FPUS_SHIFT
);
481 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R520
) ||
482 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R580
))
483 vap_cntl
|= (8 << R300_PVS_NUM_FPUS_SHIFT
);
485 vap_cntl
|= (4 << R300_PVS_NUM_FPUS_SHIFT
);
487 R300_STATECHANGE(r300
, vap_cntl
);
490 OUT_BATCH_REGVAL(R300_VAP_CNTL
, vap_cntl
);
494 struct radeon_state_atom vpu
;
496 R300_STATECHANGE(r300
, pvs
);
497 R300_STATECHANGE(r300
, vpi
);
500 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
501 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT
) |
502 (0 << R300_PVS_XYZW_VALID_INST_SHIFT
) |
503 (1 << R300_PVS_LAST_INST_SHIFT
));
504 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT
) |
505 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT
));
506 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT
);
509 vpu
.check
= check_vpu
;
511 vpu
.cmd
[0] = cmdvpu(r300
->radeon
.radeonScreen
, 0, 2);
513 vpu
.cmd
[1] = PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
,
514 0, 0xf, PVS_DST_REG_OUT
);
515 vpu
.cmd
[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X
, PVS_SRC_SELECT_Y
,
516 PVS_SRC_SELECT_Z
, PVS_SRC_SELECT_W
,
517 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
518 vpu
.cmd
[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0
,
519 PVS_SRC_SELECT_FORCE_0
,
520 PVS_SRC_SELECT_FORCE_0
,
521 PVS_SRC_SELECT_FORCE_0
,
522 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
525 vpu
.cmd
[5] = PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
, 1, 0xf,
527 vpu
.cmd
[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X
,
528 PVS_SRC_SELECT_Y
, PVS_SRC_SELECT_Z
,
529 PVS_SRC_SELECT_W
, PVS_SRC_REG_INPUT
,
532 vpu
.cmd
[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0
,
533 PVS_SRC_SELECT_FORCE_0
,
534 PVS_SRC_SELECT_FORCE_0
,
535 PVS_SRC_SELECT_FORCE_0
,
536 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
539 r300
->vap_flush_needed
= GL_TRUE
;
544 static void r300KernelClear(GLcontext
*ctx
, GLuint flags
)
546 r300ContextPtr r300
= R300_CONTEXT(ctx
);
547 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
548 struct radeon_framebuffer
*rfb
= dPriv
->driverPrivate
;
549 struct radeon_renderbuffer
*rrb
;
550 struct radeon_renderbuffer
*rrbd
;
553 /* Make sure it fits there. */
554 rcommonEnsureCmdBufSpace(&r300
->radeon
, 421 * 3, __FUNCTION__
);
556 r300EmitClearState(ctx
);
557 rrbd
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
558 if (rrbd
&& (flags
& BUFFER_BIT_DEPTH
))
559 bits
|= CLEARBUFFER_DEPTH
;
561 if (rrbd
&& (flags
& BUFFER_BIT_STENCIL
))
562 bits
|= CLEARBUFFER_STENCIL
;
564 if (flags
& BUFFER_BIT_COLOR0
) {
565 rrb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_COLOR0
);
566 r300ClearBuffer(r300
, CLEARBUFFER_COLOR
, rrb
, NULL
);
570 if (flags
& BUFFER_BIT_FRONT_LEFT
) {
571 rrb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
);
572 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, rrb
, rrbd
);
576 if (flags
& BUFFER_BIT_BACK_LEFT
) {
577 rrb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
);
578 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, rrb
, rrbd
);
583 r300ClearBuffer(r300
, bits
, NULL
, rrbd
);
591 static void r300Clear(GLcontext
* ctx
, GLbitfield mask
)
593 r300ContextPtr r300
= R300_CONTEXT(ctx
);
594 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
595 const GLuint colorMask
= *((GLuint
*) & ctx
->Color
.ColorMask
);
596 GLbitfield swrast_mask
= 0, tri_mask
= 0;
598 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
600 if (RADEON_DEBUG
& DEBUG_IOCTL
)
601 fprintf(stderr
, "r300Clear\n");
603 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
604 LOCK_HARDWARE(&r300
->radeon
);
605 UNLOCK_HARDWARE(&r300
->radeon
);
606 if (dPriv
->numClipRects
== 0)
610 /* Flush swtcl vertices if necessary, because we will change hardware
611 * state during clear. See also the state-related comment in
612 * r300EmitClearState.
617 tri_mask
|= (mask
& BUFFER_BITS_COLOR
);
621 if (mask
& BUFFER_BIT_STENCIL
) {
622 tri_mask
|= BUFFER_BIT_STENCIL
;
626 if (mask
& BUFFER_BIT_DEPTH
) {
627 tri_mask
|= BUFFER_BIT_DEPTH
;
630 /* If we're doing a tri pass for depth/stencil, include a likely color
634 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
635 GLuint bufBit
= 1 << i
;
636 if ((tri_mask
) & bufBit
) {
637 if (!fb
->Attachment
[i
].Renderbuffer
->ClassID
) {
639 swrast_mask
|= bufBit
;
644 /* SW fallback clearing */
645 swrast_mask
= mask
& ~tri_mask
;
648 if (r300
->radeon
.radeonScreen
->kernel_mm
)
649 r300UserClear(ctx
, tri_mask
);
651 r300KernelClear(ctx
, tri_mask
);
654 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
655 fprintf(stderr
, "%s: swrast clear, mask: %x\n",
656 __FUNCTION__
, swrast_mask
);
657 _swrast_Clear(ctx
, swrast_mask
);
662 void r300InitIoctlFuncs(struct dd_function_table
*functions
)
664 functions
->Clear
= r300Clear
;
665 functions
->Finish
= radeonFinish
;
666 functions
->Flush
= radeonFlush
;