2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 **************************************************************************/
35 * \author Keith Whitwell <keith@tungstengraphics.com>
37 * \author Nicolai Haehnle <prefect_@gmx.net>
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
49 #include "radeon_common.h"
50 #include "radeon_lock.h"
51 #include "r300_context.h"
52 #include "r300_ioctl.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_state.h"
55 #include "r300_vertprog.h"
56 #include "radeon_reg.h"
57 #include "r300_emit.h"
58 #include "r300_fragprog.h"
59 #include "r300_context.h"
63 #define R200_3D_DRAW_IMMD_2 0xC0003500
65 #define CLEARBUFFER_COLOR 0x1
66 #define CLEARBUFFER_DEPTH 0x2
67 #define CLEARBUFFER_STENCIL 0x4
69 static void r300ClearBuffer(r300ContextPtr r300
, int flags
,
70 struct radeon_renderbuffer
*rrb
,
71 struct radeon_renderbuffer
*rrbd
)
73 BATCH_LOCALS(&r300
->radeon
);
74 GLcontext
*ctx
= r300
->radeon
.glCtx
;
75 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
77 r300ContextPtr rmesa
= r300
;
79 if (RADEON_DEBUG
& DEBUG_IOCTL
)
80 fprintf(stderr
, "%s: buffer %p (%i,%i %ix%i)\n",
81 __FUNCTION__
, rrb
, dPriv
->x
, dPriv
->y
,
85 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
87 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
89 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
91 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
){
92 cbpitch
|= R300_COLOR_TILE_ENABLE
;
97 cp_wait(&r300
->radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
98 end_3d(&rmesa
->radeon
);
100 if (flags
& CLEARBUFFER_COLOR
) {
102 BEGIN_BATCH_NO_AUTOSTATE(6);
103 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
104 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
105 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0
, cbpitch
);
109 if (flags
& (CLEARBUFFER_DEPTH
| CLEARBUFFER_STENCIL
)) {
111 cbpitch
= (rrbd
->pitch
/ rrbd
->cpp
);
112 if (rrbd
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
){
113 cbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
115 if (rrbd
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
116 cbpitch
|= R300_DEPTHMICROTILE_TILED
;
118 BEGIN_BATCH_NO_AUTOSTATE(6);
119 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
120 OUT_BATCH_RELOC(0, rrbd
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
121 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH
, cbpitch
);
125 BEGIN_BATCH_NO_AUTOSTATE(6);
126 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK
, 1);
127 if (flags
& CLEARBUFFER_COLOR
) {
128 OUT_BATCH((ctx
->Color
.ColorMask
[BCOMP
] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0
: 0) |
129 (ctx
->Color
.ColorMask
[GCOMP
] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0
: 0) |
130 (ctx
->Color
.ColorMask
[RCOMP
] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0
: 0) |
131 (ctx
->Color
.ColorMask
[ACOMP
] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0
: 0));
143 if (flags
& CLEARBUFFER_DEPTH
) {
144 t1
|= R300_Z_ENABLE
| R300_Z_WRITE_ENABLE
;
146 (R300_ZS_ALWAYS
<< R300_Z_FUNC_SHIFT
);
149 if (flags
& CLEARBUFFER_STENCIL
) {
150 t1
|= R300_STENCIL_ENABLE
;
153 R300_S_FRONT_FUNC_SHIFT
) |
155 R300_S_FRONT_SFAIL_OP_SHIFT
) |
157 R300_S_FRONT_ZPASS_OP_SHIFT
) |
159 R300_S_FRONT_ZFAIL_OP_SHIFT
);
162 OUT_BATCH_REGSEQ(R300_ZB_CNTL
, 3);
165 OUT_BATCH(((ctx
->Stencil
.WriteMask
[0] & R300_STENCILREF_MASK
) <<
166 R300_STENCILWRITEMASK_SHIFT
) |
167 (ctx
->Stencil
.Clear
& R300_STENCILREF_MASK
));
171 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
172 BEGIN_BATCH_NO_AUTOSTATE(9);
173 OUT_BATCH(cmdpacket3(r300
->radeon
.radeonScreen
, R300_CMD_PACKET3_CLEAR
));
174 OUT_BATCH_FLOAT32(dPriv
->w
/ 2.0);
175 OUT_BATCH_FLOAT32(dPriv
->h
/ 2.0);
176 OUT_BATCH_FLOAT32(ctx
->Depth
.Clear
);
177 OUT_BATCH_FLOAT32(1.0);
178 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[0]);
179 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[1]);
180 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[2]);
181 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[3]);
184 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2
, 8));
185 OUT_BATCH(R300_PRIM_TYPE_POINT
| R300_PRIM_WALK_RING
|
186 (1 << R300_PRIM_NUM_VERTICES_SHIFT
));
187 OUT_BATCH_FLOAT32(dPriv
->w
/ 2.0);
188 OUT_BATCH_FLOAT32(dPriv
->h
/ 2.0);
189 OUT_BATCH_FLOAT32(ctx
->Depth
.Clear
);
190 OUT_BATCH_FLOAT32(1.0);
191 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[0]);
192 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[1]);
193 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[2]);
194 OUT_BATCH_FLOAT32(ctx
->Color
.ClearColor
[3]);
197 r300EmitCacheFlush(rmesa
);
198 cp_wait(&r300
->radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
200 R300_STATECHANGE(r300
, cb
);
201 R300_STATECHANGE(r300
, cmk
);
202 R300_STATECHANGE(r300
, zs
);
205 static void r300EmitClearState(GLcontext
* ctx
)
207 r300ContextPtr r300
= R300_CONTEXT(ctx
);
208 BATCH_LOCALS(&r300
->radeon
);
209 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
215 if (!(r300
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
))
218 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
221 /* State atom dirty tracking is a little subtle here.
223 * On the one hand, we need to make sure base state is emitted
224 * here if we start with an empty batch buffer, otherwise clear
225 * works incorrectly with multiple processes. Therefore, the first
226 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
228 * On the other hand, implicit state emission clears the state atom
229 * dirty bits, so we have to call R300_STATECHANGE later than the
232 * The final trickiness is that, because we change state, we need
233 * to ensure that any stored swtcl primitives are flushed properly
234 * before we start changing state. See the R300_NEWPRIM in r300Clear
238 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0
, 1);
240 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
241 ((R300_LAST_VEC
| (2 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
243 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
244 ((R300_LAST_VEC
| (1 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
246 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND
, 0);
247 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0
,
248 ((((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
249 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
250 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
251 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
252 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
253 << R300_SWIZZLE0_SHIFT
) |
254 (((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
255 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
256 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
257 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
258 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
259 << R300_SWIZZLE1_SHIFT
)));
261 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
262 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL
, 2);
263 OUT_BATCH((R300_SEL_USER_COLOR_0
<< R300_COLOR_0_ASSEMBLY_SHIFT
));
264 OUT_BATCH(R300_INPUT_CNTL_POS
| R300_INPUT_CNTL_COLOR
| R300_INPUT_CNTL_TC0
);
266 /* comes from fglrx startup of clear */
267 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL
, 2);
268 OUT_BATCH(R300_VTX_W0_FMT
| R300_VPORT_X_SCALE_ENA
|
269 R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Y_SCALE_ENA
|
270 R300_VPORT_Y_OFFSET_ENA
| R300_VPORT_Z_SCALE_ENA
|
271 R300_VPORT_Z_OFFSET_ENA
);
274 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL
, 0xaaaaaaaa);
276 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
277 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
|
278 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
);
279 OUT_BATCH(0); /* no textures */
281 OUT_BATCH_REGVAL(R300_TX_ENABLE
, 0);
283 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE
, 6);
284 OUT_BATCH_FLOAT32(1.0);
285 OUT_BATCH_FLOAT32(dPriv
->x
);
286 OUT_BATCH_FLOAT32(1.0);
287 OUT_BATCH_FLOAT32(dPriv
->y
);
288 OUT_BATCH_FLOAT32(1.0);
289 OUT_BATCH_FLOAT32(0.0);
291 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC
, 0);
293 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND
, 2);
298 R300_STATECHANGE(r300
, vir
[0]);
299 R300_STATECHANGE(r300
, fogs
);
300 R300_STATECHANGE(r300
, vir
[1]);
301 R300_STATECHANGE(r300
, vic
);
302 R300_STATECHANGE(r300
, vte
);
303 R300_STATECHANGE(r300
, vof
);
304 R300_STATECHANGE(r300
, txe
);
305 R300_STATECHANGE(r300
, vpt
);
306 R300_STATECHANGE(r300
, at
);
307 R300_STATECHANGE(r300
, bld
);
308 R300_STATECHANGE(r300
, ps
);
311 R300_STATECHANGE(r300
, vap_clip_cntl
);
313 BEGIN_BATCH_NO_AUTOSTATE(2);
314 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL
, R300_PS_UCP_MODE_CLIP_AS_TRIFAN
| R300_CLIP_DISABLE
);
318 BEGIN_BATCH_NO_AUTOSTATE(2);
319 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE
,
320 ((dPriv
->w
* 6) << R300_POINTSIZE_X_SHIFT
) |
321 ((dPriv
->h
* 6) << R300_POINTSIZE_Y_SHIFT
));
325 R300_STATECHANGE(r300
, ri
);
326 R300_STATECHANGE(r300
, rc
);
327 R300_STATECHANGE(r300
, rr
);
330 OUT_BATCH_REGSEQ(R300_RS_IP_0
, 8);
331 for (i
= 0; i
< 8; ++i
)
332 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
334 OUT_BATCH_REGSEQ(R300_RS_COUNT
, 2);
335 OUT_BATCH((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
338 OUT_BATCH_REGVAL(R300_RS_INST_0
, R300_RS_INST_COL_CN_WRITE
);
341 R300_STATECHANGE(r300
, ri
);
342 R300_STATECHANGE(r300
, rc
);
343 R300_STATECHANGE(r300
, rr
);
346 OUT_BATCH_REGSEQ(R500_RS_IP_0
, 8);
347 for (i
= 0; i
< 8; ++i
) {
348 OUT_BATCH((R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_S_SHIFT
) |
349 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_T_SHIFT
) |
350 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_R_SHIFT
) |
351 (R500_RS_IP_PTR_K1
<< R500_RS_IP_TEX_PTR_Q_SHIFT
));
354 OUT_BATCH_REGSEQ(R300_RS_COUNT
, 2);
355 OUT_BATCH((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
358 OUT_BATCH_REGVAL(R500_RS_INST_0
, R500_RS_INST_COL_CN_WRITE
);
363 R300_STATECHANGE(r300
, fp
);
364 R300_STATECHANGE(r300
, fpi
[0]);
365 R300_STATECHANGE(r300
, fpi
[1]);
366 R300_STATECHANGE(r300
, fpi
[2]);
367 R300_STATECHANGE(r300
, fpi
[3]);
370 OUT_BATCH_REGSEQ(R300_US_CONFIG
, 3);
374 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0
, 4);
378 OUT_BATCH(R300_RGBA_OUT
);
380 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0
,
381 FP_INSTRC(MAD
, FP_ARGC(SRC0C_XYZ
), FP_ARGC(ONE
), FP_ARGC(ZERO
)));
382 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0
,
383 FP_SELC(0, NO
, XYZ
, FP_TMP(0), 0, 0));
384 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0
,
385 FP_INSTRA(MAD
, FP_ARGA(SRC0A
), FP_ARGA(ONE
), FP_ARGA(ZERO
)));
386 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0
,
387 FP_SELA(0, NO
, W
, FP_TMP(0), 0, 0));
390 struct radeon_state_atom r500fp
;
393 R300_STATECHANGE(r300
, fp
);
394 R300_STATECHANGE(r300
, r500fp
);
397 OUT_BATCH_REGSEQ(R500_US_CONFIG
, 2);
398 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
400 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR
, 3);
401 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
402 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
403 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
406 r500fp
.check
= check_r500fp
;
408 r500fp
.cmd
[0] = cmdr500fp(r300
->radeon
.radeonScreen
, 0, 1, 0, 0);
409 r500fp
.cmd
[1] = R500_INST_TYPE_OUT
|
410 R500_INST_TEX_SEM_WAIT
|
412 R500_INST_RGB_OMASK_R
|
413 R500_INST_RGB_OMASK_G
|
414 R500_INST_RGB_OMASK_B
|
415 R500_INST_ALPHA_OMASK
|
416 R500_INST_RGB_CLAMP
|
417 R500_INST_ALPHA_CLAMP
;
418 r500fp
.cmd
[2] = R500_RGB_ADDR0(0) |
420 R500_RGB_ADDR1_CONST
|
422 R500_RGB_ADDR2_CONST
;
423 r500fp
.cmd
[3] = R500_ALPHA_ADDR0(0) |
424 R500_ALPHA_ADDR1(0) |
425 R500_ALPHA_ADDR1_CONST
|
426 R500_ALPHA_ADDR2(0) |
427 R500_ALPHA_ADDR2_CONST
;
428 r500fp
.cmd
[4] = R500_ALU_RGB_SEL_A_SRC0
|
429 R500_ALU_RGB_R_SWIZ_A_R
|
430 R500_ALU_RGB_G_SWIZ_A_G
|
431 R500_ALU_RGB_B_SWIZ_A_B
|
432 R500_ALU_RGB_SEL_B_SRC0
|
433 R500_ALU_RGB_R_SWIZ_B_R
|
434 R500_ALU_RGB_B_SWIZ_B_G
|
435 R500_ALU_RGB_G_SWIZ_B_B
;
436 r500fp
.cmd
[5] = R500_ALPHA_OP_CMP
|
437 R500_ALPHA_SWIZ_A_A
|
439 r500fp
.cmd
[6] = R500_ALU_RGBA_OP_CMP
|
440 R500_ALU_RGBA_R_SWIZ_0
|
441 R500_ALU_RGBA_G_SWIZ_0
|
442 R500_ALU_RGBA_B_SWIZ_0
|
443 R500_ALU_RGBA_A_SWIZ_0
;
446 emit_r500fp(ctx
, &r500fp
);
450 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
454 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
455 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
456 (12 << R300_VF_MAX_VTX_NUM_SHIFT
));
457 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
458 vap_cntl
|= R500_TCL_STATE_OPTIMIZATION
;
460 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
461 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
462 (5 << R300_VF_MAX_VTX_NUM_SHIFT
));
465 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV515
)
466 vap_cntl
|= (2 << R300_PVS_NUM_FPUS_SHIFT
);
467 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) ||
468 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV560
) ||
469 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV570
))
470 vap_cntl
|= (5 << R300_PVS_NUM_FPUS_SHIFT
);
471 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV410
) ||
472 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R420
))
473 vap_cntl
|= (6 << R300_PVS_NUM_FPUS_SHIFT
);
474 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R520
) ||
475 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R580
))
476 vap_cntl
|= (8 << R300_PVS_NUM_FPUS_SHIFT
);
478 vap_cntl
|= (4 << R300_PVS_NUM_FPUS_SHIFT
);
480 R300_STATECHANGE(r300
, vap_cntl
);
483 OUT_BATCH_REGVAL(R300_VAP_CNTL
, vap_cntl
);
487 struct radeon_state_atom vpu
;
489 R300_STATECHANGE(r300
, pvs
);
490 R300_STATECHANGE(r300
, vpi
);
493 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
494 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT
) |
495 (0 << R300_PVS_XYZW_VALID_INST_SHIFT
) |
496 (1 << R300_PVS_LAST_INST_SHIFT
));
497 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT
) |
498 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT
));
499 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT
);
502 vpu
.check
= check_vpu
;
504 vpu
.cmd
[0] = cmdvpu(r300
->radeon
.radeonScreen
, 0, 2);
506 vpu
.cmd
[1] = PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
,
507 0, 0xf, PVS_DST_REG_OUT
);
508 vpu
.cmd
[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X
, PVS_SRC_SELECT_Y
,
509 PVS_SRC_SELECT_Z
, PVS_SRC_SELECT_W
,
510 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
511 vpu
.cmd
[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0
,
512 PVS_SRC_SELECT_FORCE_0
,
513 PVS_SRC_SELECT_FORCE_0
,
514 PVS_SRC_SELECT_FORCE_0
,
515 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
518 vpu
.cmd
[5] = PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
, 1, 0xf,
520 vpu
.cmd
[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X
,
521 PVS_SRC_SELECT_Y
, PVS_SRC_SELECT_Z
,
522 PVS_SRC_SELECT_W
, PVS_SRC_REG_INPUT
,
525 vpu
.cmd
[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0
,
526 PVS_SRC_SELECT_FORCE_0
,
527 PVS_SRC_SELECT_FORCE_0
,
528 PVS_SRC_SELECT_FORCE_0
,
529 PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
);
532 r300
->vap_flush_needed
= GL_TRUE
;
540 static void r300Clear(GLcontext
* ctx
, GLbitfield mask
)
542 r300ContextPtr r300
= R300_CONTEXT(ctx
);
543 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
544 struct radeon_framebuffer
*rfb
= dPriv
->driverPrivate
;
545 struct radeon_renderbuffer
*rrb
;
546 struct radeon_renderbuffer
*rrbd
;
550 if (RADEON_DEBUG
& DEBUG_IOCTL
)
551 fprintf(stderr
, "r300Clear\n");
554 LOCK_HARDWARE(&r300
->radeon
);
555 UNLOCK_HARDWARE(&r300
->radeon
);
556 if (dPriv
->numClipRects
== 0)
560 /* Flush swtcl vertices if necessary, because we will change hardware
561 * state during clear. See also the state-related comment in
562 * r300EmitClearState.
566 if (mask
& BUFFER_BIT_FRONT_LEFT
) {
567 flags
|= BUFFER_BIT_FRONT_LEFT
;
568 mask
&= ~BUFFER_BIT_FRONT_LEFT
;
571 if (mask
& BUFFER_BIT_BACK_LEFT
) {
572 flags
|= BUFFER_BIT_BACK_LEFT
;
573 mask
&= ~BUFFER_BIT_BACK_LEFT
;
576 if (mask
& BUFFER_BIT_DEPTH
) {
577 bits
|= CLEARBUFFER_DEPTH
;
578 mask
&= ~BUFFER_BIT_DEPTH
;
581 if ((mask
& BUFFER_BIT_STENCIL
) && r300
->radeon
.state
.stencil
.hwBuffer
) {
582 bits
|= CLEARBUFFER_STENCIL
;
583 mask
&= ~BUFFER_BIT_STENCIL
;
587 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
588 fprintf(stderr
, "%s: swrast clear, mask: %x\n",
590 _swrast_Clear(ctx
, mask
);
593 /* Make sure it fits there. */
594 rcommonEnsureCmdBufSpace(&r300
->radeon
, 421 * 3, __FUNCTION__
);
596 r300EmitClearState(ctx
);
597 rrbd
= (void *)rfb
->base
.Attachment
[BUFFER_DEPTH
].Renderbuffer
;
599 if (flags
& BUFFER_BIT_FRONT_LEFT
) {
600 rrb
= (void *)rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
;
601 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, rrb
, rrbd
);
605 if (flags
& BUFFER_BIT_BACK_LEFT
) {
606 rrb
= (void *)rfb
->base
.Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
;
607 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, rrb
, rrbd
);
612 r300ClearBuffer(r300
, bits
, NULL
, rrbd
);
617 void r300InitIoctlFuncs(struct dd_function_table
*functions
)
619 functions
->Clear
= r300Clear
;
620 functions
->Finish
= radeonFinish
;
621 functions
->Flush
= radeonFlush
;