2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 **************************************************************************/
35 * \author Keith Whitwell <keith@tungstengraphics.com>
37 * \author Nicolai Haehnle <prefect_@gmx.net>
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
49 #include "r300_context.h"
50 #include "radeon_ioctl.h"
51 #include "r300_ioctl.h"
52 #include "r300_cmdbuf.h"
53 #include "r300_state.h"
54 #include "r300_vertprog.h"
55 #include "radeon_reg.h"
56 #include "r300_emit.h"
57 #include "r300_fragprog.h"
61 #define CLEARBUFFER_COLOR 0x1
62 #define CLEARBUFFER_DEPTH 0x2
63 #define CLEARBUFFER_STENCIL 0x4
65 static void r300ClearBuffer(r300ContextPtr r300
, int flags
, int buffer
)
67 GLcontext
*ctx
= r300
->radeon
.glCtx
;
68 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
69 GLuint cboffset
, cbpitch
;
70 drm_r300_cmd_header_t
*cmd2
;
73 drm_radeon_cmd_header_t
*cmd
= NULL
;
74 r300ContextPtr rmesa
= r300
;
76 if (RADEON_DEBUG
& DEBUG_IOCTL
)
77 fprintf(stderr
, "%s: %s buffer (%i,%i %ix%i)\n",
78 __FUNCTION__
, buffer
? "back" : "front",
79 dPriv
->x
, dPriv
->y
, dPriv
->w
, dPriv
->h
);
82 cboffset
= r300
->radeon
.radeonScreen
->backOffset
;
83 cbpitch
= r300
->radeon
.radeonScreen
->backPitch
;
85 cboffset
= r300
->radeon
.radeonScreen
->frontOffset
;
86 cbpitch
= r300
->radeon
.radeonScreen
->frontPitch
;
89 cboffset
+= r300
->radeon
.radeonScreen
->fbLocation
;
91 cp_wait(r300
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
94 R300_STATECHANGE(r300
, cb
);
95 reg_start(R300_RB3D_COLOROFFSET0
, 0);
98 if (r300
->radeon
.radeonScreen
->cpp
== 4)
99 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
101 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
103 if (r300
->radeon
.sarea
->tiling_enabled
)
104 cbpitch
|= R300_COLOR_TILE_ENABLE
;
106 reg_start(R300_RB3D_COLORPITCH0
, 0);
109 R300_STATECHANGE(r300
, cmk
);
110 reg_start(RB3D_COLOR_CHANNEL_MASK
, 0);
112 if (flags
& CLEARBUFFER_COLOR
) {
113 e32((ctx
->Color
.ColorMask
[BCOMP
] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0
: 0) |
114 (ctx
->Color
.ColorMask
[GCOMP
] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0
: 0) |
115 (ctx
->Color
.ColorMask
[RCOMP
] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0
: 0) |
116 (ctx
->Color
.ColorMask
[ACOMP
] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0
: 0));
121 R300_STATECHANGE(r300
, zs
);
122 reg_start(R300_ZB_CNTL
, 2);
130 if (flags
& CLEARBUFFER_DEPTH
) {
131 t1
|= R300_Z_ENABLE
| R300_Z_WRITE_ENABLE
;
133 (R300_ZS_ALWAYS
<< R300_Z_FUNC_SHIFT
);
136 if (flags
& CLEARBUFFER_STENCIL
) {
137 t1
|= R300_STENCIL_ENABLE
;
140 R300_S_FRONT_FUNC_SHIFT
) |
142 R300_S_FRONT_SFAIL_OP_SHIFT
) |
144 R300_S_FRONT_ZPASS_OP_SHIFT
) |
146 R300_S_FRONT_ZFAIL_OP_SHIFT
);
151 e32(((ctx
->Stencil
.WriteMask
[0] & R300_STENCILREF_MASK
) << R300_STENCILWRITEMASK_SHIFT
) |
152 (ctx
->Stencil
.Clear
& R300_STENCILREF_MASK
));
155 cmd2
= (drm_r300_cmd_header_t
*) r300AllocCmdBuf(r300
, 9, __FUNCTION__
);
156 cmd2
[0].packet3
.cmd_type
= R300_CMD_PACKET3
;
157 cmd2
[0].packet3
.packet
= R300_CMD_PACKET3_CLEAR
;
158 cmd2
[1].u
= r300PackFloat32(dPriv
->w
/ 2.0);
159 cmd2
[2].u
= r300PackFloat32(dPriv
->h
/ 2.0);
160 cmd2
[3].u
= r300PackFloat32(ctx
->Depth
.Clear
);
161 cmd2
[4].u
= r300PackFloat32(1.0);
162 cmd2
[5].u
= r300PackFloat32(ctx
->Color
.ClearColor
[0]);
163 cmd2
[6].u
= r300PackFloat32(ctx
->Color
.ClearColor
[1]);
164 cmd2
[7].u
= r300PackFloat32(ctx
->Color
.ClearColor
[2]);
165 cmd2
[8].u
= r300PackFloat32(ctx
->Color
.ClearColor
[3]);
167 r300EmitCacheFlush(rmesa
);
168 cp_wait(rmesa
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
171 static void r300EmitClearState(GLcontext
* ctx
)
173 r300ContextPtr r300
= R300_CONTEXT(ctx
);
174 r300ContextPtr rmesa
= r300
;
175 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
177 int cmd_reserved
= 0;
179 drm_radeon_cmd_header_t
*cmd
= NULL
;
184 if (!(r300
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
))
187 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
191 /* FIXME: the values written to R300_VAP_INPUT_ROUTE_0_0 and
192 * R300_VAP_INPUT_ROUTE_0_1 are in fact known, however, the values are
193 * quite complex; see the functions in r300_emit.c.
195 * I believe it would be a good idea to extend the functions in
196 * r300_emit.c so that they can be used to setup the default values for
197 * these registers, as well as the actual values used for rendering.
199 R300_STATECHANGE(r300
, vir
[0]);
200 reg_start(R300_VAP_PROG_STREAM_CNTL_0
, 0);
202 e32(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
203 ((R300_LAST_VEC
| (2 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
205 e32(((((0 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_0_SHIFT
) |
206 ((R300_LAST_VEC
| (1 << R300_DST_VEC_LOC_SHIFT
) | R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
)));
209 R300_STATECHANGE(r300
, fogs
);
210 reg_start(R300_FG_FOG_BLEND
, 0);
213 R300_STATECHANGE(r300
, vir
[1]);
214 reg_start(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 0);
215 e32(((((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
216 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
217 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
218 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
219 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
220 << R300_SWIZZLE0_SHIFT
) |
221 (((R300_SWIZZLE_SELECT_X
<< R300_SWIZZLE_SELECT_X_SHIFT
) |
222 (R300_SWIZZLE_SELECT_Y
<< R300_SWIZZLE_SELECT_Y_SHIFT
) |
223 (R300_SWIZZLE_SELECT_Z
<< R300_SWIZZLE_SELECT_Z_SHIFT
) |
224 (R300_SWIZZLE_SELECT_W
<< R300_SWIZZLE_SELECT_W_SHIFT
) |
225 ((R300_WRITE_ENA_X
| R300_WRITE_ENA_Y
| R300_WRITE_ENA_Z
| R300_WRITE_ENA_W
) << R300_WRITE_ENA_SHIFT
))
226 << R300_SWIZZLE1_SHIFT
)));
228 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
229 R300_STATECHANGE(r300
, vic
);
230 reg_start(R300_VAP_VTX_STATE_CNTL
, 1);
231 e32((R300_SEL_USER_COLOR_0
<< R300_COLOR_0_ASSEMBLY_SHIFT
));
232 e32(R300_INPUT_CNTL_POS
| R300_INPUT_CNTL_COLOR
| R300_INPUT_CNTL_TC0
);
234 R300_STATECHANGE(r300
, vte
);
235 /* comes from fglrx startup of clear */
236 reg_start(R300_SE_VTE_CNTL
, 1);
237 e32(R300_VTX_W0_FMT
| R300_VPORT_X_SCALE_ENA
|
238 R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Y_SCALE_ENA
|
239 R300_VPORT_Y_OFFSET_ENA
| R300_VPORT_Z_SCALE_ENA
|
240 R300_VPORT_Z_OFFSET_ENA
);
243 reg_start(R300_VAP_PSC_SGN_NORM_CNTL
, 0);
246 R300_STATECHANGE(r300
, vof
);
247 reg_start(R300_VAP_OUTPUT_VTX_FMT_0
, 1);
248 e32(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
|
249 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
);
250 e32(0x0); /* no textures */
252 R300_STATECHANGE(r300
, txe
);
253 reg_start(R300_TX_ENABLE
, 0);
256 R300_STATECHANGE(r300
, vpt
);
257 reg_start(R300_SE_VPORT_XSCALE
, 5);
265 R300_STATECHANGE(r300
, at
);
266 reg_start(R300_FG_ALPHA_FUNC
, 0);
269 R300_STATECHANGE(r300
, bld
);
270 reg_start(R300_RB3D_CBLEND
, 1);
275 R300_STATECHANGE(r300
, vap_clip_cntl
);
276 reg_start(R300_VAP_CLIP_CNTL
, 0);
277 e32(R300_PS_UCP_MODE_CLIP_AS_TRIFAN
| R300_CLIP_DISABLE
);
280 R300_STATECHANGE(r300
, ps
);
281 reg_start(R300_GA_POINT_SIZE
, 0);
282 e32(((dPriv
->w
* 6) << R300_POINTSIZE_X_SHIFT
) |
283 ((dPriv
->h
* 6) << R300_POINTSIZE_Y_SHIFT
));
286 R300_STATECHANGE(r300
, ri
);
287 reg_start(R300_RS_IP_0
, 7);
288 for (i
= 0; i
< 8; ++i
) {
289 e32(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
292 R300_STATECHANGE(r300
, rc
);
293 /* The second constant is needed to get glxgears display anything .. */
294 reg_start(R300_RS_COUNT
, 1);
295 e32((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
298 R300_STATECHANGE(r300
, rr
);
299 reg_start(R300_RS_INST_0
, 0);
300 e32(R300_RS_INST_COL_CN_WRITE
);
302 R300_STATECHANGE(r300
, ri
);
303 reg_start(R500_RS_IP_0
, 7);
304 for (i
= 0; i
< 8; ++i
) {
305 e32((R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_S_SHIFT
) |
306 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_T_SHIFT
) |
307 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_R_SHIFT
) |
308 (R500_RS_IP_PTR_K1
<< R500_RS_IP_TEX_PTR_Q_SHIFT
));
311 R300_STATECHANGE(r300
, rc
);
312 /* The second constant is needed to get glxgears display anything .. */
313 reg_start(R300_RS_COUNT
, 1);
314 e32((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
317 R300_STATECHANGE(r300
, rr
);
318 reg_start(R500_RS_INST_0
, 0);
319 e32(R500_RS_INST_COL_CN_WRITE
);
324 R300_STATECHANGE(r300
, fp
);
325 reg_start(R300_US_CONFIG
, 2);
329 reg_start(R300_US_CODE_ADDR_0
, 3);
335 R300_STATECHANGE(r300
, fpi
[0]);
336 R300_STATECHANGE(r300
, fpi
[1]);
337 R300_STATECHANGE(r300
, fpi
[2]);
338 R300_STATECHANGE(r300
, fpi
[3]);
340 reg_start(R300_US_ALU_RGB_INST_0
, 0);
341 e32(FP_INSTRC(MAD
, FP_ARGC(SRC0C_XYZ
), FP_ARGC(ONE
), FP_ARGC(ZERO
)));
343 reg_start(R300_US_ALU_RGB_ADDR_0
, 0);
344 e32(FP_SELC(0, NO
, XYZ
, FP_TMP(0), 0, 0));
346 reg_start(R300_US_ALU_ALPHA_INST_0
, 0);
347 e32(FP_INSTRA(MAD
, FP_ARGA(SRC0A
), FP_ARGA(ONE
), FP_ARGA(ZERO
)));
349 reg_start(R300_US_ALU_ALPHA_ADDR_0
, 0);
350 e32(FP_SELA(0, NO
, W
, FP_TMP(0), 0, 0));
352 R300_STATECHANGE(r300
, fp
);
353 reg_start(R500_US_CONFIG
, 1);
354 e32(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
356 reg_start(R500_US_CODE_ADDR
, 2);
357 e32(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
358 e32(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
359 e32(R500_US_CODE_OFFSET_ADDR(0));
361 R300_STATECHANGE(r300
, r500fp
);
362 r500fp_start_fragment(0, 6);
364 e32(R500_INST_TYPE_OUT
|
365 R500_INST_TEX_SEM_WAIT
|
367 R500_INST_RGB_OMASK_R
|
368 R500_INST_RGB_OMASK_G
|
369 R500_INST_RGB_OMASK_B
|
370 R500_INST_ALPHA_OMASK
|
371 R500_INST_RGB_CLAMP
|
372 R500_INST_ALPHA_CLAMP
);
374 e32(R500_RGB_ADDR0(0) |
376 R500_RGB_ADDR1_CONST
|
378 R500_RGB_ADDR2_CONST
);
380 e32(R500_ALPHA_ADDR0(0) |
381 R500_ALPHA_ADDR1(0) |
382 R500_ALPHA_ADDR1_CONST
|
383 R500_ALPHA_ADDR2(0) |
384 R500_ALPHA_ADDR2_CONST
);
386 e32(R500_ALU_RGB_SEL_A_SRC0
|
387 R500_ALU_RGB_R_SWIZ_A_R
|
388 R500_ALU_RGB_G_SWIZ_A_G
|
389 R500_ALU_RGB_B_SWIZ_A_B
|
390 R500_ALU_RGB_SEL_B_SRC0
|
391 R500_ALU_RGB_R_SWIZ_B_R
|
392 R500_ALU_RGB_B_SWIZ_B_G
|
393 R500_ALU_RGB_G_SWIZ_B_B
);
395 e32(R500_ALPHA_OP_CMP
|
396 R500_ALPHA_SWIZ_A_A
|
397 R500_ALPHA_SWIZ_B_A
);
399 e32(R500_ALU_RGBA_OP_CMP
|
400 R500_ALU_RGBA_R_SWIZ_0
|
401 R500_ALU_RGBA_G_SWIZ_0
|
402 R500_ALU_RGBA_B_SWIZ_0
|
403 R500_ALU_RGBA_A_SWIZ_0
);
406 reg_start(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
409 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
410 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
411 (12 << R300_VF_MAX_VTX_NUM_SHIFT
));
412 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
413 vap_cntl
|= R500_TCL_STATE_OPTIMIZATION
;
415 vap_cntl
= ((10 << R300_PVS_NUM_SLOTS_SHIFT
) |
416 (5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
417 (5 << R300_VF_MAX_VTX_NUM_SHIFT
));
419 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV515
)
420 vap_cntl
|= (2 << R300_PVS_NUM_FPUS_SHIFT
);
421 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) ||
422 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV560
) ||
423 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV570
))
424 vap_cntl
|= (5 << R300_PVS_NUM_FPUS_SHIFT
);
425 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV410
) ||
426 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R420
))
427 vap_cntl
|= (6 << R300_PVS_NUM_FPUS_SHIFT
);
428 else if ((r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R520
) ||
429 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R580
))
430 vap_cntl
|= (8 << R300_PVS_NUM_FPUS_SHIFT
);
432 vap_cntl
|= (4 << R300_PVS_NUM_FPUS_SHIFT
);
434 R300_STATECHANGE(rmesa
, vap_cntl
);
435 reg_start(R300_VAP_CNTL
, 0);
439 R300_STATECHANGE(r300
, pvs
);
440 reg_start(R300_VAP_PVS_CODE_CNTL_0
, 2);
442 e32((0 << R300_PVS_FIRST_INST_SHIFT
) |
443 (0 << R300_PVS_XYZW_VALID_INST_SHIFT
) |
444 (1 << R300_PVS_LAST_INST_SHIFT
));
445 e32((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT
) |
446 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT
));
447 e32(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT
);
449 R300_STATECHANGE(r300
, vpi
);
450 vsf_start_fragment(0x0, 8);
452 e32(PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
, 0, 0xf, PVS_DST_REG_OUT
));
453 e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X
, PVS_SRC_SELECT_Y
, PVS_SRC_SELECT_Z
, PVS_SRC_SELECT_W
, PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
));
454 e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
));
457 e32(PVS_OP_DST_OPERAND(VE_ADD
, GL_FALSE
, GL_FALSE
, 1, 0xf, PVS_DST_REG_OUT
));
458 e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X
, PVS_SRC_SELECT_Y
, PVS_SRC_SELECT_Z
, PVS_SRC_SELECT_W
, PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
));
459 e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_SELECT_FORCE_0
, PVS_SRC_REG_INPUT
, VSF_FLAG_NONE
));
467 static void r300Clear(GLcontext
* ctx
, GLbitfield mask
)
469 r300ContextPtr r300
= R300_CONTEXT(ctx
);
470 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
475 if (RADEON_DEBUG
& DEBUG_IOCTL
)
476 fprintf(stderr
, "r300Clear\n");
479 LOCK_HARDWARE(&r300
->radeon
);
480 UNLOCK_HARDWARE(&r300
->radeon
);
481 if (dPriv
->numClipRects
== 0)
485 if (mask
& BUFFER_BIT_FRONT_LEFT
) {
486 flags
|= BUFFER_BIT_FRONT_LEFT
;
487 mask
&= ~BUFFER_BIT_FRONT_LEFT
;
490 if (mask
& BUFFER_BIT_BACK_LEFT
) {
491 flags
|= BUFFER_BIT_BACK_LEFT
;
492 mask
&= ~BUFFER_BIT_BACK_LEFT
;
495 if (mask
& BUFFER_BIT_DEPTH
) {
496 bits
|= CLEARBUFFER_DEPTH
;
497 mask
&= ~BUFFER_BIT_DEPTH
;
500 if ((mask
& BUFFER_BIT_STENCIL
) && r300
->state
.stencil
.hw_stencil
) {
501 bits
|= CLEARBUFFER_STENCIL
;
502 mask
&= ~BUFFER_BIT_STENCIL
;
506 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
507 fprintf(stderr
, "%s: swrast clear, mask: %x\n",
509 _swrast_Clear(ctx
, mask
);
512 swapped
= r300
->radeon
.sarea
->pfCurrentPage
== 1;
514 /* Make sure it fits there. */
515 r300EnsureCmdBufSpace(r300
, 421 * 3, __FUNCTION__
);
517 r300EmitClearState(ctx
);
519 if (flags
& BUFFER_BIT_FRONT_LEFT
) {
520 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, swapped
);
524 if (flags
& BUFFER_BIT_BACK_LEFT
) {
525 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, swapped
^ 1);
530 r300ClearBuffer(r300
, bits
, 0);
534 void r300Flush(GLcontext
* ctx
)
536 r300ContextPtr rmesa
= R300_CONTEXT(ctx
);
538 if (RADEON_DEBUG
& DEBUG_IOCTL
)
539 fprintf(stderr
, "%s\n", __FUNCTION__
);
541 if (rmesa
->dma
.flush
)
542 rmesa
->dma
.flush( rmesa
);
544 if (rmesa
->cmdbuf
.count_used
> rmesa
->cmdbuf
.count_reemit
)
545 r300FlushCmdBuf(rmesa
, __FUNCTION__
);
549 #include "r300_mem.h"
551 void r300RefillCurrentDmaRegion(r300ContextPtr rmesa
, int size
)
553 struct r300_dma_buffer
*dmabuf
;
554 size
= MAX2(size
, RADEON_BUFFER_SIZE
* 16);
556 if (RADEON_DEBUG
& (DEBUG_IOCTL
| DEBUG_DMA
))
557 fprintf(stderr
, "%s\n", __FUNCTION__
);
559 if (rmesa
->dma
.flush
) {
560 rmesa
->dma
.flush(rmesa
);
563 if (rmesa
->dma
.current
.buf
) {
565 r300_mem_use(rmesa
, rmesa
->dma
.current
.buf
->id
);
567 r300ReleaseDmaRegion(rmesa
, &rmesa
->dma
.current
, __FUNCTION__
);
569 if (rmesa
->dma
.nr_released_bufs
> 4)
570 r300FlushCmdBuf(rmesa
, __FUNCTION__
);
572 dmabuf
= CALLOC_STRUCT(r300_dma_buffer
);
573 dmabuf
->buf
= (void *)1; /* hack */
574 dmabuf
->refcount
= 1;
576 dmabuf
->id
= r300_mem_alloc(rmesa
, 4, size
);
577 if (dmabuf
->id
== 0) {
578 LOCK_HARDWARE(&rmesa
->radeon
); /* no need to validate */
580 r300FlushCmdBufLocked(rmesa
, __FUNCTION__
);
581 radeonWaitForIdleLocked(&rmesa
->radeon
);
583 dmabuf
->id
= r300_mem_alloc(rmesa
, 4, size
);
585 UNLOCK_HARDWARE(&rmesa
->radeon
);
587 if (dmabuf
->id
== 0) {
589 "Error: Could not get dma buffer... exiting\n");
594 rmesa
->dma
.current
.buf
= dmabuf
;
595 rmesa
->dma
.current
.address
= r300_mem_ptr(rmesa
, dmabuf
->id
);
596 rmesa
->dma
.current
.end
= size
;
597 rmesa
->dma
.current
.start
= 0;
598 rmesa
->dma
.current
.ptr
= 0;
601 void r300ReleaseDmaRegion(r300ContextPtr rmesa
,
602 struct r300_dma_region
*region
, const char *caller
)
604 if (RADEON_DEBUG
& DEBUG_IOCTL
)
605 fprintf(stderr
, "%s from %s\n", __FUNCTION__
, caller
);
610 if (rmesa
->dma
.flush
)
611 rmesa
->dma
.flush(rmesa
);
613 if (--region
->buf
->refcount
== 0) {
614 r300_mem_free(rmesa
, region
->buf
->id
);
616 rmesa
->dma
.nr_released_bufs
++;
623 /* Allocates a region from rmesa->dma.current. If there isn't enough
624 * space in current, grab a new buffer (and discard what was left of current)
626 void r300AllocDmaRegion(r300ContextPtr rmesa
,
627 struct r300_dma_region
*region
,
628 int bytes
, int alignment
)
630 if (RADEON_DEBUG
& DEBUG_IOCTL
)
631 fprintf(stderr
, "%s %d\n", __FUNCTION__
, bytes
);
633 if (rmesa
->dma
.flush
)
634 rmesa
->dma
.flush(rmesa
);
637 r300ReleaseDmaRegion(rmesa
, region
, __FUNCTION__
);
640 rmesa
->dma
.current
.start
= rmesa
->dma
.current
.ptr
=
641 (rmesa
->dma
.current
.ptr
+ alignment
) & ~alignment
;
643 if (rmesa
->dma
.current
.ptr
+ bytes
> rmesa
->dma
.current
.end
)
644 r300RefillCurrentDmaRegion(rmesa
, (bytes
+ 0x7) & ~0x7);
646 region
->start
= rmesa
->dma
.current
.start
;
647 region
->ptr
= rmesa
->dma
.current
.start
;
648 region
->end
= rmesa
->dma
.current
.start
+ bytes
;
649 region
->address
= rmesa
->dma
.current
.address
;
650 region
->buf
= rmesa
->dma
.current
.buf
;
651 region
->buf
->refcount
++;
653 rmesa
->dma
.current
.ptr
+= bytes
; /* bug - if alignment > 7 */
654 rmesa
->dma
.current
.start
=
655 rmesa
->dma
.current
.ptr
= (rmesa
->dma
.current
.ptr
+ 0x7) & ~0x7;
657 assert(rmesa
->dma
.current
.ptr
<= rmesa
->dma
.current
.end
);
661 static void r300RefillCurrentDmaRegion(r300ContextPtr rmesa
)
663 struct r300_dma_buffer
*dmabuf
;
664 int fd
= rmesa
->radeon
.dri
.fd
;
670 if (RADEON_DEBUG
& (DEBUG_IOCTL
| DEBUG_DMA
))
671 fprintf(stderr
, "%s\n", __FUNCTION__
);
673 if (rmesa
->dma
.flush
) {
674 rmesa
->dma
.flush(rmesa
);
677 if (rmesa
->dma
.current
.buf
)
678 r300ReleaseDmaRegion(rmesa
, &rmesa
->dma
.current
, __FUNCTION__
);
680 if (rmesa
->dma
.nr_released_bufs
> 4)
681 r300FlushCmdBuf(rmesa
, __FUNCTION__
);
683 dma
.context
= rmesa
->radeon
.dri
.hwContext
;
685 dma
.send_list
= NULL
;
686 dma
.send_sizes
= NULL
;
688 dma
.request_count
= 1;
689 dma
.request_size
= RADEON_BUFFER_SIZE
;
690 dma
.request_list
= &index
;
691 dma
.request_sizes
= &size
;
692 dma
.granted_count
= 0;
694 LOCK_HARDWARE(&rmesa
->radeon
); /* no need to validate */
696 ret
= drmDMA(fd
, &dma
);
699 /* Try to release some buffers and wait until we can't get any more */
700 if (rmesa
->dma
.nr_released_bufs
) {
701 r300FlushCmdBufLocked(rmesa
, __FUNCTION__
);
704 if (RADEON_DEBUG
& DEBUG_DMA
)
705 fprintf(stderr
, "Waiting for buffers\n");
707 radeonWaitForIdleLocked(&rmesa
->radeon
);
708 ret
= drmDMA(fd
, &dma
);
711 UNLOCK_HARDWARE(&rmesa
->radeon
);
713 "Error: Could not get dma buffer... exiting\n");
718 UNLOCK_HARDWARE(&rmesa
->radeon
);
720 if (RADEON_DEBUG
& DEBUG_DMA
)
721 fprintf(stderr
, "Allocated buffer %d\n", index
);
723 dmabuf
= CALLOC_STRUCT(r300_dma_buffer
);
724 dmabuf
->buf
= &rmesa
->radeon
.radeonScreen
->buffers
->list
[index
];
725 dmabuf
->refcount
= 1;
727 rmesa
->dma
.current
.buf
= dmabuf
;
728 rmesa
->dma
.current
.address
= dmabuf
->buf
->address
;
729 rmesa
->dma
.current
.end
= dmabuf
->buf
->total
;
730 rmesa
->dma
.current
.start
= 0;
731 rmesa
->dma
.current
.ptr
= 0;
734 void r300ReleaseDmaRegion(r300ContextPtr rmesa
,
735 struct r300_dma_region
*region
, const char *caller
)
737 if (RADEON_DEBUG
& DEBUG_IOCTL
)
738 fprintf(stderr
, "%s from %s\n", __FUNCTION__
, caller
);
743 if (rmesa
->dma
.flush
)
744 rmesa
->dma
.flush(rmesa
);
746 if (--region
->buf
->refcount
== 0) {
747 drm_radeon_cmd_header_t
*cmd
;
749 if (RADEON_DEBUG
& (DEBUG_IOCTL
| DEBUG_DMA
))
750 fprintf(stderr
, "%s -- DISCARD BUF %d\n",
751 __FUNCTION__
, region
->buf
->buf
->idx
);
753 (drm_radeon_cmd_header_t
*) r300AllocCmdBuf(rmesa
,
757 cmd
->dma
.cmd_type
= R300_CMD_DMA_DISCARD
;
758 cmd
->dma
.buf_idx
= region
->buf
->buf
->idx
;
761 rmesa
->dma
.nr_released_bufs
++;
768 /* Allocates a region from rmesa->dma.current. If there isn't enough
769 * space in current, grab a new buffer (and discard what was left of current)
771 void r300AllocDmaRegion(r300ContextPtr rmesa
,
772 struct r300_dma_region
*region
,
773 int bytes
, int alignment
)
775 if (RADEON_DEBUG
& DEBUG_IOCTL
)
776 fprintf(stderr
, "%s %d\n", __FUNCTION__
, bytes
);
778 if (rmesa
->dma
.flush
)
779 rmesa
->dma
.flush(rmesa
);
782 r300ReleaseDmaRegion(rmesa
, region
, __FUNCTION__
);
785 rmesa
->dma
.current
.start
= rmesa
->dma
.current
.ptr
=
786 (rmesa
->dma
.current
.ptr
+ alignment
) & ~alignment
;
788 if (rmesa
->dma
.current
.ptr
+ bytes
> rmesa
->dma
.current
.end
)
789 r300RefillCurrentDmaRegion(rmesa
);
791 region
->start
= rmesa
->dma
.current
.start
;
792 region
->ptr
= rmesa
->dma
.current
.start
;
793 region
->end
= rmesa
->dma
.current
.start
+ bytes
;
794 region
->address
= rmesa
->dma
.current
.address
;
795 region
->buf
= rmesa
->dma
.current
.buf
;
796 region
->buf
->refcount
++;
798 rmesa
->dma
.current
.ptr
+= bytes
; /* bug - if alignment > 7 */
799 rmesa
->dma
.current
.start
=
800 rmesa
->dma
.current
.ptr
= (rmesa
->dma
.current
.ptr
+ 0x7) & ~0x7;
802 assert(rmesa
->dma
.current
.ptr
<= rmesa
->dma
.current
.end
);
807 GLboolean
r300IsGartMemory(r300ContextPtr rmesa
, const GLvoid
* pointer
,
812 (char *)rmesa
->radeon
.radeonScreen
->gartTextures
.map
;
813 int valid
= (size
>= 0 && offset
>= 0
815 rmesa
->radeon
.radeonScreen
->gartTextures
.size
);
817 if (RADEON_DEBUG
& DEBUG_IOCTL
)
818 fprintf(stderr
, "r300IsGartMemory( %p ) : %d\n", pointer
,
824 GLuint
r300GartOffsetFromVirtual(r300ContextPtr rmesa
, const GLvoid
* pointer
)
828 (char *)rmesa
->radeon
.radeonScreen
->gartTextures
.map
;
830 //fprintf(stderr, "offset=%08x\n", offset);
833 || offset
> rmesa
->radeon
.radeonScreen
->gartTextures
.size
)
836 return rmesa
->radeon
.radeonScreen
->gart_texture_offset
+ offset
;
839 void r300InitIoctlFuncs(struct dd_function_table
*functions
)
841 functions
->Clear
= r300Clear
;
842 functions
->Finish
= radeonFinish
;
843 functions
->Flush
= r300Flush
;