2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 **************************************************************************/
34 * Keith Whitwell <keith@tungstengraphics.com>
35 * Nicolai Haehnle <prefect_@gmx.net>
45 #include "swrast/swrast.h"
47 #include "r300_context.h"
48 #include "radeon_ioctl.h"
49 #include "r300_ioctl.h"
50 #include "r300_cmdbuf.h"
51 #include "r300_state.h"
52 #include "r300_program.h"
53 #include "radeon_reg.h"
58 #define CLEARBUFFER_COLOR 0x1
59 #define CLEARBUFFER_DEPTH 0x2
61 static void r300ClearBuffer(r300ContextPtr r300
, int flags
, int buffer
)
63 GLcontext
* ctx
= r300
->radeon
.glCtx
;
64 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
66 GLuint cboffset
, cbpitch
;
67 drm_r300_cmd_header_t
* cmd
;
69 if (RADEON_DEBUG
& DEBUG_IOCTL
)
70 fprintf(stderr
, "%s: %s buffer (%i,%i %ix%i)\n",
71 __FUNCTION__
, buffer
? "back" : "front",
72 dPriv
->x
, dPriv
->y
, dPriv
->w
, dPriv
->h
);
75 cboffset
= r300
->radeon
.radeonScreen
->backOffset
;
76 cbpitch
= r300
->radeon
.radeonScreen
->backPitch
;
78 cboffset
= r300
->radeon
.radeonScreen
->frontOffset
;
79 cbpitch
= r300
->radeon
.radeonScreen
->frontPitch
;
82 cboffset
+= r300
->radeon
.radeonScreen
->fbLocation
;
84 R300_STATECHANGE(r300
, vpt
);
85 r300
->hw
.vpt
.cmd
[R300_VPT_XSCALE
] = r300PackFloat32(1.0);
86 r300
->hw
.vpt
.cmd
[R300_VPT_XOFFSET
] = r300PackFloat32(dPriv
->x
);
87 r300
->hw
.vpt
.cmd
[R300_VPT_YSCALE
] = r300PackFloat32(1.0);
88 r300
->hw
.vpt
.cmd
[R300_VPT_YOFFSET
] = r300PackFloat32(dPriv
->y
);
89 r300
->hw
.vpt
.cmd
[R300_VPT_ZSCALE
] = r300PackFloat32(1.0);
90 r300
->hw
.vpt
.cmd
[R300_VPT_ZOFFSET
] = r300PackFloat32(0.0);
92 R300_STATECHANGE(r300
, cb
);
93 r300
->hw
.cb
.cmd
[R300_CB_OFFSET
] = cboffset
;
94 r300
->hw
.cb
.cmd
[R300_CB_PITCH
] = cbpitch
| R300_COLOR_UNKNOWN_22_23
;
96 R300_STATECHANGE(r300
, unk221C
);
97 r300
->hw
.unk221C
.cmd
[1] = R300_221C_CLEAR
;
99 R300_STATECHANGE(r300
, ps
);
100 r300
->hw
.ps
.cmd
[R300_PS_POINTSIZE
] =
101 ((dPriv
->w
* 6) << R300_POINTSIZE_X_SHIFT
) |
102 ((dPriv
->h
* 6) << R300_POINTSIZE_Y_SHIFT
);
104 R300_STATECHANGE(r300
, ri
);
105 for(i
= 1; i
<= 8; ++i
)
106 r300
->hw
.ri
.cmd
[i
] = R300_RS_INTERP_USED
;
108 R300_STATECHANGE(r300
, rr
);
109 ((drm_r300_cmd_header_t
*)r300
->hw
.rr
.cmd
)->unchecked_state
.count
= 1;
110 r300
->hw
.rr
.cmd
[1] = 0x00004000;
112 R300_STATECHANGE(r300
, cmk
);
113 if (flags
& CLEARBUFFER_COLOR
) {
114 r300
->hw
.cmk
.cmd
[R300_CMK_COLORMASK
] =
115 (ctx
->Color
.ColorMask
[BCOMP
] ? R300_COLORMASK0_B
: 0) |
116 (ctx
->Color
.ColorMask
[GCOMP
] ? R300_COLORMASK0_G
: 0) |
117 (ctx
->Color
.ColorMask
[RCOMP
] ? R300_COLORMASK0_R
: 0) |
118 (ctx
->Color
.ColorMask
[ACOMP
] ? R300_COLORMASK0_A
: 0);
120 r300
->hw
.cmk
.cmd
[R300_CMK_COLORMASK
] = 0;
123 R300_STATECHANGE(r300
, fp
);
124 r300
->hw
.fp
.cmd
[R300_FP_CNTL0
] = 0; /* 1 pass, no textures */
125 r300
->hw
.fp
.cmd
[R300_FP_CNTL1
] = 0; /* no temporaries */
126 r300
->hw
.fp
.cmd
[R300_FP_CNTL2
] = 0; /* no offset, one ALU instr */
127 r300
->hw
.fp
.cmd
[R300_FP_NODE0
] = 0;
128 r300
->hw
.fp
.cmd
[R300_FP_NODE1
] = 0;
129 r300
->hw
.fp
.cmd
[R300_FP_NODE2
] = 0;
130 r300
->hw
.fp
.cmd
[R300_FP_NODE3
] = R300_PFS_NODE_LAST_NODE
;
132 R300_STATECHANGE(r300
, fpi
[0]);
133 R300_STATECHANGE(r300
, fpi
[1]);
134 R300_STATECHANGE(r300
, fpi
[2]);
135 R300_STATECHANGE(r300
, fpi
[3]);
136 ((drm_r300_cmd_header_t
*)r300
->hw
.fpi
[0].cmd
)->unchecked_state
.count
= 1;
137 ((drm_r300_cmd_header_t
*)r300
->hw
.fpi
[1].cmd
)->unchecked_state
.count
= 1;
138 ((drm_r300_cmd_header_t
*)r300
->hw
.fpi
[2].cmd
)->unchecked_state
.count
= 1;
139 ((drm_r300_cmd_header_t
*)r300
->hw
.fpi
[3].cmd
)->unchecked_state
.count
= 1;
142 r300
->hw
.fpi
[0].cmd
[1] = FP_INSTRC(MAD
, FP_ARGC(SRC0C_XYZ
), FP_ARGC(ONE
), FP_ARGC(ZERO
));
143 r300
->hw
.fpi
[1].cmd
[1] = FP_SELC(0,NO
,XYZ
,FP_TMP(0),0,0);
144 r300
->hw
.fpi
[2].cmd
[1] = FP_INSTRA(MAD
, FP_ARGA(SRC0A
), FP_ARGA(ONE
), FP_ARGA(ZERO
));
145 r300
->hw
.fpi
[3].cmd
[1] = FP_SELA(0,NO
,W
,FP_TMP(0),0,0);
147 R300_STATECHANGE(r300
, pvs
);
148 r300
->hw
.pvs
.cmd
[R300_PVS_CNTL_1
] =
149 (0 << R300_PVS_CNTL_1_PROGRAM_START_SHIFT
) |
150 (0 << R300_PVS_CNTL_1_UNKNOWN_SHIFT
) |
151 (1 << R300_PVS_CNTL_1_PROGRAM_END_SHIFT
);
152 r300
->hw
.pvs
.cmd
[R300_PVS_CNTL_2
] = 0; /* no parameters */
153 r300
->hw
.pvs
.cmd
[R300_PVS_CNTL_3
] =
154 (1 << R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT
);
156 R300_STATECHANGE(r300
, vpi
);
157 ((drm_r300_cmd_header_t
*)r300
->hw
.vpi
.cmd
)->unchecked_state
.count
= 8;
160 r300
->hw
.vpi
.cmd
[1] = VP_OUT(ADD
,OUT
,0,XYZW
);
161 r300
->hw
.vpi
.cmd
[2] = VP_IN(IN
,0);
162 r300
->hw
.vpi
.cmd
[3] = VP_ZERO();
163 r300
->hw
.vpi
.cmd
[4] = 0;
166 r300
->hw
.vpi
.cmd
[5] = VP_OUT(ADD
,OUT
,1,XYZW
);
167 r300
->hw
.vpi
.cmd
[6] = VP_IN(IN
,1);
168 r300
->hw
.vpi
.cmd
[7] = VP_ZERO();
169 r300
->hw
.vpi
.cmd
[8] = 0;
171 R300_STATECHANGE(r300
, zc
);
172 if (flags
& CLEARBUFFER_DEPTH
) {
173 r300
->hw
.zc
.cmd
[R300_ZC_CNTL_0
] = 0x6; // test and write
174 r300
->hw
.zc
.cmd
[R300_ZC_CNTL_1
] = R300_Z_TEST_ALWAYS
;
176 R300_STATECHANGE(r300, zb);
177 r300->hw.zb.cmd[R300_ZB_OFFSET] =
179 r300->radeon.radeonScreen->frontOffset +
180 r300->radeon.radeonScreen->fbLocation;
181 r300->hw.zb.cmd[R300_ZB_PITCH] =
182 r300->radeon.radeonScreen->depthPitch;
185 r300
->hw
.zc
.cmd
[R300_ZC_CNTL_0
] = 0; // disable
186 r300
->hw
.zc
.cmd
[R300_ZC_CNTL_1
] = 0;
189 /* Make sure we have enough space */
190 r300EnsureCmdBufSpace(r300
, r300
->hw
.max_state_size
+ 9, __FUNCTION__
);
194 cmd
= (drm_r300_cmd_header_t
*)r300AllocCmdBuf(r300
, 9, __FUNCTION__
);
195 cmd
[0].packet3
.cmd_type
= R300_CMD_PACKET3
;
196 cmd
[0].packet3
.packet
= R300_CMD_PACKET3_CLEAR
;
197 cmd
[1].u
= r300PackFloat32(dPriv
->w
/ 2.0);
198 cmd
[2].u
= r300PackFloat32(dPriv
->h
/ 2.0);
199 cmd
[3].u
= r300PackFloat32(ctx
->Depth
.Clear
);
200 cmd
[4].u
= r300PackFloat32(1.0);
201 cmd
[5].u
= r300PackFloat32(ctx
->Color
.ClearColor
[0]);
202 cmd
[6].u
= r300PackFloat32(ctx
->Color
.ClearColor
[1]);
203 cmd
[7].u
= r300PackFloat32(ctx
->Color
.ClearColor
[2]);
204 cmd
[8].u
= r300PackFloat32(ctx
->Color
.ClearColor
[3]);
211 static void r300Clear(GLcontext
* ctx
, GLbitfield mask
, GLboolean all
,
212 GLint cx
, GLint cy
, GLint cw
, GLint ch
)
214 r300ContextPtr r300
= R300_CONTEXT(ctx
);
215 __DRIdrawablePrivate
*dPriv
= r300
->radeon
.dri
.drawable
;
220 if (RADEON_DEBUG
& DEBUG_IOCTL
)
221 fprintf(stderr
, "%s: all=%d cx=%d cy=%d cw=%d ch=%d\n",
222 __FUNCTION__
, all
, cx
, cy
, cw
, ch
);
225 LOCK_HARDWARE(&r300
->radeon
);
226 UNLOCK_HARDWARE(&r300
->radeon
);
227 if (dPriv
->numClipRects
== 0)
231 if (mask
& DD_FRONT_LEFT_BIT
) {
232 flags
|= DD_FRONT_LEFT_BIT
;
233 mask
&= ~DD_FRONT_LEFT_BIT
;
236 if (mask
& DD_BACK_LEFT_BIT
) {
237 flags
|= DD_BACK_LEFT_BIT
;
238 mask
&= ~DD_BACK_LEFT_BIT
;
241 if (mask
& DD_DEPTH_BIT
) {
242 bits
|= CLEARBUFFER_DEPTH
;
243 mask
&= ~DD_DEPTH_BIT
;
247 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
248 fprintf(stderr
, "%s: swrast clear, mask: %x\n",
250 _swrast_Clear(ctx
, mask
, all
, cx
, cy
, cw
, ch
);
253 swapped
= r300
->radeon
.doPageFlip
&& (r300
->radeon
.sarea
->pfCurrentPage
== 1);
255 if (flags
& DD_FRONT_LEFT_BIT
) {
256 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, swapped
);
260 if (flags
& DD_BACK_LEFT_BIT
) {
261 r300ClearBuffer(r300
, bits
| CLEARBUFFER_COLOR
, swapped
^ 1);
266 r300ClearBuffer(r300
, bits
, 0);
268 /* Recalculate the hardware state. This could be done more efficiently,
269 * but do keep it like this for now.
271 r300ResetHwState(r300
);
274 void r300Flush(GLcontext
* ctx
)
276 r300ContextPtr r300
= R300_CONTEXT(ctx
);
278 if (RADEON_DEBUG
& DEBUG_IOCTL
)
279 fprintf(stderr
, "%s\n", __FUNCTION__
);
281 if (r300
->cmdbuf
.count_used
> r300
->cmdbuf
.count_reemit
)
282 r300FlushCmdBuf(r300
, __FUNCTION__
);
285 void r300InitIoctlFuncs(struct dd_function_table
*functions
)
287 functions
->Clear
= r300Clear
;
288 functions
->Finish
= radeonFinish
;
289 functions
->Flush
= r300Flush
;