src/mesa/drivers/dri/r300/r300_ioctl.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.
   3 Copyright (C) 2004 Nicolai Haehnle.
   4 All Rights Reserved.
   5
   6 The Weather Channel (TM) funded Tungsten Graphics to develop the
   7 initial release of the Radeon 8500 driver under the XFree86 license.
   8 This notice must be preserved.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining
  11 a copy of this software and associated documentation files (the
  12 "Software"), to deal in the Software without restriction, including
  13 without limitation the rights to use, copy, modify, merge, publish,
  14 distribute, sublicense, and/or sell copies of the Software, and to
  15 permit persons to whom the Software is furnished to do so, subject to
  16 the following conditions:
  17
  18 The above copyright notice and this permission notice (including the
  19 next paragraph) shall be included in all copies or substantial
  20 portions of the Software.
  21
  22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  29
  30 **************************************************************************/
  31
  32 /**
  33  * \file
  34  *
  35  * \author Keith Whitwell <keith@tungstengraphics.com>
  36  *
  37  * \author Nicolai Haehnle <prefect_@gmx.net>
  38  */
  39
  40 #include <sched.h>
  41 #include <errno.h>
  42
  43 #include "main/glheader.h"
  44 #include "main/imports.h"
  45 #include "main/macros.h"
  46 #include "main/context.h"
  47 #include "swrast/swrast.h"
  48
  49 #include "radeon_common.h"
  50 #include "radeon_lock.h"
  51 #include "r300_context.h"
  52 #include "r300_ioctl.h"
  53 #include "r300_cmdbuf.h"
  54 #include "r300_state.h"
  55 #include "r300_vertprog.h"
  56 #include "radeon_reg.h"
  57 #include "r300_emit.h"
  58 #include "r300_fragprog.h"
  59 #include "r300_context.h"
  60
  61 #include "vblank.h"
  62
  63 #define R200_3D_DRAW_IMMD_2      0xC0003500
  64
  65 #define CLEARBUFFER_COLOR       0x1
  66 #define CLEARBUFFER_DEPTH       0x2
  67 #define CLEARBUFFER_STENCIL     0x4
  68
  69 static void r300EmitClearState(GLcontext * ctx);
  70
  71 static void r300UserClear(GLcontext *ctx, GLuint mask)
  72 {
  73         radeon_clear_tris(ctx, mask);
  74 }
  75
  76 static void r300ClearBuffer(r300ContextPtr r300, int flags,
  77                             struct radeon_renderbuffer *rrb,
  78                             struct radeon_renderbuffer *rrbd)
  79 {
  80         BATCH_LOCALS(&r300->radeon);
  81         GLcontext *ctx = r300->radeon.glCtx;
  82         __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
  83         GLuint cbpitch = 0;
  84         r300ContextPtr rmesa = r300;
  85
  86         if (RADEON_DEBUG & DEBUG_IOCTL)
  87                 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
  88                         __FUNCTION__, rrb, dPriv->x, dPriv->y,
  89                         dPriv->w, dPriv->h);
  90
  91         if (rrb) {
  92                 cbpitch = (rrb->pitch / rrb->cpp);
  93                 if (rrb->cpp == 4)
  94                         cbpitch |= R300_COLOR_FORMAT_ARGB8888;
  95                 else
  96                         cbpitch |= R300_COLOR_FORMAT_RGB565;
  97
  98                 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
  99                         cbpitch |= R300_COLOR_TILE_ENABLE;
 100         }
 101         }
 102
 103         /* TODO in bufmgr */
 104         cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 105         end_3d(&rmesa->radeon);
 106
 107         if (flags & CLEARBUFFER_COLOR) {
 108                 assert(rrb != 0);
 109                 BEGIN_BATCH_NO_AUTOSTATE(6);
 110                 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 111                 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 112                 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
 113                 END_BATCH();
 114         }
 115 #if 1
 116         if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
 117                 assert(rrbd != 0);
 118                 cbpitch = (rrbd->pitch / rrbd->cpp);
 119                 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
 120                         cbpitch |= R300_DEPTHMACROTILE_ENABLE;
 121         }
 122                 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 123             cbpitch |= R300_DEPTHMICROTILE_TILED;
 124         }
 125                 BEGIN_BATCH_NO_AUTOSTATE(6);
 126                 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 127                 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 128                 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
 129                 END_BATCH();
 130         }
 131 #endif
 132         BEGIN_BATCH_NO_AUTOSTATE(6);
 133         OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
 134         if (flags & CLEARBUFFER_COLOR) {
 135                 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
 136                           (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
 137                           (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
 138                           (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
 139         } else {
 140                 OUT_BATCH(0);
 141         }
 142
 143
 144         {
 145                 uint32_t t1, t2;
 146
 147                 t1 = 0x0;
 148                 t2 = 0x0;
 149
 150                 if (flags & CLEARBUFFER_DEPTH) {
 151                         t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
 152                         t2 |=
 153                             (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
 154                 }
 155
 156                 if (flags & CLEARBUFFER_STENCIL) {
 157                         t1 |= R300_STENCIL_ENABLE;
 158                         t2 |=
 159                             (R300_ZS_ALWAYS <<
 160                              R300_S_FRONT_FUNC_SHIFT) |
 161                             (R300_ZS_REPLACE <<
 162                              R300_S_FRONT_SFAIL_OP_SHIFT) |
 163                             (R300_ZS_REPLACE <<
 164                              R300_S_FRONT_ZPASS_OP_SHIFT) |
 165                             (R300_ZS_REPLACE <<
 166                              R300_S_FRONT_ZFAIL_OP_SHIFT);
 167                 }
 168
 169                 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
 170                 OUT_BATCH(t1);
 171                 OUT_BATCH(t2);
 172                 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
 173                    R300_STENCILWRITEMASK_SHIFT) |
 174                           (ctx->Stencil.Clear & R300_STENCILREF_MASK));
 175                 END_BATCH();
 176         }
 177
 178         if (!rmesa->radeon.radeonScreen->kernel_mm) {
 179                 BEGIN_BATCH_NO_AUTOSTATE(9);
 180                 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
 181                 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
 182                 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
 183                 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
 184                 OUT_BATCH_FLOAT32(1.0);
 185                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
 186                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
 187                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
 188                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
 189                 END_BATCH();
 190         } else {
 191                 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 192                 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 193                           (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 194                 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
 195                 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
 196                 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
 197                 OUT_BATCH_FLOAT32(1.0);
 198                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
 199                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
 200                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
 201                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
 202         }
 203
 204         r300EmitCacheFlush(rmesa);
 205         cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 206
 207         R300_STATECHANGE(r300, cb);
 208         R300_STATECHANGE(r300, cmk);
 209         R300_STATECHANGE(r300, zs);
 210 }
 211
 212 static void r300EmitClearState(GLcontext * ctx)
 213 {
 214         r300ContextPtr r300 = R300_CONTEXT(ctx);
 215         BATCH_LOCALS(&r300->radeon);
 216         __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 217         int i;
 218         int has_tcl;
 219         int is_r500 = 0;
 220         GLuint vap_cntl;
 221
 222         has_tcl = r300->options.hw_tcl_enabled;
 223
 224         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 225                 is_r500 = 1;
 226
 227         /* State atom dirty tracking is a little subtle here.
 228          *
 229          * On the one hand, we need to make sure base state is emitted
 230          * here if we start with an empty batch buffer, otherwise clear
 231          * works incorrectly with multiple processes. Therefore, the first
 232          * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
 233          *
 234          * On the other hand, implicit state emission clears the state atom
 235          * dirty bits, so we have to call R300_STATECHANGE later than the
 236          * first BEGIN_BATCH.
 237          *
 238          * The final trickiness is that, because we change state, we need
 239          * to ensure that any stored swtcl primitives are flushed properly
 240          * before we start changing state. See the R300_NEWPRIM in r300Clear
 241          * for this.
 242          */
 243         BEGIN_BATCH(31);
 244         OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
 245         if (!has_tcl)
 246                 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
 247                  ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
 248         else
 249                 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
 250                  ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
 251
 252         OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
 253         OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
 254            ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
 255                (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
 256                (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
 257                (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
 258                ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
 259               << R300_SWIZZLE0_SHIFT) |
 260              (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
 261                (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
 262                (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
 263                (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
 264                ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
 265               << R300_SWIZZLE1_SHIFT)));
 266
 267         /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
 268         OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
 269         OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
 270         OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
 271
 272         /* comes from fglrx startup of clear */
 273         OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
 274         OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
 275                   R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
 276                   R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
 277                   R300_VPORT_Z_OFFSET_ENA);
 278         OUT_BATCH(0x8);
 279
 280         OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
 281
 282         OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 283         OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
 284                   R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
 285         OUT_BATCH(0); /* no textures */
 286
 287         OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
 288
 289         OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
 290         OUT_BATCH_FLOAT32(1.0);
 291         OUT_BATCH_FLOAT32(dPriv->x);
 292         OUT_BATCH_FLOAT32(1.0);
 293         OUT_BATCH_FLOAT32(dPriv->y);
 294         OUT_BATCH_FLOAT32(1.0);
 295         OUT_BATCH_FLOAT32(0.0);
 296
 297         OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
 298
 299         OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
 300         OUT_BATCH(0x0);
 301         OUT_BATCH(0x0);
 302         END_BATCH();
 303
 304         R300_STATECHANGE(r300, vir[0]);
 305         R300_STATECHANGE(r300, fogs);
 306         R300_STATECHANGE(r300, vir[1]);
 307         R300_STATECHANGE(r300, vic);
 308         R300_STATECHANGE(r300, vte);
 309         R300_STATECHANGE(r300, vof);
 310         R300_STATECHANGE(r300, txe);
 311         R300_STATECHANGE(r300, vpt);
 312         R300_STATECHANGE(r300, at);
 313         R300_STATECHANGE(r300, bld);
 314         R300_STATECHANGE(r300, ps);
 315
 316         if (has_tcl) {
 317                 R300_STATECHANGE(r300, vap_clip_cntl);
 318
 319                 BEGIN_BATCH_NO_AUTOSTATE(2);
 320                 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
 321                 END_BATCH();
 322         }
 323
 324         BEGIN_BATCH_NO_AUTOSTATE(2);
 325         OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
 326                 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
 327                 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
 328         END_BATCH();
 329
 330         if (!is_r500) {
 331                 R300_STATECHANGE(r300, ri);
 332                 R300_STATECHANGE(r300, rc);
 333                 R300_STATECHANGE(r300, rr);
 334
 335                 BEGIN_BATCH(14);
 336                 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
 337                 for (i = 0; i < 8; ++i)
 338                         OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
 339
 340                 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
 341                 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 342                 OUT_BATCH(0x0);
 343
 344                 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
 345                 END_BATCH();
 346         } else {
 347                 R300_STATECHANGE(r300, ri);
 348                 R300_STATECHANGE(r300, rc);
 349                 R300_STATECHANGE(r300, rr);
 350
 351                 BEGIN_BATCH(14);
 352                 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
 353                 for (i = 0; i < 8; ++i) {
 354                         OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 355                                   (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 356                                   (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 357                                   (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 358                 }
 359
 360                 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
 361                 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 362                 OUT_BATCH(0x0);
 363
 364                 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
 365                 END_BATCH();
 366         }
 367
 368         if (!is_r500) {
 369                 R300_STATECHANGE(r300, fp);
 370                 R300_STATECHANGE(r300, fpi[0]);
 371                 R300_STATECHANGE(r300, fpi[1]);
 372                 R300_STATECHANGE(r300, fpi[2]);
 373                 R300_STATECHANGE(r300, fpi[3]);
 374
 375                 BEGIN_BATCH(17);
 376                 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
 377                 OUT_BATCH(0x0);
 378                 OUT_BATCH(0x0);
 379                 OUT_BATCH(0x0);
 380                 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
 381                 OUT_BATCH(0x0);
 382                 OUT_BATCH(0x0);
 383                 OUT_BATCH(0x0);
 384                 OUT_BATCH(R300_RGBA_OUT);
 385
 386                 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
 387                         FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
 388                 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
 389                         FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
 390                 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
 391                         FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
 392                 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
 393                         FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
 394                 END_BATCH();
 395         } else {
 396                 struct radeon_state_atom r500fp;
 397                 uint32_t _cmd[10];
 398
 399                 R300_STATECHANGE(r300, fp);
 400                 R300_STATECHANGE(r300, r500fp);
 401
 402                 BEGIN_BATCH(7);
 403                 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
 404                 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
 405                 OUT_BATCH(0x0);
 406                 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
 407                 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
 408                 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
 409                 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
 410                 END_BATCH();
 411
 412                 r500fp.check = check_r500fp;
 413                 r500fp.cmd = _cmd;
 414                 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
 415                 r500fp.cmd[1] = R500_INST_TYPE_OUT |
 416                         R500_INST_TEX_SEM_WAIT |
 417                         R500_INST_LAST |
 418                         R500_INST_RGB_OMASK_R |
 419                         R500_INST_RGB_OMASK_G |
 420                         R500_INST_RGB_OMASK_B |
 421                         R500_INST_ALPHA_OMASK |
 422                         R500_INST_RGB_CLAMP |
 423                         R500_INST_ALPHA_CLAMP;
 424                 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
 425                         R500_RGB_ADDR1(0) |
 426                         R500_RGB_ADDR1_CONST |
 427                         R500_RGB_ADDR2(0) |
 428                         R500_RGB_ADDR2_CONST;
 429                 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
 430                         R500_ALPHA_ADDR1(0) |
 431                         R500_ALPHA_ADDR1_CONST |
 432                         R500_ALPHA_ADDR2(0) |
 433                         R500_ALPHA_ADDR2_CONST;
 434                 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
 435                         R500_ALU_RGB_R_SWIZ_A_R |
 436                         R500_ALU_RGB_G_SWIZ_A_G |
 437                         R500_ALU_RGB_B_SWIZ_A_B |
 438                         R500_ALU_RGB_SEL_B_SRC0 |
 439                         R500_ALU_RGB_R_SWIZ_B_R |
 440                         R500_ALU_RGB_B_SWIZ_B_G |
 441                         R500_ALU_RGB_G_SWIZ_B_B;
 442                 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
 443                         R500_ALPHA_SWIZ_A_A |
 444                         R500_ALPHA_SWIZ_B_A;
 445                 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
 446                         R500_ALU_RGBA_R_SWIZ_0 |
 447                         R500_ALU_RGBA_G_SWIZ_0 |
 448                         R500_ALU_RGBA_B_SWIZ_0 |
 449                         R500_ALU_RGBA_A_SWIZ_0;
 450
 451                 r500fp.cmd[7] = 0;
 452                 emit_r500fp(ctx, &r500fp);
 453         }
 454
 455         BEGIN_BATCH(2);
 456         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 457         END_BATCH();
 458
 459         if (has_tcl) {
 460                 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
 461                         (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 462                         (12 << R300_VF_MAX_VTX_NUM_SHIFT));
 463                 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 464                         vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
 465         } else {
 466                 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
 467                         (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 468                         (5 << R300_VF_MAX_VTX_NUM_SHIFT));
 469         }
 470
 471         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
 472                 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
 473         else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
 474                  (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
 475                  (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
 476                 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
 477         else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
 478                  (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
 479                 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
 480         else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
 481                  (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
 482                 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
 483         else
 484                 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
 485
 486         R300_STATECHANGE(r300, vap_cntl);
 487
 488         BEGIN_BATCH(2);
 489         OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
 490         END_BATCH();
 491
 492         if (has_tcl) {
 493         struct radeon_state_atom vpu;
 494         uint32_t _cmd[10];
 495                 R300_STATECHANGE(r300, pvs);
 496                 R300_STATECHANGE(r300, vpi);
 497
 498                 BEGIN_BATCH(4);
 499                 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 500                 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
 501                           (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
 502                           (1 << R300_PVS_LAST_INST_SHIFT));
 503                 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
 504                           (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
 505                 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
 506                 END_BATCH();
 507
 508                 vpu.check = check_vpu;
 509                 vpu.cmd = _cmd;
 510                 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
 511
 512                 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
 513                                          0, 0xf, PVS_DST_REG_OUT);
 514                 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
 515                                       PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
 516                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 517                 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
 518                                       PVS_SRC_SELECT_FORCE_0,
 519                                       PVS_SRC_SELECT_FORCE_0,
 520                                       PVS_SRC_SELECT_FORCE_0,
 521                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 522                 vpu.cmd[4] = 0x0;
 523
 524                 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
 525                                          PVS_DST_REG_OUT);
 526                 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
 527                                       PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
 528                                       PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
 529
 530                                       VSF_FLAG_NONE);
 531                 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
 532                                       PVS_SRC_SELECT_FORCE_0,
 533                                       PVS_SRC_SELECT_FORCE_0,
 534                                       PVS_SRC_SELECT_FORCE_0,
 535                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 536                 vpu.cmd[8] = 0x0;
 537
 538                 r300->vap_flush_needed = GL_TRUE;
 539                 emit_vpu(ctx, &vpu);
 540         }
 541 }
 542
 543 static void r300KernelClear(GLcontext *ctx, GLuint flags)
 544 {
 545         r300ContextPtr r300 = R300_CONTEXT(ctx);
 546         __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 547         struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 548         struct radeon_renderbuffer *rrb;
 549         struct radeon_renderbuffer *rrbd;
 550         int bits = 0;
 551
 552         /* Make sure it fits there. */
 553         rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
 554         if (flags || bits)
 555                 r300EmitClearState(ctx);
 556         rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
 557         if (rrbd && (flags & BUFFER_BIT_DEPTH))
 558                 bits |= CLEARBUFFER_DEPTH;
 559
 560         if (rrbd && (flags & BUFFER_BIT_STENCIL))
 561                 bits |= CLEARBUFFER_STENCIL;
 562
 563         if (flags & BUFFER_BIT_COLOR0) {
 564                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
 565                 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
 566                 bits = 0;
 567         }
 568
 569         if (flags & BUFFER_BIT_FRONT_LEFT) {
 570                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
 571                 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 572                 bits = 0;
 573         }
 574
 575         if (flags & BUFFER_BIT_BACK_LEFT) {
 576                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
 577                 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 578                 bits = 0;
 579         }
 580
 581         if (bits)
 582                 r300ClearBuffer(r300, bits, NULL, rrbd);
 583
 584         COMMIT_BATCH();
 585 }
 586
 587 /**
 588  * Buffer clear
 589  */
 590 static void r300Clear(GLcontext * ctx, GLbitfield mask)
 591 {
 592         r300ContextPtr r300 = R300_CONTEXT(ctx);
 593         __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 594         const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
 595         GLbitfield swrast_mask = 0, tri_mask = 0;
 596         int i;
 597         struct gl_framebuffer *fb = ctx->DrawBuffer;
 598
 599         if (RADEON_DEBUG & DEBUG_IOCTL)
 600                 fprintf(stderr, "r300Clear\n");
 601
 602         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 603                 LOCK_HARDWARE(&r300->radeon);
 604                 UNLOCK_HARDWARE(&r300->radeon);
 605                 if (dPriv->numClipRects == 0)
 606                         return;
 607         }
 608
 609         /* Flush swtcl vertices if necessary, because we will change hardware
 610          * state during clear. See also the state-related comment in
 611          * r300EmitClearState.
 612          */
 613         R300_NEWPRIM(r300);
 614
 615         if (colorMask == ~0)
 616           tri_mask |= (mask & BUFFER_BITS_COLOR);
 617
 618
 619         /* HW stencil */
 620         if (mask & BUFFER_BIT_STENCIL) {
 621                 tri_mask |= BUFFER_BIT_STENCIL;
 622         }
 623
 624         /* HW depth */
 625         if (mask & BUFFER_BIT_DEPTH) {
 626                 tri_mask |= BUFFER_BIT_DEPTH;
 627         }
 628
 629         /* If we're doing a tri pass for depth/stencil, include a likely color
 630          * buffer with it.
 631          */
 632
 633         for (i = 0; i < BUFFER_COUNT; i++) {
 634           GLuint bufBit = 1 << i;
 635           if ((tri_mask) & bufBit) {
 636             if (!fb->Attachment[i].Renderbuffer->ClassID) {
 637               tri_mask &= ~bufBit;
 638               swrast_mask |= bufBit;
 639             }
 640           }
 641         }
 642
 643         /* SW fallback clearing */
 644         swrast_mask = mask & ~tri_mask;
 645
 646         if (tri_mask) {
 647                 if (r300->radeon.radeonScreen->kernel_mm)
 648                         r300UserClear(ctx, tri_mask);
 649                 else
 650                         r300KernelClear(ctx, tri_mask);
 651         }
 652         if (swrast_mask) {
 653                 if (RADEON_DEBUG & DEBUG_FALLBACKS)
 654                         fprintf(stderr, "%s: swrast clear, mask: %x\n",
 655                                 __FUNCTION__, swrast_mask);
 656                 _swrast_Clear(ctx, swrast_mask);
 657         }
 658 }
 659
 660
 661 void r300InitIoctlFuncs(struct dd_function_table *functions)
 662 {
 663         functions->Clear = r300Clear;
 664         functions->Finish = radeonFinish;
 665         functions->Flush = radeonFlush;
 666 }