projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge branch 'master' into asm-shader-rework-1
[mesa.git] / src / mesa / drivers / dri / r300 / r300_ioctl.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Keith Whitwell <keith@tungstengraphics.com>
36 *
37 * \author Nicolai Haehnle <prefect_@gmx.net>
38 */
39
40 #include <sched.h>
41 #include <errno.h>
42
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "main/simple_list.h"
48 #include "swrast/swrast.h"
49
50 #include "radeon_common.h"
51 #include "radeon_lock.h"
52 #include "r300_context.h"
53 #include "r300_ioctl.h"
54 #include "r300_cmdbuf.h"
55 #include "r300_state.h"
56 #include "r300_vertprog.h"
57 #include "radeon_reg.h"
58 #include "r300_emit.h"
59 #include "r300_context.h"
60 #include "r300_queryobj.h"
61
62 #include "vblank.h"
63
64 #define R200_3D_DRAW_IMMD_2 0xC0003500
65
66 #define CLEARBUFFER_COLOR 0x1
67 #define CLEARBUFFER_DEPTH 0x2
68 #define CLEARBUFFER_STENCIL 0x4
69
70 #if 1
71
72 /**
73 * Fragment program helper macros
74 */
75
76 /* Produce unshifted source selectors */
77 #define FP_TMP(idx) (idx)
78 #define FP_CONST(idx) ((idx) | (1 << 5))
79
80 /* Produce source/dest selector dword */
81 #define FP_SELC_MASK_NO 0
82 #define FP_SELC_MASK_X 1
83 #define FP_SELC_MASK_Y 2
84 #define FP_SELC_MASK_XY 3
85 #define FP_SELC_MASK_Z 4
86 #define FP_SELC_MASK_XZ 5
87 #define FP_SELC_MASK_YZ 6
88 #define FP_SELC_MASK_XYZ 7
89
90 #define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
91 (((destidx) << R300_ALU_DSTC_SHIFT) | \
92 (FP_SELC_MASK_##regmask << 23) | \
93 (FP_SELC_MASK_##outmask << 26) | \
94 ((src0) << R300_ALU_SRC0C_SHIFT) | \
95 ((src1) << R300_ALU_SRC1C_SHIFT) | \
96 ((src2) << R300_ALU_SRC2C_SHIFT))
97
98 #define FP_SELA_MASK_NO 0
99 #define FP_SELA_MASK_W 1
100
101 #define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
102 (((destidx) << R300_ALU_DSTA_SHIFT) | \
103 (FP_SELA_MASK_##regmask << 23) | \
104 (FP_SELA_MASK_##outmask << 24) | \
105 ((src0) << R300_ALU_SRC0A_SHIFT) | \
106 ((src1) << R300_ALU_SRC1A_SHIFT) | \
107 ((src2) << R300_ALU_SRC2A_SHIFT))
108
109 /* Produce unshifted argument selectors */
110 #define FP_ARGC(source) R300_ALU_ARGC_##source
111 #define FP_ARGA(source) R300_ALU_ARGA_##source
112 #define FP_ABS(arg) ((arg) | (1 << 6))
113 #define FP_NEG(arg) ((arg) ^ (1 << 5))
114
115 /* Produce instruction dword */
116 #define FP_INSTRC(opcode,arg0,arg1,arg2) \
117 (R300_ALU_OUTC_##opcode | \
118 ((arg0) << R300_ALU_ARG0C_SHIFT) | \
119 ((arg1) << R300_ALU_ARG1C_SHIFT) | \
120 ((arg2) << R300_ALU_ARG2C_SHIFT))
121
122 #define FP_INSTRA(opcode,arg0,arg1,arg2) \
123 (R300_ALU_OUTA_##opcode | \
124 ((arg0) << R300_ALU_ARG0A_SHIFT) | \
125 ((arg1) << R300_ALU_ARG1A_SHIFT) | \
126 ((arg2) << R300_ALU_ARG2A_SHIFT))
127
128 #endif
129
130 static void r300EmitClearState(GLcontext * ctx);
131
132 static void r300ClearBuffer(r300ContextPtr r300, int flags,
133 struct radeon_renderbuffer *rrb,
134 struct radeon_renderbuffer *rrbd)
135 {
136 BATCH_LOCALS(&r300->radeon);
137 GLcontext *ctx = r300->radeon.glCtx;
138 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
139 GLuint cbpitch = 0;
140 r300ContextPtr rmesa = r300;
141
142 if (RADEON_DEBUG & DEBUG_IOCTL)
143 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
144 __FUNCTION__, rrb, dPriv->x, dPriv->y,
145 dPriv->w, dPriv->h);
146
147 if (rrb) {
148 cbpitch = (rrb->pitch / rrb->cpp);
149 if (rrb->cpp == 4)
150 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
151 else
152 cbpitch |= R300_COLOR_FORMAT_RGB565;
153
154 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
155 cbpitch |= R300_COLOR_TILE_ENABLE;
156 }
157 }
158
159 /* TODO in bufmgr */
160 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
161 end_3d(&rmesa->radeon);
162
163 if (flags & CLEARBUFFER_COLOR) {
164 assert(rrb != 0);
165 BEGIN_BATCH_NO_AUTOSTATE(6);
166 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
167 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
168 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
169 END_BATCH();
170 }
171 #if 1
172 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
173 uint32_t zbpitch = (rrbd->pitch / rrbd->cpp);
174 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
175 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
176 }
177 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
178 zbpitch |= R300_DEPTHMICROTILE_TILED;
179 }
180 BEGIN_BATCH_NO_AUTOSTATE(6);
181 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
182 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
183 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
184 if (!r300->radeon.radeonScreen->kernel_mm)
185 OUT_BATCH(zbpitch);
186 else
187 OUT_BATCH_RELOC(zbpitch, rrbd->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
188 END_BATCH();
189 }
190 #endif
191 BEGIN_BATCH_NO_AUTOSTATE(6);
192 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
193 if (flags & CLEARBUFFER_COLOR) {
194 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
195 (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
196 (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
197 (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
198 } else {
199 OUT_BATCH(0);
200 }
201
202
203 {
204 uint32_t t1, t2;
205
206 t1 = 0x0;
207 t2 = 0x0;
208
209 if (flags & CLEARBUFFER_DEPTH) {
210 t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
211 t2 |=
212 (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
213 }
214
215 if (flags & CLEARBUFFER_STENCIL) {
216 t1 |= R300_STENCIL_ENABLE;
217 t2 |=
218 (R300_ZS_ALWAYS <<
219 R300_S_FRONT_FUNC_SHIFT) |
220 (R300_ZS_REPLACE <<
221 R300_S_FRONT_SFAIL_OP_SHIFT) |
222 (R300_ZS_REPLACE <<
223 R300_S_FRONT_ZPASS_OP_SHIFT) |
224 (R300_ZS_REPLACE <<
225 R300_S_FRONT_ZFAIL_OP_SHIFT);
226 }
227
228 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
229 OUT_BATCH(t1);
230 OUT_BATCH(t2);
231 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
232 R300_STENCILWRITEMASK_SHIFT) |
233 (ctx->Stencil.Clear & R300_STENCILREF_MASK));
234 END_BATCH();
235 }
236
237 if (!rmesa->radeon.radeonScreen->kernel_mm) {
238 BEGIN_BATCH_NO_AUTOSTATE(9);
239 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
240 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
241 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
242 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
243 OUT_BATCH_FLOAT32(1.0);
244 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
245 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
246 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
247 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
248 END_BATCH();
249 } else {
250 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
251 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
252 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
253 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
254 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
255 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
256 OUT_BATCH_FLOAT32(1.0);
257 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
258 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
259 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
260 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
261 }
262
263 r300EmitCacheFlush(rmesa);
264 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
265
266 R300_STATECHANGE(r300, cb);
267 R300_STATECHANGE(r300, cmk);
268 R300_STATECHANGE(r300, zs);
269 }
270
271 static void r300EmitClearState(GLcontext * ctx)
272 {
273 r300ContextPtr r300 = R300_CONTEXT(ctx);
274 BATCH_LOCALS(&r300->radeon);
275 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
276 int i;
277 int has_tcl;
278 int is_r500 = 0;
279 GLuint vap_cntl;
280
281 has_tcl = r300->options.hw_tcl_enabled;
282
283 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
284 is_r500 = 1;
285
286 /* State atom dirty tracking is a little subtle here.
287 *
288 * On the one hand, we need to make sure base state is emitted
289 * here if we start with an empty batch buffer, otherwise clear
290 * works incorrectly with multiple processes. Therefore, the first
291 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
292 *
293 * On the other hand, implicit state emission clears the state atom
294 * dirty bits, so we have to call R300_STATECHANGE later than the
295 * first BEGIN_BATCH.
296 *
297 * The final trickiness is that, because we change state, we need
298 * to ensure that any stored swtcl primitives are flushed properly
299 * before we start changing state. See the R300_NEWPRIM in r300Clear
300 * for this.
301 */
302 BEGIN_BATCH(31);
303 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
304 if (!has_tcl)
305 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
306 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
307 else
308 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
309 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
310
311 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
312 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
313 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
314 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
315 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
316 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
317 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
318 << R300_SWIZZLE0_SHIFT) |
319 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
320 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
321 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
322 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
323 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
324 << R300_SWIZZLE1_SHIFT)));
325
326 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
327 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
328 OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
329 OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
330
331 /* comes from fglrx startup of clear */
332 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
333 OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
334 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
335 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
336 R300_VPORT_Z_OFFSET_ENA);
337 OUT_BATCH(0x8);
338
339 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
340
341 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
342 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
343 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
344 OUT_BATCH(0); /* no textures */
345
346 OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
347
348 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
349 OUT_BATCH_FLOAT32(1.0);
350 OUT_BATCH_FLOAT32(dPriv->x);
351 OUT_BATCH_FLOAT32(1.0);
352 OUT_BATCH_FLOAT32(dPriv->y);
353 OUT_BATCH_FLOAT32(1.0);
354 OUT_BATCH_FLOAT32(0.0);
355
356 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
357
358 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
359 OUT_BATCH(0x0);
360 OUT_BATCH(0x0);
361 END_BATCH();
362
363 R300_STATECHANGE(r300, vir[0]);
364 R300_STATECHANGE(r300, fogs);
365 R300_STATECHANGE(r300, vir[1]);
366 R300_STATECHANGE(r300, vic);
367 R300_STATECHANGE(r300, vte);
368 R300_STATECHANGE(r300, vof);
369 R300_STATECHANGE(r300, txe);
370 R300_STATECHANGE(r300, vpt);
371 R300_STATECHANGE(r300, at);
372 R300_STATECHANGE(r300, bld);
373 R300_STATECHANGE(r300, ps);
374
375 if (has_tcl) {
376 R300_STATECHANGE(r300, vap_clip_cntl);
377
378 BEGIN_BATCH_NO_AUTOSTATE(2);
379 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
380 END_BATCH();
381 }
382
383 BEGIN_BATCH_NO_AUTOSTATE(2);
384 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
385 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
386 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
387 END_BATCH();
388
389 if (!is_r500) {
390 R300_STATECHANGE(r300, ri);
391 R300_STATECHANGE(r300, rc);
392 R300_STATECHANGE(r300, rr);
393
394 BEGIN_BATCH(14);
395 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
396 for (i = 0; i < 8; ++i)
397 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
398
399 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
400 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
401 OUT_BATCH(0x0);
402
403 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
404 END_BATCH();
405 } else {
406 R300_STATECHANGE(r300, ri);
407 R300_STATECHANGE(r300, rc);
408 R300_STATECHANGE(r300, rr);
409
410 BEGIN_BATCH(14);
411 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
412 for (i = 0; i < 8; ++i) {
413 OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
414 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
415 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
416 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
417 }
418
419 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
420 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
421 OUT_BATCH(0x0);
422
423 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
424 END_BATCH();
425 }
426
427 if (!is_r500) {
428 R300_STATECHANGE(r300, fp);
429 R300_STATECHANGE(r300, fpi[0]);
430 R300_STATECHANGE(r300, fpi[1]);
431 R300_STATECHANGE(r300, fpi[2]);
432 R300_STATECHANGE(r300, fpi[3]);
433
434 BEGIN_BATCH(17);
435 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
436 OUT_BATCH(0x0);
437 OUT_BATCH(0x0);
438 OUT_BATCH(0x0);
439 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
440 OUT_BATCH(0x0);
441 OUT_BATCH(0x0);
442 OUT_BATCH(0x0);
443 OUT_BATCH(R300_RGBA_OUT);
444
445 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
446 FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
447 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
448 FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
449 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
450 FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
451 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
452 FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
453 END_BATCH();
454 } else {
455 struct radeon_state_atom r500fp;
456 uint32_t _cmd[10];
457
458 R300_STATECHANGE(r300, fp);
459 R300_STATECHANGE(r300, r500fp);
460
461 BEGIN_BATCH(7);
462 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
463 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
464 OUT_BATCH(0x0);
465 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
466 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
467 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
468 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
469 END_BATCH();
470
471 r500fp.check = check_r500fp;
472 r500fp.cmd = _cmd;
473 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
474 r500fp.cmd[1] = R500_INST_TYPE_OUT |
475 R500_INST_TEX_SEM_WAIT |
476 R500_INST_LAST |
477 R500_INST_RGB_OMASK_R |
478 R500_INST_RGB_OMASK_G |
479 R500_INST_RGB_OMASK_B |
480 R500_INST_ALPHA_OMASK |
481 R500_INST_RGB_CLAMP |
482 R500_INST_ALPHA_CLAMP;
483 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
484 R500_RGB_ADDR1(0) |
485 R500_RGB_ADDR1_CONST |
486 R500_RGB_ADDR2(0) |
487 R500_RGB_ADDR2_CONST;
488 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
489 R500_ALPHA_ADDR1(0) |
490 R500_ALPHA_ADDR1_CONST |
491 R500_ALPHA_ADDR2(0) |
492 R500_ALPHA_ADDR2_CONST;
493 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
494 R500_ALU_RGB_R_SWIZ_A_R |
495 R500_ALU_RGB_G_SWIZ_A_G |
496 R500_ALU_RGB_B_SWIZ_A_B |
497 R500_ALU_RGB_SEL_B_SRC0 |
498 R500_ALU_RGB_R_SWIZ_B_R |
499 R500_ALU_RGB_B_SWIZ_B_G |
500 R500_ALU_RGB_G_SWIZ_B_B;
501 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
502 R500_ALPHA_SWIZ_A_A |
503 R500_ALPHA_SWIZ_B_A;
504 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
505 R500_ALU_RGBA_R_SWIZ_0 |
506 R500_ALU_RGBA_G_SWIZ_0 |
507 R500_ALU_RGBA_B_SWIZ_0 |
508 R500_ALU_RGBA_A_SWIZ_0;
509
510 r500fp.cmd[7] = 0;
511 emit_r500fp(ctx, &r500fp);
512 }
513
514 BEGIN_BATCH(2);
515 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
516 END_BATCH();
517
518 if (has_tcl) {
519 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
520 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
521 (12 << R300_VF_MAX_VTX_NUM_SHIFT));
522 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
523 vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
524 } else {
525 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
526 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
527 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
528 }
529
530 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
531 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
532 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
533 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
534 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
535 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
536 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
537 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
538 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
539 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
540 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
541 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
542 else
543 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
544
545 R300_STATECHANGE(r300, vap_cntl);
546
547 BEGIN_BATCH(2);
548 OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
549 END_BATCH();
550
551 if (has_tcl) {
552 struct radeon_state_atom vpu;
553 uint32_t _cmd[10];
554 R300_STATECHANGE(r300, pvs);
555 R300_STATECHANGE(r300, vpi);
556
557 BEGIN_BATCH(4);
558 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
559 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
560 (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
561 (1 << R300_PVS_LAST_INST_SHIFT));
562 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
563 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
564 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
565 END_BATCH();
566
567 vpu.check = check_vpu;
568 vpu.cmd = _cmd;
569 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
570
571 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
572 0, 0xf, PVS_DST_REG_OUT);
573 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
574 PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
575 PVS_SRC_REG_INPUT, NEGATE_NONE);
576 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
577 PVS_SRC_SELECT_FORCE_0,
578 PVS_SRC_SELECT_FORCE_0,
579 PVS_SRC_SELECT_FORCE_0,
580 PVS_SRC_REG_INPUT, NEGATE_NONE);
581 vpu.cmd[4] = 0x0;
582
583 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
584 PVS_DST_REG_OUT);
585 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
586 PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
587 PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
588 NEGATE_NONE);
589 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
590 PVS_SRC_SELECT_FORCE_0,
591 PVS_SRC_SELECT_FORCE_0,
592 PVS_SRC_SELECT_FORCE_0,
593 PVS_SRC_REG_INPUT, NEGATE_NONE);
594 vpu.cmd[8] = 0x0;
595
596 r300->vap_flush_needed = GL_TRUE;
597 emit_vpu(ctx, &vpu);
598 }
599 }
600
601 static int r300KernelClear(GLcontext *ctx, GLuint flags)
602 {
603 r300ContextPtr r300 = R300_CONTEXT(ctx);
604 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
605 struct radeon_framebuffer *rfb = dPriv->driverPrivate;
606 struct radeon_renderbuffer *rrb;
607 struct radeon_renderbuffer *rrbd;
608 int bits = 0, ret;
609
610 /* Make sure it fits there. */
611 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
612
613 if (flags & BUFFER_BIT_COLOR0) {
614 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
615 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
616 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
617 }
618
619 if (flags & BUFFER_BIT_FRONT_LEFT) {
620 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
621 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
622 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
623 }
624
625 if (flags & BUFFER_BIT_BACK_LEFT) {
626 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
627 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
628 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
629 }
630
631 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
632 if (rrbd) {
633 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
634 rrbd->bo, 0, RADEON_GEM_DOMAIN_VRAM);
635 }
636
637 ret = radeon_cs_space_check(r300->radeon.cmdbuf.cs);
638 if (ret)
639 return -1;
640
641 rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
642 if (flags || bits)
643 r300EmitClearState(ctx);
644
645 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
646 if (rrbd && (flags & BUFFER_BIT_DEPTH))
647 bits |= CLEARBUFFER_DEPTH;
648
649 if (rrbd && (flags & BUFFER_BIT_STENCIL))
650 bits |= CLEARBUFFER_STENCIL;
651
652 if (flags & BUFFER_BIT_COLOR0) {
653 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
654 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
655 bits = 0;
656 }
657
658 if (flags & BUFFER_BIT_FRONT_LEFT) {
659 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
660 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
661 bits = 0;
662 }
663
664 if (flags & BUFFER_BIT_BACK_LEFT) {
665 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
666 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
667 bits = 0;
668 }
669
670 if (bits)
671 r300ClearBuffer(r300, bits, NULL, rrbd);
672
673 COMMIT_BATCH();
674 return 0;
675 }
676
677 /**
678 * Buffer clear
679 */
680 static void r300Clear(GLcontext * ctx, GLbitfield mask)
681 {
682 r300ContextPtr r300 = R300_CONTEXT(ctx);
683 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
684 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
685 GLbitfield swrast_mask = 0, tri_mask = 0;
686 int i, ret;
687 struct gl_framebuffer *fb = ctx->DrawBuffer;
688
689 if (RADEON_DEBUG & DEBUG_IOCTL)
690 fprintf(stderr, "r300Clear\n");
691
692 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
693 LOCK_HARDWARE(&r300->radeon);
694 UNLOCK_HARDWARE(&r300->radeon);
695 if (dPriv->numClipRects == 0)
696 return;
697 }
698
699 /* Flush swtcl vertices if necessary, because we will change hardware
700 * state during clear. See also the state-related comment in
701 * r300EmitClearState.
702 */
703 R300_NEWPRIM(r300);
704
705 if (colorMask == ~0)
706 tri_mask |= (mask & BUFFER_BITS_COLOR);
707 else
708 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
709
710
711 /* HW stencil */
712 if (mask & BUFFER_BIT_STENCIL) {
713 tri_mask |= BUFFER_BIT_STENCIL;
714 }
715
716 /* HW depth */
717 if (mask & BUFFER_BIT_DEPTH) {
718 tri_mask |= BUFFER_BIT_DEPTH;
719 }
720
721 /* If we're doing a tri pass for depth/stencil, include a likely color
722 * buffer with it.
723 */
724
725 for (i = 0; i < BUFFER_COUNT; i++) {
726 GLuint bufBit = 1 << i;
727 if ((tri_mask) & bufBit) {
728 if (!fb->Attachment[i].Renderbuffer->ClassID) {
729 tri_mask &= ~bufBit;
730 swrast_mask |= bufBit;
731 }
732 }
733 }
734
735 /* SW fallback clearing */
736 swrast_mask = mask & ~tri_mask;
737
738 ret = 0;
739 if (tri_mask) {
740 if (r300->radeon.radeonScreen->kernel_mm)
741 radeonUserClear(ctx, tri_mask);
742 else {
743 /* if kernel clear fails due to size restraints fallback */
744 ret = r300KernelClear(ctx, tri_mask);
745 if (ret < 0)
746 swrast_mask |= tri_mask;
747 }
748 }
749
750 if (swrast_mask) {
751 if (RADEON_DEBUG & DEBUG_FALLBACKS)
752 fprintf(stderr, "%s: swrast clear, mask: %x\n",
753 __FUNCTION__, swrast_mask);
754 _swrast_Clear(ctx, swrast_mask);
755 }
756 }
757
758 static void r300Flush(GLcontext *ctx)
759 {
760 r300ContextPtr r300 = R300_CONTEXT(ctx);
761
762 radeonFlush(ctx);
763
764 make_empty_list(&r300->query.not_flushed_head);
765 }
766
767
768 void r300InitIoctlFuncs(struct dd_function_table *functions)
769 {
770 functions->Clear = r300Clear;
771 functions->Finish = radeonFinish;
772 functions->Flush = r300Flush;
773 }