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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / r300 / r300_ioctl.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Keith Whitwell <keith@tungstengraphics.com>
36 *
37 * \author Nicolai Haehnle <prefect_@gmx.net>
38 */
39
40 #include <sched.h>
41 #include <errno.h>
42
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
48
49 #include "radeon_common.h"
50 #include "radeon_lock.h"
51 #include "r300_context.h"
52 #include "r300_ioctl.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_state.h"
55 #include "r300_vertprog.h"
56 #include "radeon_reg.h"
57 #include "r300_emit.h"
58 #include "r300_fragprog.h"
59 #include "r300_context.h"
60
61 #include "vblank.h"
62
63 #define R200_3D_DRAW_IMMD_2 0xC0003500
64
65 #define CLEARBUFFER_COLOR 0x1
66 #define CLEARBUFFER_DEPTH 0x2
67 #define CLEARBUFFER_STENCIL 0x4
68
69 static void r300EmitClearState(GLcontext * ctx);
70
71 static void r300ClearBuffer(r300ContextPtr r300, int flags,
72 struct radeon_renderbuffer *rrb,
73 struct radeon_renderbuffer *rrbd)
74 {
75 BATCH_LOCALS(&r300->radeon);
76 GLcontext *ctx = r300->radeon.glCtx;
77 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
78 GLuint cbpitch = 0;
79 r300ContextPtr rmesa = r300;
80
81 if (RADEON_DEBUG & DEBUG_IOCTL)
82 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
83 __FUNCTION__, rrb, dPriv->x, dPriv->y,
84 dPriv->w, dPriv->h);
85
86 if (rrb) {
87 cbpitch = (rrb->pitch / rrb->cpp);
88 if (rrb->cpp == 4)
89 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
90 else
91 cbpitch |= R300_COLOR_FORMAT_RGB565;
92
93 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
94 cbpitch |= R300_COLOR_TILE_ENABLE;
95 }
96 }
97
98 /* TODO in bufmgr */
99 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
100 end_3d(&rmesa->radeon);
101
102 if (flags & CLEARBUFFER_COLOR) {
103 assert(rrb != 0);
104 BEGIN_BATCH_NO_AUTOSTATE(6);
105 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
106 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
107 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
108 END_BATCH();
109 }
110 #if 1
111 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
112 assert(rrbd != 0);
113 cbpitch = (rrbd->pitch / rrbd->cpp);
114 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
115 cbpitch |= R300_DEPTHMACROTILE_ENABLE;
116 }
117 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
118 cbpitch |= R300_DEPTHMICROTILE_TILED;
119 }
120 BEGIN_BATCH_NO_AUTOSTATE(6);
121 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
122 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
123 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
124 END_BATCH();
125 }
126 #endif
127 BEGIN_BATCH_NO_AUTOSTATE(6);
128 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
129 if (flags & CLEARBUFFER_COLOR) {
130 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
131 (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
132 (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
133 (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
134 } else {
135 OUT_BATCH(0);
136 }
137
138
139 {
140 uint32_t t1, t2;
141
142 t1 = 0x0;
143 t2 = 0x0;
144
145 if (flags & CLEARBUFFER_DEPTH) {
146 t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
147 t2 |=
148 (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
149 }
150
151 if (flags & CLEARBUFFER_STENCIL) {
152 t1 |= R300_STENCIL_ENABLE;
153 t2 |=
154 (R300_ZS_ALWAYS <<
155 R300_S_FRONT_FUNC_SHIFT) |
156 (R300_ZS_REPLACE <<
157 R300_S_FRONT_SFAIL_OP_SHIFT) |
158 (R300_ZS_REPLACE <<
159 R300_S_FRONT_ZPASS_OP_SHIFT) |
160 (R300_ZS_REPLACE <<
161 R300_S_FRONT_ZFAIL_OP_SHIFT);
162 }
163
164 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
165 OUT_BATCH(t1);
166 OUT_BATCH(t2);
167 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
168 R300_STENCILWRITEMASK_SHIFT) |
169 (ctx->Stencil.Clear & R300_STENCILREF_MASK));
170 END_BATCH();
171 }
172
173 if (!rmesa->radeon.radeonScreen->kernel_mm) {
174 BEGIN_BATCH_NO_AUTOSTATE(9);
175 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
176 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
177 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
178 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
179 OUT_BATCH_FLOAT32(1.0);
180 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
181 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
182 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
183 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
184 END_BATCH();
185 } else {
186 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
187 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
188 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
189 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
190 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
191 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
192 OUT_BATCH_FLOAT32(1.0);
193 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
194 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
195 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
196 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
197 }
198
199 r300EmitCacheFlush(rmesa);
200 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
201
202 R300_STATECHANGE(r300, cb);
203 R300_STATECHANGE(r300, cmk);
204 R300_STATECHANGE(r300, zs);
205 }
206
207 static void r300EmitClearState(GLcontext * ctx)
208 {
209 r300ContextPtr r300 = R300_CONTEXT(ctx);
210 BATCH_LOCALS(&r300->radeon);
211 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
212 int i;
213 int has_tcl;
214 int is_r500 = 0;
215 GLuint vap_cntl;
216
217 has_tcl = r300->options.hw_tcl_enabled;
218
219 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
220 is_r500 = 1;
221
222 /* State atom dirty tracking is a little subtle here.
223 *
224 * On the one hand, we need to make sure base state is emitted
225 * here if we start with an empty batch buffer, otherwise clear
226 * works incorrectly with multiple processes. Therefore, the first
227 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
228 *
229 * On the other hand, implicit state emission clears the state atom
230 * dirty bits, so we have to call R300_STATECHANGE later than the
231 * first BEGIN_BATCH.
232 *
233 * The final trickiness is that, because we change state, we need
234 * to ensure that any stored swtcl primitives are flushed properly
235 * before we start changing state. See the R300_NEWPRIM in r300Clear
236 * for this.
237 */
238 BEGIN_BATCH(31);
239 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
240 if (!has_tcl)
241 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
242 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
243 else
244 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
245 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
246
247 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
248 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
249 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
250 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
251 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
252 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
253 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
254 << R300_SWIZZLE0_SHIFT) |
255 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
256 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
257 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
258 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
259 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
260 << R300_SWIZZLE1_SHIFT)));
261
262 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
263 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
264 OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
265 OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
266
267 /* comes from fglrx startup of clear */
268 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
269 OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
270 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
271 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
272 R300_VPORT_Z_OFFSET_ENA);
273 OUT_BATCH(0x8);
274
275 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
276
277 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
278 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
279 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
280 OUT_BATCH(0); /* no textures */
281
282 OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
283
284 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
285 OUT_BATCH_FLOAT32(1.0);
286 OUT_BATCH_FLOAT32(dPriv->x);
287 OUT_BATCH_FLOAT32(1.0);
288 OUT_BATCH_FLOAT32(dPriv->y);
289 OUT_BATCH_FLOAT32(1.0);
290 OUT_BATCH_FLOAT32(0.0);
291
292 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
293
294 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
295 OUT_BATCH(0x0);
296 OUT_BATCH(0x0);
297 END_BATCH();
298
299 R300_STATECHANGE(r300, vir[0]);
300 R300_STATECHANGE(r300, fogs);
301 R300_STATECHANGE(r300, vir[1]);
302 R300_STATECHANGE(r300, vic);
303 R300_STATECHANGE(r300, vte);
304 R300_STATECHANGE(r300, vof);
305 R300_STATECHANGE(r300, txe);
306 R300_STATECHANGE(r300, vpt);
307 R300_STATECHANGE(r300, at);
308 R300_STATECHANGE(r300, bld);
309 R300_STATECHANGE(r300, ps);
310
311 if (has_tcl) {
312 R300_STATECHANGE(r300, vap_clip_cntl);
313
314 BEGIN_BATCH_NO_AUTOSTATE(2);
315 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
316 END_BATCH();
317 }
318
319 BEGIN_BATCH_NO_AUTOSTATE(2);
320 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
321 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
322 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
323 END_BATCH();
324
325 if (!is_r500) {
326 R300_STATECHANGE(r300, ri);
327 R300_STATECHANGE(r300, rc);
328 R300_STATECHANGE(r300, rr);
329
330 BEGIN_BATCH(14);
331 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
332 for (i = 0; i < 8; ++i)
333 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
334
335 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
336 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
337 OUT_BATCH(0x0);
338
339 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
340 END_BATCH();
341 } else {
342 R300_STATECHANGE(r300, ri);
343 R300_STATECHANGE(r300, rc);
344 R300_STATECHANGE(r300, rr);
345
346 BEGIN_BATCH(14);
347 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
348 for (i = 0; i < 8; ++i) {
349 OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
350 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
351 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
352 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
353 }
354
355 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
356 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
357 OUT_BATCH(0x0);
358
359 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
360 END_BATCH();
361 }
362
363 if (!is_r500) {
364 R300_STATECHANGE(r300, fp);
365 R300_STATECHANGE(r300, fpi[0]);
366 R300_STATECHANGE(r300, fpi[1]);
367 R300_STATECHANGE(r300, fpi[2]);
368 R300_STATECHANGE(r300, fpi[3]);
369
370 BEGIN_BATCH(17);
371 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
372 OUT_BATCH(0x0);
373 OUT_BATCH(0x0);
374 OUT_BATCH(0x0);
375 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
376 OUT_BATCH(0x0);
377 OUT_BATCH(0x0);
378 OUT_BATCH(0x0);
379 OUT_BATCH(R300_RGBA_OUT);
380
381 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
382 FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
383 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
384 FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
385 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
386 FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
387 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
388 FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
389 END_BATCH();
390 } else {
391 struct radeon_state_atom r500fp;
392 uint32_t _cmd[10];
393
394 R300_STATECHANGE(r300, fp);
395 R300_STATECHANGE(r300, r500fp);
396
397 BEGIN_BATCH(7);
398 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
399 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
400 OUT_BATCH(0x0);
401 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
402 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
403 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
404 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
405 END_BATCH();
406
407 r500fp.check = check_r500fp;
408 r500fp.cmd = _cmd;
409 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
410 r500fp.cmd[1] = R500_INST_TYPE_OUT |
411 R500_INST_TEX_SEM_WAIT |
412 R500_INST_LAST |
413 R500_INST_RGB_OMASK_R |
414 R500_INST_RGB_OMASK_G |
415 R500_INST_RGB_OMASK_B |
416 R500_INST_ALPHA_OMASK |
417 R500_INST_RGB_CLAMP |
418 R500_INST_ALPHA_CLAMP;
419 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
420 R500_RGB_ADDR1(0) |
421 R500_RGB_ADDR1_CONST |
422 R500_RGB_ADDR2(0) |
423 R500_RGB_ADDR2_CONST;
424 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
425 R500_ALPHA_ADDR1(0) |
426 R500_ALPHA_ADDR1_CONST |
427 R500_ALPHA_ADDR2(0) |
428 R500_ALPHA_ADDR2_CONST;
429 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
430 R500_ALU_RGB_R_SWIZ_A_R |
431 R500_ALU_RGB_G_SWIZ_A_G |
432 R500_ALU_RGB_B_SWIZ_A_B |
433 R500_ALU_RGB_SEL_B_SRC0 |
434 R500_ALU_RGB_R_SWIZ_B_R |
435 R500_ALU_RGB_B_SWIZ_B_G |
436 R500_ALU_RGB_G_SWIZ_B_B;
437 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
438 R500_ALPHA_SWIZ_A_A |
439 R500_ALPHA_SWIZ_B_A;
440 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
441 R500_ALU_RGBA_R_SWIZ_0 |
442 R500_ALU_RGBA_G_SWIZ_0 |
443 R500_ALU_RGBA_B_SWIZ_0 |
444 R500_ALU_RGBA_A_SWIZ_0;
445
446 r500fp.cmd[7] = 0;
447 emit_r500fp(ctx, &r500fp);
448 }
449
450 BEGIN_BATCH(2);
451 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
452 END_BATCH();
453
454 if (has_tcl) {
455 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
456 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
457 (12 << R300_VF_MAX_VTX_NUM_SHIFT));
458 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
459 vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
460 } else {
461 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
462 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
463 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
464 }
465
466 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
467 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
468 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
469 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
470 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
471 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
472 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
473 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
474 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
475 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
476 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
477 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
478 else
479 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
480
481 R300_STATECHANGE(r300, vap_cntl);
482
483 BEGIN_BATCH(2);
484 OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
485 END_BATCH();
486
487 if (has_tcl) {
488 struct radeon_state_atom vpu;
489 uint32_t _cmd[10];
490 R300_STATECHANGE(r300, pvs);
491 R300_STATECHANGE(r300, vpi);
492
493 BEGIN_BATCH(4);
494 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
495 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
496 (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
497 (1 << R300_PVS_LAST_INST_SHIFT));
498 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
499 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
500 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
501 END_BATCH();
502
503 vpu.check = check_vpu;
504 vpu.cmd = _cmd;
505 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
506
507 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
508 0, 0xf, PVS_DST_REG_OUT);
509 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
510 PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
511 PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
512 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
513 PVS_SRC_SELECT_FORCE_0,
514 PVS_SRC_SELECT_FORCE_0,
515 PVS_SRC_SELECT_FORCE_0,
516 PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
517 vpu.cmd[4] = 0x0;
518
519 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
520 PVS_DST_REG_OUT);
521 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
522 PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
523 PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
524
525 VSF_FLAG_NONE);
526 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
527 PVS_SRC_SELECT_FORCE_0,
528 PVS_SRC_SELECT_FORCE_0,
529 PVS_SRC_SELECT_FORCE_0,
530 PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
531 vpu.cmd[8] = 0x0;
532
533 r300->vap_flush_needed = GL_TRUE;
534 emit_vpu(ctx, &vpu);
535 }
536 }
537
538 static int r300KernelClear(GLcontext *ctx, GLuint flags)
539 {
540 r300ContextPtr r300 = R300_CONTEXT(ctx);
541 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
542 struct radeon_framebuffer *rfb = dPriv->driverPrivate;
543 struct radeon_renderbuffer *rrb;
544 struct radeon_renderbuffer *rrbd;
545 int bits = 0, ret;
546
547 /* Make sure it fits there. */
548 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
549
550 if (flags & BUFFER_BIT_COLOR0) {
551 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
552 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
553 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
554 }
555
556 if (flags & BUFFER_BIT_FRONT_LEFT) {
557 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
558 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
559 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
560 }
561
562 if (flags & BUFFER_BIT_BACK_LEFT) {
563 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
564 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
565 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
566 }
567
568 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
569 if (rrbd) {
570 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
571 rrbd->bo, 0, RADEON_GEM_DOMAIN_VRAM);
572 }
573
574 ret = radeon_cs_space_check(r300->radeon.cmdbuf.cs);
575 if (ret)
576 return -1;
577
578 rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
579 if (flags || bits)
580 r300EmitClearState(ctx);
581
582 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
583 if (rrbd && (flags & BUFFER_BIT_DEPTH))
584 bits |= CLEARBUFFER_DEPTH;
585
586 if (rrbd && (flags & BUFFER_BIT_STENCIL))
587 bits |= CLEARBUFFER_STENCIL;
588
589 if (flags & BUFFER_BIT_COLOR0) {
590 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
591 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
592 bits = 0;
593 }
594
595 if (flags & BUFFER_BIT_FRONT_LEFT) {
596 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
597 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
598 bits = 0;
599 }
600
601 if (flags & BUFFER_BIT_BACK_LEFT) {
602 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
603 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
604 bits = 0;
605 }
606
607 if (bits)
608 r300ClearBuffer(r300, bits, NULL, rrbd);
609
610 COMMIT_BATCH();
611 return 0;
612 }
613
614 /**
615 * Buffer clear
616 */
617 static void r300Clear(GLcontext * ctx, GLbitfield mask)
618 {
619 r300ContextPtr r300 = R300_CONTEXT(ctx);
620 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
621 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
622 GLbitfield swrast_mask = 0, tri_mask = 0;
623 int i, ret;
624 struct gl_framebuffer *fb = ctx->DrawBuffer;
625
626 if (RADEON_DEBUG & DEBUG_IOCTL)
627 fprintf(stderr, "r300Clear\n");
628
629 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
630 LOCK_HARDWARE(&r300->radeon);
631 UNLOCK_HARDWARE(&r300->radeon);
632 if (dPriv->numClipRects == 0)
633 return;
634 }
635
636 /* Flush swtcl vertices if necessary, because we will change hardware
637 * state during clear. See also the state-related comment in
638 * r300EmitClearState.
639 */
640 R300_NEWPRIM(r300);
641
642 if (colorMask == ~0)
643 tri_mask |= (mask & BUFFER_BITS_COLOR);
644 else
645 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
646
647
648 /* HW stencil */
649 if (mask & BUFFER_BIT_STENCIL) {
650 tri_mask |= BUFFER_BIT_STENCIL;
651 }
652
653 /* HW depth */
654 if (mask & BUFFER_BIT_DEPTH) {
655 tri_mask |= BUFFER_BIT_DEPTH;
656 }
657
658 /* If we're doing a tri pass for depth/stencil, include a likely color
659 * buffer with it.
660 */
661
662 for (i = 0; i < BUFFER_COUNT; i++) {
663 GLuint bufBit = 1 << i;
664 if ((tri_mask) & bufBit) {
665 if (!fb->Attachment[i].Renderbuffer->ClassID) {
666 tri_mask &= ~bufBit;
667 swrast_mask |= bufBit;
668 }
669 }
670 }
671
672 /* SW fallback clearing */
673 swrast_mask = mask & ~tri_mask;
674
675 ret = 0;
676 if (tri_mask) {
677 if (r300->radeon.radeonScreen->kernel_mm)
678 radeonUserClear(ctx, tri_mask);
679 else {
680 /* if kernel clear fails due to size restraints fallback */
681 ret = r300KernelClear(ctx, tri_mask);
682 if (ret < 0)
683 swrast_mask |= tri_mask;
684 }
685 }
686
687 if (swrast_mask) {
688 if (RADEON_DEBUG & DEBUG_FALLBACKS)
689 fprintf(stderr, "%s: swrast clear, mask: %x\n",
690 __FUNCTION__, swrast_mask);
691 _swrast_Clear(ctx, swrast_mask);
692 }
693 }
694
695
696 void r300InitIoctlFuncs(struct dd_function_table *functions)
697 {
698 functions->Clear = r300Clear;
699 functions->Finish = radeonFinish;
700 functions->Flush = radeonFlush;
701 }