5 This file contains registers and constants for the R300. They have been
6 found mostly by examining command buffers captured using glxtest, as well
7 as by extrapolating some known registers and constants from the R200.
9 I am fairly certain that they are correct unless stated otherwise in comments.
12 #define R300_SE_VPORT_XSCALE 0x1D98
13 #define R300_SE_VPORT_XOFFSET 0x1D9C
14 #define R300_SE_VPORT_YSCALE 0x1DA0
15 #define R300_SE_VPORT_YOFFSET 0x1DA4
16 #define R300_SE_VPORT_ZSCALE 0x1DA8
17 #define R300_SE_VPORT_ZOFFSET 0x1DAC
20 /* This register is written directly and also starts data section in many 3d CP_PACKET3's */
21 #define R300_VAP_VF_CNTL 0x2084
23 # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
24 # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
25 # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
26 # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
27 # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
28 # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
29 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
30 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
31 # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
32 # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
33 # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
34 # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
36 # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
37 /* State based - direct writes to registers trigger vertex generation */
38 # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
39 # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
40 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
41 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
43 /* I don't think I saw these three used.. */
44 # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
45 # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
46 # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
48 /* index size - when not set the indices are assumed to be 16 bit */
49 # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
50 /* number of vertices */
51 # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
53 /* BEGIN: Wild guesses */
54 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
55 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
56 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
57 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
58 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
59 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
60 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
62 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
63 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
64 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
65 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
66 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
67 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
68 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
69 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
70 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
73 #define R300_SE_VTE_CNTL 0x20b0
74 # define R300_VPORT_X_SCALE_ENA 0x00000001
75 # define R300_VPORT_X_OFFSET_ENA 0x00000002
76 # define R300_VPORT_Y_SCALE_ENA 0x00000004
77 # define R300_VPORT_Y_OFFSET_ENA 0x00000008
78 # define R300_VPORT_Z_SCALE_ENA 0x00000010
79 # define R300_VPORT_Z_OFFSET_ENA 0x00000020
80 # define R300_VTX_XY_FMT 0x00000100
81 # define R300_VTX_Z_FMT 0x00000200
82 # define R300_VTX_W0_FMT 0x00000400
83 # define R300_VTX_W0_NORMALIZE 0x00000800
84 # define R300_VTX_ST_DENORMALIZED 0x00001000
86 /* BEGIN: Vertex data assembly - lots of uncertainties */
88 /* Where do we get our vertex data?
90 // Vertex data either comes either from immediate mode registers or from
92 // There appears to be no mixed mode (though we can force the pitch of
93 // vertex arrays to 0, effectively reusing the same element over and over
96 // Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
97 // if these registers influence vertex array processing.
99 // Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
101 // In both cases, vertex attributes are then passed through INPUT_ROUTE.
103 // Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
104 // into the vertex processor's input registers.
105 // The first word routes the first input, the second word the second, etc.
106 // The corresponding input is routed into the register with the given index.
107 // The list is ended by a word with INPUT_ROUTE_END set.
109 // Always set COMPONENTS_4 in immediate mode. */
111 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
112 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
113 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
114 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
115 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
116 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
117 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
118 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
119 # define R300_VAP_INPUT_ROUTE_END (1 << 13)
120 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
121 # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
122 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
123 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
124 #define R300_VAP_INPUT_ROUTE_0_1 0x2154
125 #define R300_VAP_INPUT_ROUTE_0_2 0x2158
126 #define R300_VAP_INPUT_ROUTE_0_3 0x215C
130 // - always set up to produce at least two attributes:
131 // if vertex program uses only position, fglrx will set normal, too
132 // - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */
133 #define R300_VAP_INPUT_CNTL_0 0x2180
134 # define R300_INPUT_CNTL_0_COLOR 0x00000001
135 #define R300_VAP_INPUT_CNTL_1 0x2184
136 # define R300_INPUT_CNTL_POS 0x00000001
137 # define R300_INPUT_CNTL_NORMAL 0x00000002
138 # define R300_INPUT_CNTL_COLOR 0x00000004
139 # define R300_INPUT_CNTL_TC0 0x00000400
140 # define R300_INPUT_CNTL_TC1 0x00000800
141 # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
142 # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
143 # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
144 # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
145 # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
146 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
149 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
150 // are set to a swizzling bit pattern, other words are 0.
152 // In immediate mode, the pattern is always set to xyzw. In vertex array
153 // mode, the swizzling pattern is e.g. used to set zw components in texture
154 // coordinates with only tweo components. */
155 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
156 # define R300_INPUT_ROUTE_SELECT_X 0
157 # define R300_INPUT_ROUTE_SELECT_Y 1
158 # define R300_INPUT_ROUTE_SELECT_Z 2
159 # define R300_INPUT_ROUTE_SELECT_W 3
160 # define R300_INPUT_ROUTE_SELECT_ZERO 4
161 # define R300_INPUT_ROUTE_SELECT_ONE 5
162 # define R300_INPUT_ROUTE_SELECT_MASK 7
163 # define R300_INPUT_ROUTE_X_SHIFT 0
164 # define R300_INPUT_ROUTE_Y_SHIFT 3
165 # define R300_INPUT_ROUTE_Z_SHIFT 6
166 # define R300_INPUT_ROUTE_W_SHIFT 9
167 # define R300_INPUT_ROUTE_ENABLE (15 << 12)
168 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
169 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
170 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
175 /* BEGIN: Upload vertex program and data
176 // The programmable vertex shader unit has a memory bank of unknown size
177 // that can be written to in 16 byte units by writing the address into
178 // UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
180 // Pointers into the memory bank are always in multiples of 16 bytes.
182 // The memory bank is divided into areas with fixed meaning.
184 // Starting at address UPLOAD_PROGRAM: Vertex program instructions.
185 // Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
186 // whereas the difference between known addresses suggests size 512.
188 // Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
189 // Native reported limits and the VPI layout suggest size 256, whereas
190 // difference between known addresses suggests size 512.
192 // At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
193 // floating point pointsize. The exact purpose of this state is uncertain,
194 // as there is also the R300_RE_POINTSIZE register.
196 // Multiple vertex programs and parameter sets can be loaded at once,
197 // which could explain the size discrepancy. */
198 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
199 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
200 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
201 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406
203 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
207 /* I do not know the purpose of this register. However, I do know that
208 // it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
209 // for normal rendering. */
210 #define R300_VAP_UNKNOWN_221C 0x221C
211 # define R300_221C_NORMAL 0x00000000
212 # define R300_221C_CLEAR 0x0001C000
215 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
216 // rendering commands and overwriting vertex program parameters.
217 // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
218 // avoids bugs caused by still running shaders reading bad data from memory. */
219 #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
221 /* Absolutely no clue what this register is about. */
222 #define R300_VAP_UNKNOWN_2288 0x2288
223 # define R300_2288_R300 0x00750000 /* -- nh */
224 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
227 /* Addresses are relative to the vertex program instruction area of the
228 // memory bank. PROGRAM_END points to the last instruction of the active
231 // The meaning of the two UNKNOWN fields is obviously not known. However,
232 // experiments so far have shown that both *must* point to an instruction
233 // inside the vertex program, otherwise the GPU locks up.
234 // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
235 // CNTL_1_UNKNOWN points to instruction where last write to position takes place.
236 // Most likely this is used to ignore rest of the program in cases where group of verts arent visible.
237 // For some reason this "section" is sometimes accepted other instruction that have
238 // no relationship with position calculations.
240 #define R300_VAP_PVS_CNTL_1 0x22D0
241 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
242 # define R300_PVS_CNTL_1_POS_END_SHIFT 10
243 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
244 /* Addresses are relative the the vertex program parameters area. */
245 #define R300_VAP_PVS_CNTL_2 0x22D4
246 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
247 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
248 #define R300_VAP_PVS_CNTL_3 0x22D8
249 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
250 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
252 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
253 // immediate vertices */
254 #define R300_VAP_VTX_COLOR_R 0x2464
255 #define R300_VAP_VTX_COLOR_G 0x2468
256 #define R300_VAP_VTX_COLOR_B 0x246C
257 #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
258 #define R300_VAP_VTX_POS_0_Y_1 0x2494
259 #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
260 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
261 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
262 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
263 #define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */
267 /* These are values from r300_reg/r300_reg.h - they are known to be correct
268 and are here so we can use one register file instead of several
270 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
271 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
272 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
273 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
274 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
275 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
276 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
277 # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
279 #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
280 /* each of the following is 3 bits wide, specifies number
282 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
283 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
284 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
285 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
286 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
287 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
288 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
289 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
291 /* UNK30 seems to enables point to quad transformation on textures
292 (or something closely related to that).
293 This bit is rather fatal at the time being due to lackings at pixel shader side */
294 #define R300_GB_ENABLE 0x4008
295 # define R300_GB_POINT_STUFF_ENABLE (1<<0)
296 # define R300_GB_LINE_STUFF_ENABLE (1<<1)
297 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
298 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
299 # define R300_GB_UNK30 (1<<30)
300 /* each of the following is 2 bits wide */
301 #define R300_GB_TEX_REPLICATE 0
302 #define R300_GB_TEX_ST 1
303 #define R300_GB_TEX_STR 2
304 # define R300_GB_TEX0_SOURCE_SHIFT 16
305 # define R300_GB_TEX1_SOURCE_SHIFT 18
306 # define R300_GB_TEX2_SOURCE_SHIFT 20
307 # define R300_GB_TEX3_SOURCE_SHIFT 22
308 # define R300_GB_TEX4_SOURCE_SHIFT 24
309 # define R300_GB_TEX5_SOURCE_SHIFT 26
310 # define R300_GB_TEX6_SOURCE_SHIFT 28
311 # define R300_GB_TEX7_SOURCE_SHIFT 30
313 /* MSPOS - positions for multisample antialiasing (?) */
314 #define R300_GB_MSPOS0 0x4010
315 /* shifts - each of the fields is 4 bits */
316 # define R300_GB_MSPOS0__MS_X0_SHIFT 0
317 # define R300_GB_MSPOS0__MS_Y0_SHIFT 4
318 # define R300_GB_MSPOS0__MS_X1_SHIFT 8
319 # define R300_GB_MSPOS0__MS_Y1_SHIFT 12
320 # define R300_GB_MSPOS0__MS_X2_SHIFT 16
321 # define R300_GB_MSPOS0__MS_Y2_SHIFT 20
322 # define R300_GB_MSPOS0__MSBD0_Y 24
323 # define R300_GB_MSPOS0__MSBD0_X 28
325 #define R300_GB_MSPOS1 0x4014
326 # define R300_GB_MSPOS1__MS_X3_SHIFT 0
327 # define R300_GB_MSPOS1__MS_Y3_SHIFT 4
328 # define R300_GB_MSPOS1__MS_X4_SHIFT 8
329 # define R300_GB_MSPOS1__MS_Y4_SHIFT 12
330 # define R300_GB_MSPOS1__MS_X5_SHIFT 16
331 # define R300_GB_MSPOS1__MS_Y5_SHIFT 20
332 # define R300_GB_MSPOS1__MSBD1 24
335 #define R300_GB_TILE_CONFIG 0x4018
336 # define R300_GB_TILE_ENABLE (1<<0)
337 # define R300_GB_TILE_PIPE_COUNT_RV300 0
338 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
339 # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
340 # define R300_GB_TILE_SIZE_8 0
341 # define R300_GB_TILE_SIZE_16 (1<<4)
342 # define R300_GB_TILE_SIZE_32 (2<<4)
343 # define R300_GB_SUPER_SIZE_1 (0<<6)
344 # define R300_GB_SUPER_SIZE_2 (1<<6)
345 # define R300_GB_SUPER_SIZE_4 (2<<6)
346 # define R300_GB_SUPER_SIZE_8 (3<<6)
347 # define R300_GB_SUPER_SIZE_16 (4<<6)
348 # define R300_GB_SUPER_SIZE_32 (5<<6)
349 # define R300_GB_SUPER_SIZE_64 (6<<6)
350 # define R300_GB_SUPER_SIZE_128 (7<<6)
351 # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
352 # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
353 # define R300_GB_SUPER_TILE_A 0
354 # define R300_GB_SUPER_TILE_B (1<<15)
355 # define R300_GB_SUBPIXEL_1_12 0
356 # define R300_GB_SUBPIXEL_1_16 (1<<16)
358 #define R300_GB_FIFO_SIZE 0x4024
359 /* each of the following is 2 bits wide */
360 #define R300_GB_FIFO_SIZE_32 0
361 #define R300_GB_FIFO_SIZE_64 1
362 #define R300_GB_FIFO_SIZE_128 2
363 #define R300_GB_FIFO_SIZE_256 3
364 # define R300_SC_IFIFO_SIZE_SHIFT 0
365 # define R300_SC_TZFIFO_SIZE_SHIFT 2
366 # define R300_SC_BFIFO_SIZE_SHIFT 4
368 # define R300_US_OFIFO_SIZE_SHIFT 12
369 # define R300_US_WFIFO_SIZE_SHIFT 14
370 /* the following use the same constants as above, but meaning is
371 is times 2 (i.e. instead of 32 words it means 64 */
372 # define R300_RS_TFIFO_SIZE_SHIFT 6
373 # define R300_RS_CFIFO_SIZE_SHIFT 8
374 # define R300_US_RAM_SIZE_SHIFT 10
375 /* watermarks, 3 bits wide */
376 # define R300_RS_HIGHWATER_COL_SHIFT 16
377 # define R300_RS_HIGHWATER_TEX_SHIFT 19
378 # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
379 # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
381 #define R300_GB_SELECT 0x401C
382 # define R300_GB_FOG_SELECT_C0A 0
383 # define R300_GB_FOG_SELECT_C1A 1
384 # define R300_GB_FOG_SELECT_C2A 2
385 # define R300_GB_FOG_SELECT_C3A 3
386 # define R300_GB_FOG_SELECT_1_1_W 4
387 # define R300_GB_FOG_SELECT_Z 5
388 # define R300_GB_DEPTH_SELECT_Z 0
389 # define R300_GB_DEPTH_SELECT_1_1_W (1<<3)
390 # define R300_GB_W_SELECT_1_W 0
391 # define R300_GB_W_SELECT_1 (1<<4)
393 #define R300_GB_AA_CONFIG 0x4020
394 # define R300_AA_ENABLE 0x01
395 # define R300_AA_SUBSAMPLES_2 0
396 # define R300_AA_SUBSAMPLES_3 (1<<1)
397 # define R300_AA_SUBSAMPLES_4 (2<<1)
398 # define R300_AA_SUBSAMPLES_6 (3<<1)
403 /* The upper enable bits are guessed, based on fglrx reported limits. */
404 #define R300_TX_ENABLE 0x4104
405 # define R300_TX_ENABLE_0 (1 << 0)
406 # define R300_TX_ENABLE_1 (1 << 1)
407 # define R300_TX_ENABLE_2 (1 << 2)
408 # define R300_TX_ENABLE_3 (1 << 3)
409 # define R300_TX_ENABLE_4 (1 << 4)
410 # define R300_TX_ENABLE_5 (1 << 5)
411 # define R300_TX_ENABLE_6 (1 << 6)
412 # define R300_TX_ENABLE_7 (1 << 7)
413 # define R300_TX_ENABLE_8 (1 << 8)
414 # define R300_TX_ENABLE_9 (1 << 9)
415 # define R300_TX_ENABLE_10 (1 << 10)
416 # define R300_TX_ENABLE_11 (1 << 11)
417 # define R300_TX_ENABLE_12 (1 << 12)
418 # define R300_TX_ENABLE_13 (1 << 13)
419 # define R300_TX_ENABLE_14 (1 << 14)
420 # define R300_TX_ENABLE_15 (1 << 15)
422 /* The pointsize is given in multiples of 6. The pointsize can be
423 // enormous: Clear() renders a single point that fills the entire
425 #define R300_RE_POINTSIZE 0x421C
426 # define R300_POINTSIZE_Y_SHIFT 0
427 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
428 # define R300_POINTSIZE_X_SHIFT 16
429 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
430 # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
432 /* The line width is given in multiples of 6.
433 R300_LINE_CNT_UNK1 must be on to obtain expected results. */
434 #define R300_RE_LINE_CNT 0x4234
435 # define R300_LINESIZE_SHIFT 0
436 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
437 # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)
438 # define R300_LINE_CNT_UNK1 (1 << 17)
440 /* Linestipple factor. 3a088889 == 1.0, 3baaaaa9 == 10.0 */
441 #define R300_RE_LINE_STIPPLE_FACTOR 0x4238
443 #define R300_RE_SHADE_MODEL 0x4278
444 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa
445 # define R300_RE_SHADE_MODEL_FLAT 0x39595
448 #define R300_RE_POLYGON_MODE 0x4288
450 /* Not sure why there are duplicate of factor and constant values.
451 My best guess so far is that there are seperate zbiases for test and write.
452 Ordering might be wrong.
453 Some of the tests indicate that fgl has a fallback implementation of zbias
454 via pixel shaders. */
455 #define R300_RE_ZBIAS_T_FACTOR 0x42A4
456 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8
457 #define R300_RE_ZBIAS_W_FACTOR 0x42AC
458 #define R300_RE_ZBIAS_W_CONSTANT 0x42B0
460 /* This register needs to be set to (1<<1) for RV350 to correctly
461 perform depth test (see --vb-triangles in r300_demo)
462 Don't know about other chips. - Vladimir
463 This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
464 My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT).
465 One to enable depth test and one for depth write.
466 Yet this doesnt explain why depth writes work ...
468 #define R300_RE_OCCLUSION_CNTL 0x42B4
469 # define R300_OCCLUSION_ON (1<<1)
471 #define R300_RE_CULL_CNTL 0x42B8
472 # define R300_CULL_FRONT (1 << 0)
473 # define R300_CULL_BACK (1 << 1)
474 # define R300_FRONT_FACE_CCW (0 << 2)
475 # define R300_FRONT_FACE_CW (1 << 2)
478 /* BEGIN: Rasterization / Interpolators - many guesses
479 // 0_UNKNOWN_18 has always been set except for clear operations.
480 // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
481 // on the vertex program, *not* the fragment program) */
482 #define R300_RS_CNTL_0 0x4300
483 # define R300_RS_CNTL_TC_CNT_SHIFT 2
484 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
485 # define R300_RS_CNTL_0_UNKNOWN_7 (1 << 7) /* Number of color interpolators used (shifted by 7) */
486 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
487 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */
488 #define R300_RS_CNTL_1 0x4304
491 /* Only used for texture coordinates.
492 // Use the source field to route texture coordinate input from the vertex program
493 // to the desired interpolator. Note that the source field is relative to the
494 // outputs the vertex program *actually* writes. If a vertex program only writes
495 // texcoord[1], this will be source index 0.
496 // Set INTERP_USED on all interpolators that produce data used by the
497 // fragment program. INTERP_USED looks like a swizzling mask, but
498 // I haven't seen it used that way.
500 // Note: The _UNKNOWN constants are always set in their respective register.
501 // I don't know if this is necessary. */
502 #define R300_RS_INTERP_0 0x4310
503 #define R300_RS_INTERP_1 0x4314
504 # define R300_RS_INTERP_1_UNKNOWN 0x40
505 #define R300_RS_INTERP_2 0x4318
506 # define R300_RS_INTERP_2_UNKNOWN 0x80
507 #define R300_RS_INTERP_3 0x431C
508 # define R300_RS_INTERP_3_UNKNOWN 0xC0
509 #define R300_RS_INTERP_4 0x4320
510 #define R300_RS_INTERP_5 0x4324
511 #define R300_RS_INTERP_6 0x4328
512 #define R300_RS_INTERP_7 0x432C
513 # define R300_RS_INTERP_SRC_SHIFT 2
514 # define R300_RS_INTERP_SRC_MASK (7 << 2)
515 # define R300_RS_INTERP_USED 0x00D10000
517 /* These DWORDs control how vertex data is routed into fragment program
518 // registers, after interpolators. */
519 #define R300_RS_ROUTE_0 0x4330
520 #define R300_RS_ROUTE_1 0x4334
521 #define R300_RS_ROUTE_2 0x4338
522 #define R300_RS_ROUTE_3 0x433C /* GUESS */
523 #define R300_RS_ROUTE_4 0x4340 /* GUESS */
524 #define R300_RS_ROUTE_5 0x4344 /* GUESS */
525 #define R300_RS_ROUTE_6 0x4348 /* GUESS */
526 #define R300_RS_ROUTE_7 0x434C /* GUESS */
527 # define R300_RS_ROUTE_SOURCE_INTERP_0 0
528 # define R300_RS_ROUTE_SOURCE_INTERP_1 1
529 # define R300_RS_ROUTE_SOURCE_INTERP_2 2
530 # define R300_RS_ROUTE_SOURCE_INTERP_3 3
531 # define R300_RS_ROUTE_SOURCE_INTERP_4 4
532 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
533 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
534 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
535 # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
536 # define R300_RS_ROUTE_DEST_SHIFT 6
537 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
539 /* Special handling for color: When the fragment program uses color,
540 // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
541 // color register index. */
542 # define R300_RS_ROUTE_0_COLOR (1 << 14)
543 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
544 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
547 /* BEGIN: Scissors and cliprects
548 // There are four clipping rectangles. Their corner coordinates are inclusive.
549 // Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
550 // on whether the pixel is inside cliprects 0-3, respectively. For example,
551 // if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
552 // the number 3 (binary 0011).
553 // Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
554 // the pixel is rasterized.
556 // In addition to this, there is a scissors rectangle. Only pixels inside the
557 // scissors rectangle are drawn. (coordinates are inclusive)
559 // For some reason, the top-left corner of the framebuffer is at (1440, 1440)
560 // for the purpose of clipping and scissors. */
561 #define R300_RE_CLIPRECT_TL_0 0x43B0
562 #define R300_RE_CLIPRECT_BR_0 0x43B4
563 #define R300_RE_CLIPRECT_TL_1 0x43B8
564 #define R300_RE_CLIPRECT_BR_1 0x43BC
565 #define R300_RE_CLIPRECT_TL_2 0x43C0
566 #define R300_RE_CLIPRECT_BR_2 0x43C4
567 #define R300_RE_CLIPRECT_TL_3 0x43C8
568 #define R300_RE_CLIPRECT_BR_3 0x43CC
569 # define R300_CLIPRECT_OFFSET 1440
570 # define R300_CLIPRECT_MASK 0x1FFF
571 # define R300_CLIPRECT_X_SHIFT 0
572 # define R300_CLIPRECT_X_MASK (0x1FFF << 0)
573 # define R300_CLIPRECT_Y_SHIFT 13
574 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
575 #define R300_RE_CLIPRECT_CNTL 0x43D0
576 # define R300_CLIP_OUT (1 << 0)
577 # define R300_CLIP_0 (1 << 1)
578 # define R300_CLIP_1 (1 << 2)
579 # define R300_CLIP_10 (1 << 3)
580 # define R300_CLIP_2 (1 << 4)
581 # define R300_CLIP_20 (1 << 5)
582 # define R300_CLIP_21 (1 << 6)
583 # define R300_CLIP_210 (1 << 7)
584 # define R300_CLIP_3 (1 << 8)
585 # define R300_CLIP_30 (1 << 9)
586 # define R300_CLIP_31 (1 << 10)
587 # define R300_CLIP_310 (1 << 11)
588 # define R300_CLIP_32 (1 << 12)
589 # define R300_CLIP_320 (1 << 13)
590 # define R300_CLIP_321 (1 << 14)
591 # define R300_CLIP_3210 (1 << 15)
594 #define R300_RE_SCISSORS_TL 0x43E0
595 #define R300_RE_SCISSORS_BR 0x43E4
596 # define R300_SCISSORS_OFFSET 1440
597 # define R300_SCISSORS_X_SHIFT 0
598 # define R300_SCISSORS_X_MASK (0x1FFF << 0)
599 # define R300_SCISSORS_Y_SHIFT 13
600 # define R300_SCISSORS_Y_MASK (0x1FFF << 13)
603 /* BEGIN: Texture specification
604 // The texture specification dwords are grouped by meaning and not by texture unit.
605 // This means that e.g. the offset for texture image unit N is found in register
606 // TX_OFFSET_0 + (4*N) */
607 #define R300_TX_FILTER_0 0x4400
608 # define R300_TX_REPEAT 0
609 # define R300_TX_MIRRORED 1
610 # define R300_TX_CLAMP 4
611 # define R300_TX_CLAMP_TO_EDGE 2
612 # define R300_TX_CLAMP_TO_BORDER 6
613 # define R300_TX_WRAP_S_SHIFT 0
614 # define R300_TX_WRAP_S_MASK (7 << 0)
615 # define R300_TX_WRAP_T_SHIFT 3
616 # define R300_TX_WRAP_T_MASK (7 << 3)
617 # define R300_TX_WRAP_Q_SHIFT 6
618 # define R300_TX_WRAP_Q_MASK (7 << 6)
619 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
620 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
621 # define R300_TX_MAG_FILTER_MASK (3 << 9)
622 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
623 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
624 # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11)
625 # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11)
626 # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
627 # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
629 /* NOTE: NEAREST doesnt seem to exist.
630 Im not seting MAG_FILTER_MASK and (3 << 11) on for all
631 anisotropy modes because that would void selected mag filter */
632 # define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
633 # define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
634 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
635 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
636 # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
637 # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
638 # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)
639 # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)
640 # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21)
641 # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)
642 # define R300_TX_MAX_ANISO_MASK (14 << 21)
644 #define R300_TX_UNK1_0 0x4440
645 # define R300_LOD_BIAS_MASK 0x1fff
647 #define R300_TX_SIZE_0 0x4480
648 # define R300_TX_WIDTHMASK_SHIFT 0
649 # define R300_TX_WIDTHMASK_MASK (2047 << 0)
650 # define R300_TX_HEIGHTMASK_SHIFT 11
651 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
652 # define R300_TX_SIZE_SHIFT 26 /* largest of width, height */
653 # define R300_TX_SIZE_MASK (15 << 26)
654 #define R300_TX_FORMAT_0 0x44C0
655 /* The interpretation of the format word by Wladimir van der Laan */
656 /* The X, Y, Z and W refer to the layout of the components.
657 They are given meanings as R, G, B and Alpha by the swizzle
659 # define R300_TX_FORMAT_X8 0x0
660 # define R300_TX_FORMAT_X16 0x1
661 # define R300_TX_FORMAT_Y4X4 0x2
662 # define R300_TX_FORMAT_Y8X8 0x3
663 # define R300_TX_FORMAT_Y16X16 0x4
664 # define R300_TX_FORMAT_Z3Y3X2 0x5
665 # define R300_TX_FORMAT_Z5Y6X5 0x6
666 # define R300_TX_FORMAT_Z6Y5X5 0x7
667 # define R300_TX_FORMAT_Z11Y11X10 0x8
668 # define R300_TX_FORMAT_Z10Y11X11 0x9
669 # define R300_TX_FORMAT_W4Z4Y4X4 0xA
670 # define R300_TX_FORMAT_W1Z5Y5X5 0xB
671 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
672 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
673 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
674 # define R300_TX_FORMAT_DXT1 0xF
675 # define R300_TX_FORMAT_DXT3 0x10
676 # define R300_TX_FORMAT_DXT5 0x11
677 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
678 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
679 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
680 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
681 /* 0x16 - some 16 bit green format.. ?? */
683 /* Floating point formats */
684 /* Note - hardware supports both 16 and 32 bit floating point */
685 # define R300_TX_FORMAT_FL_I16 0x18
686 # define R300_TX_FORMAT_FL_I16A16 0x19
687 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
688 # define R300_TX_FORMAT_FL_I32 0x1B
689 # define R300_TX_FORMAT_FL_I32A32 0x1C
690 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
691 /* alpha modes, convenience mostly */
692 /* if you have alpha, pick constant appropriate to the
693 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
694 # define R300_TX_FORMAT_ALPHA_1CH 0x000
695 # define R300_TX_FORMAT_ALPHA_2CH 0x200
696 # define R300_TX_FORMAT_ALPHA_4CH 0x600
697 # define R300_TX_FORMAT_ALPHA_NONE 0xA00
700 # define R300_TX_FORMAT_X 0
701 # define R300_TX_FORMAT_Y 1
702 # define R300_TX_FORMAT_Z 2
703 # define R300_TX_FORMAT_W 3
704 # define R300_TX_FORMAT_ZERO 4
705 # define R300_TX_FORMAT_ONE 5
706 # define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */
707 # define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */
709 # define R300_TX_FORMAT_B_SHIFT 18
710 # define R300_TX_FORMAT_G_SHIFT 15
711 # define R300_TX_FORMAT_R_SHIFT 12
712 # define R300_TX_FORMAT_A_SHIFT 9
713 /* Convenience macro to take care of layout and swizzling */
714 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) (\
715 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
716 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
717 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
718 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
719 | (R300_TX_FORMAT_##FMT) \
721 /* These can be ORed with result of R300_EASY_TX_FORMAT() */
722 /* We don't really know what they do. Take values from a constant color ? */
723 # define R300_TX_FORMAT_CONST_X (1<<5)
724 # define R300_TX_FORMAT_CONST_Y (2<<5)
725 # define R300_TX_FORMAT_CONST_Z (4<<5)
726 # define R300_TX_FORMAT_CONST_W (8<<5)
728 # define R300_TX_FORMAT_YUV_MODE 0x00800000
730 #define R300_TX_OFFSET_0 0x4540
731 /* BEGIN: Guess from R200 */
732 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
733 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
734 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
735 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
736 # define R300_TXO_OFFSET_MASK 0xffffffe0
737 # define R300_TXO_OFFSET_SHIFT 5
739 #define R300_TX_UNK4_0 0x4580
740 #define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 }
744 /* BEGIN: Fragment program instruction set
745 // Fragment programs are written directly into register space.
746 // There are separate instruction streams for texture instructions and ALU
748 // In order to synchronize these streams, the program is divided into up
749 // to 4 nodes. Each node begins with a number of TEX operations, followed
750 // by a number of ALU operations.
751 // The first node can have zero TEX ops, all subsequent nodes must have at least
753 // All nodes must have at least one ALU op.
755 // The index of the last node is stored in PFS_CNTL_0: A value of 0 means
756 // 1 node, a value of 3 means 4 nodes.
757 // The total amount of instructions is defined in PFS_CNTL_2. The offsets are
758 // offsets into the respective instruction streams, while *_END points to the
759 // last instruction relative to this offset. */
760 #define R300_PFS_CNTL_0 0x4600
761 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
762 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
763 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
764 #define R300_PFS_CNTL_1 0x4604
765 /* There is an unshifted value here which has so far always been equal to the
766 // index of the highest used temporary register. */
767 #define R300_PFS_CNTL_2 0x4608
768 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
769 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
770 # define R300_PFS_CNTL_ALU_END_SHIFT 6
771 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0)
772 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
773 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
774 # define R300_PFS_CNTL_TEX_END_SHIFT 18
775 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
778 /* Nodes are stored backwards. The last active node is always stored in
780 // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
781 // first node is stored in NODE_2, the second node is stored in NODE_3.
783 // Offsets are relative to the master offset from PFS_CNTL_2.
784 // LAST_NODE is set for the last node, and only for the last node. */
785 #define R300_PFS_NODE_0 0x4610
786 #define R300_PFS_NODE_1 0x4614
787 #define R300_PFS_NODE_2 0x4618
788 #define R300_PFS_NODE_3 0x461C
789 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0
790 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)
791 # define R300_PFS_NODE_ALU_END_SHIFT 6
792 # define R300_PFS_NODE_ALU_END_MASK (63 << 6)
793 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12
794 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
795 # define R300_PFS_NODE_TEX_END_SHIFT 17
796 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
797 # define R300_PFS_NODE_LAST_NODE (1 << 22)
800 // As far as I can tell, texture instructions cannot write into output
801 // registers directly. A subsequent ALU instruction is always necessary,
802 // even if it's just MAD o0, r0, 1, 0 */
803 #define R300_PFS_TEXI_0 0x4620
804 # define R300_FPITX_SRC_SHIFT 0
805 # define R300_FPITX_SRC_MASK (31 << 0)
806 # define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */
807 # define R300_FPITX_DST_SHIFT 6
808 # define R300_FPITX_DST_MASK (31 << 6)
809 # define R300_FPITX_IMAGE_SHIFT 11
810 # define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */
813 // The ALU instructions register blocks are enumerated according to the order
814 // in which fglrx. I assume there is space for 64 instructions, since
815 // each block has space for a maximum of 64 DWORDs, and this matches reported
818 // The basic functional block seems to be one MAD for each color and alpha,
819 // and an adder that adds all components after the MUL.
820 // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
821 // - DP4: Use OUTC_DP4, OUTA_DP4
822 // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
823 // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
824 // - CMP: If ARG2 < 0, return ARG1, else return ARG0
825 // - FLR: use FRC+MAD
826 // - XPD: use MAD+MAD
827 // - SGE, SLT: use MAD+CMP
828 // - RSQ: use ABS modifier for argument
829 // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP)
830 // into color register
831 // - apparently, there's no quick DST operation
832 // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
833 // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
834 // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
837 // First stage selects three sources from the available registers and
838 // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
839 // fglrx sorts the three source fields: Registers before constants,
840 // lower indices before higher indices; I do not know whether this is necessary.
841 // fglrx fills unused sources with "read constant 0"
842 // According to specs, you cannot select more than two different constants.
844 // Second stage selects the operands from the sources. This is defined in
845 // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
847 // Swizzling and negation happens in this stage, as well.
849 // Important: Color and alpha seem to be mostly separate, i.e. their sources
850 // selection appears to be fully independent (the register storage is probably
851 // physically split into a color and an alpha section).
852 // However (because of the apparent physical split), there is some interaction
853 // WRT swizzling. If, for example, you want to load an R component into an
854 // Alpha operand, this R component is taken from a *color* source, not from
855 // an alpha source. The corresponding register doesn't even have to appear in
856 // the alpha sources list. (I hope this alll makes sense to you)
858 // Destination selection
859 // The destination register index is in FPI1 (color) and FPI3 (alpha) together
861 // There are separate enable bits for writing into temporary registers
862 // (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT).
863 // You can write to both at once, or not write at all (the same index
864 // must be used for both).
866 // Note: There is a special form for LRP
867 // - Argument order is the same as in ARB_fragment_program.
868 // - Operation is MAD
869 // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
870 // - Set FPI0/FPI2_SPECIAL_LRP
871 // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */
872 #define R300_PFS_INSTR1_0 0x46C0
873 # define R300_FPI1_SRC0C_SHIFT 0
874 # define R300_FPI1_SRC0C_MASK (31 << 0)
875 # define R300_FPI1_SRC0C_CONST (1 << 5)
876 # define R300_FPI1_SRC1C_SHIFT 6
877 # define R300_FPI1_SRC1C_MASK (31 << 6)
878 # define R300_FPI1_SRC1C_CONST (1 << 11)
879 # define R300_FPI1_SRC2C_SHIFT 12
880 # define R300_FPI1_SRC2C_MASK (31 << 12)
881 # define R300_FPI1_SRC2C_CONST (1 << 17)
882 # define R300_FPI1_DSTC_SHIFT 18
883 # define R300_FPI1_DSTC_MASK (31 << 18)
884 # define R300_FPI1_DSTC_REG_X (1 << 23)
885 # define R300_FPI1_DSTC_REG_Y (1 << 24)
886 # define R300_FPI1_DSTC_REG_Z (1 << 25)
887 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26)
888 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)
889 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)
891 #define R300_PFS_INSTR3_0 0x47C0
892 # define R300_FPI3_SRC0A_SHIFT 0
893 # define R300_FPI3_SRC0A_MASK (31 << 0)
894 # define R300_FPI3_SRC0A_CONST (1 << 5)
895 # define R300_FPI3_SRC1A_SHIFT 6
896 # define R300_FPI3_SRC1A_MASK (31 << 6)
897 # define R300_FPI3_SRC1A_CONST (1 << 11)
898 # define R300_FPI3_SRC2A_SHIFT 12
899 # define R300_FPI3_SRC2A_MASK (31 << 12)
900 # define R300_FPI3_SRC2A_CONST (1 << 17)
901 # define R300_FPI3_DSTA_SHIFT 18
902 # define R300_FPI3_DSTA_MASK (31 << 18)
903 # define R300_FPI3_DSTA_REG (1 << 23)
904 # define R300_FPI3_DSTA_OUTPUT (1 << 24)
906 #define R300_PFS_INSTR0_0 0x48C0
907 # define R300_FPI0_ARGC_SRC0C_XYZ 0
908 # define R300_FPI0_ARGC_SRC0C_XXX 1
909 # define R300_FPI0_ARGC_SRC0C_YYY 2
910 # define R300_FPI0_ARGC_SRC0C_ZZZ 3
911 # define R300_FPI0_ARGC_SRC1C_XYZ 4
912 # define R300_FPI0_ARGC_SRC1C_XXX 5
913 # define R300_FPI0_ARGC_SRC1C_YYY 6
914 # define R300_FPI0_ARGC_SRC1C_ZZZ 7
915 # define R300_FPI0_ARGC_SRC2C_XYZ 8
916 # define R300_FPI0_ARGC_SRC2C_XXX 9
917 # define R300_FPI0_ARGC_SRC2C_YYY 10
918 # define R300_FPI0_ARGC_SRC2C_ZZZ 11
919 # define R300_FPI0_ARGC_SRC0A 12
920 # define R300_FPI0_ARGC_SRC1A 13
921 # define R300_FPI0_ARGC_SRC2A 14
922 # define R300_FPI0_ARGC_SRC1C_LRP 15
923 # define R300_FPI0_ARGC_ZERO 20
924 # define R300_FPI0_ARGC_ONE 21
925 # define R300_FPI0_ARGC_HALF 22 /* GUESS */
926 # define R300_FPI0_ARGC_SRC0C_YZX 23
927 # define R300_FPI0_ARGC_SRC1C_YZX 24
928 # define R300_FPI0_ARGC_SRC2C_YZX 25
929 # define R300_FPI0_ARGC_SRC0C_ZXY 26
930 # define R300_FPI0_ARGC_SRC1C_ZXY 27
931 # define R300_FPI0_ARGC_SRC2C_ZXY 28
932 # define R300_FPI0_ARGC_SRC0CA_WZY 29
933 # define R300_FPI0_ARGC_SRC1CA_WZY 30
934 # define R300_FPI0_ARGC_SRC2CA_WZY 31
936 # define R300_FPI0_ARG0C_SHIFT 0
937 # define R300_FPI0_ARG0C_MASK (31 << 0)
938 # define R300_FPI0_ARG0C_NEG (1 << 5)
939 # define R300_FPI0_ARG0C_ABS (1 << 6)
940 # define R300_FPI0_ARG1C_SHIFT 7
941 # define R300_FPI0_ARG1C_MASK (31 << 7)
942 # define R300_FPI0_ARG1C_NEG (1 << 12)
943 # define R300_FPI0_ARG1C_ABS (1 << 13)
944 # define R300_FPI0_ARG2C_SHIFT 14
945 # define R300_FPI0_ARG2C_MASK (31 << 14)
946 # define R300_FPI0_ARG2C_NEG (1 << 19)
947 # define R300_FPI0_ARG2C_ABS (1 << 20)
948 # define R300_FPI0_SPECIAL_LRP (1 << 21)
949 # define R300_FPI0_OUTC_MAD (0 << 23)
950 # define R300_FPI0_OUTC_DP3 (1 << 23)
951 # define R300_FPI0_OUTC_DP4 (2 << 23)
952 # define R300_FPI0_OUTC_MIN (4 << 23)
953 # define R300_FPI0_OUTC_MAX (5 << 23)
954 # define R300_FPI0_OUTC_CMP (8 << 23)
955 # define R300_FPI0_OUTC_FRC (9 << 23)
956 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
957 # define R300_FPI0_OUTC_SAT (1 << 30)
958 # define R300_FPI0_UNKNOWN_31 (1 << 31)
960 #define R300_PFS_INSTR2_0 0x49C0
961 # define R300_FPI2_ARGA_SRC0C_X 0
962 # define R300_FPI2_ARGA_SRC0C_Y 1
963 # define R300_FPI2_ARGA_SRC0C_Z 2
964 # define R300_FPI2_ARGA_SRC1C_X 3
965 # define R300_FPI2_ARGA_SRC1C_Y 4
966 # define R300_FPI2_ARGA_SRC1C_Z 5
967 # define R300_FPI2_ARGA_SRC2C_X 6
968 # define R300_FPI2_ARGA_SRC2C_Y 7
969 # define R300_FPI2_ARGA_SRC2C_Z 8
970 # define R300_FPI2_ARGA_SRC0A 9
971 # define R300_FPI2_ARGA_SRC1A 10
972 # define R300_FPI2_ARGA_SRC2A 11
973 # define R300_FPI2_ARGA_SRC1A_LRP 15
974 # define R300_FPI2_ARGA_ZERO 16
975 # define R300_FPI2_ARGA_ONE 17
976 # define R300_FPI2_ARGA_HALF 18 /* GUESS */
978 # define R300_FPI2_ARG0A_SHIFT 0
979 # define R300_FPI2_ARG0A_MASK (31 << 0)
980 # define R300_FPI2_ARG0A_NEG (1 << 5)
981 # define R300_FPI2_ARG1A_SHIFT 7
982 # define R300_FPI2_ARG1A_MASK (31 << 7)
983 # define R300_FPI2_ARG1A_NEG (1 << 12)
984 # define R300_FPI2_ARG2A_SHIFT 14
985 # define R300_FPI2_AEG2A_MASK (31 << 14)
986 # define R300_FPI2_ARG2A_NEG (1 << 19)
987 # define R300_FPI2_SPECIAL_LRP (1 << 21)
988 # define R300_FPI2_OUTA_MAD (0 << 23)
989 # define R300_FPI2_OUTA_DP4 (1 << 23)
990 # define R300_RPI2_OUTA_MIN (2 << 23)
991 # define R300_RPI2_OUTA_MAX (3 << 23)
992 # define R300_FPI2_OUTA_CMP (6 << 23)
993 # define R300_FPI2_OUTA_FRC (7 << 23)
994 # define R300_FPI2_OUTA_EX2 (8 << 23)
995 # define R300_FPI2_OUTA_LG2 (9 << 23)
996 # define R300_FPI2_OUTA_RCP (10 << 23)
997 # define R300_FPI2_OUTA_RSQ (11 << 23)
998 # define R300_FPI2_OUTA_SAT (1 << 30)
999 # define R300_FPI2_UNKNOWN_31 (1 << 31)
1003 #define R300_PP_ALPHA_TEST 0x4BD4
1004 # define R300_REF_ALPHA_MASK 0x000000ff
1005 # define R300_ALPHA_TEST_FAIL (0 << 8)
1006 # define R300_ALPHA_TEST_LESS (1 << 8)
1007 # define R300_ALPHA_TEST_LEQUAL (3 << 8)
1008 # define R300_ALPHA_TEST_EQUAL (2 << 8)
1009 # define R300_ALPHA_TEST_GEQUAL (6 << 8)
1010 # define R300_ALPHA_TEST_GREATER (4 << 8)
1011 # define R300_ALPHA_TEST_NEQUAL (5 << 8)
1012 # define R300_ALPHA_TEST_PASS (7 << 8)
1013 # define R300_ALPHA_TEST_OP_MASK (7 << 8)
1014 # define R300_ALPHA_TEST_ENABLE (1 << 11)
1017 /* Fragment program parameters in 7.16 floating point */
1018 #define R300_PFS_PARAM_0_X 0x4C00
1019 #define R300_PFS_PARAM_0_Y 0x4C04
1020 #define R300_PFS_PARAM_0_Z 0x4C08
1021 #define R300_PFS_PARAM_0_W 0x4C0C
1022 /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
1023 #define R300_PFS_PARAM_31_X 0x4DF0
1024 #define R300_PFS_PARAM_31_Y 0x4DF4
1025 #define R300_PFS_PARAM_31_Z 0x4DF8
1026 #define R300_PFS_PARAM_31_W 0x4DFC
1029 // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application
1030 // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same
1031 // function (both registers are always set up completely in any case)
1032 // - Most blend flags are simply copied from R200 and not tested yet */
1033 #define R300_RB3D_CBLEND 0x4E04
1034 #define R300_RB3D_ABLEND 0x4E08
1035 /* the following only appear in CBLEND */
1036 # define R300_BLEND_ENABLE (1 << 0)
1037 # define R300_BLEND_UNKNOWN (3 << 1)
1038 # define R300_BLEND_NO_SEPARATE (1 << 3)
1039 /* the following are shared between CBLEND and ABLEND */
1040 # define R300_FCN_MASK (3 << 12)
1041 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
1042 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
1043 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
1044 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
1045 # define R300_SRC_BLEND_GL_ZERO (32 << 16)
1046 # define R300_SRC_BLEND_GL_ONE (33 << 16)
1047 # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16)
1048 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
1049 # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16)
1050 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
1051 # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
1052 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
1053 # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16)
1054 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
1055 # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
1056 # define R300_SRC_BLEND_MASK (63 << 16)
1057 # define R300_DST_BLEND_GL_ZERO (32 << 24)
1058 # define R300_DST_BLEND_GL_ONE (33 << 24)
1059 # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24)
1060 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
1061 # define R300_DST_BLEND_GL_DST_COLOR (36 << 24)
1062 # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
1063 # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24)
1064 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
1065 # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24)
1066 # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
1067 # define R300_DST_BLEND_MASK (63 << 24)
1068 #define R300_RB3D_COLORMASK 0x4E0C
1069 # define R300_COLORMASK0_B (1<<0)
1070 # define R300_COLORMASK0_G (1<<1)
1071 # define R300_COLORMASK0_R (1<<2)
1072 # define R300_COLORMASK0_A (1<<3)
1075 #define R300_RB3D_COLOROFFSET0 0x4E28
1076 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
1077 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
1078 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
1079 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
1081 /* Bit 16: Larger tiles
1082 // Bit 17: 4x2 tiles
1083 // Bit 18: Extremely weird tile like, but some pixels duplicated? */
1084 #define R300_RB3D_COLORPITCH0 0x4E38
1085 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
1086 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
1087 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
1088 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1089 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1090 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1091 # define R300_COLOR_UNKNOWN_22_23 (3 << 22) /* GUESS: Format? - (6<<21) for RGBA? */
1092 #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
1093 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1094 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1097 /* Guess by Vladimir.
1098 // Set to 0A before 3D operations, set to 02 afterwards. */
1099 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
1100 # define R300_RB3D_DSTCACHE_02 0x00000002
1101 # define R300_RB3D_DSTCACHE_0A 0x0000000A
1104 /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */
1105 /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */
1106 #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
1107 # define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */
1108 # define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */
1109 # define R300_RB3D_Z_TEST 0x00000012
1110 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1111 # define R300_RB3D_Z_WRITE_ONLY 0x00000006
1113 # define R300_RB3D_Z_TEST 0x00000012
1114 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1115 # define R300_RB3D_Z_WRITE_ONLY 0x00000006
1116 # define R300_RB3D_STENCIL_ENABLE 0x00000001
1118 #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1120 # define R300_ZS_NEVER 0
1121 # define R300_ZS_LESS 1
1122 # define R300_ZS_LEQUAL 2
1123 # define R300_ZS_EQUAL 3
1124 # define R300_ZS_GEQUAL 4
1125 # define R300_ZS_GREATER 5
1126 # define R300_ZS_NOTEQUAL 6
1127 # define R300_ZS_ALWAYS 7
1128 # define R300_ZS_MASK 7
1130 # define R300_ZS_KEEP 0
1131 # define R300_ZS_ZERO 1
1132 # define R300_ZS_REPLACE 2
1133 # define R300_ZS_INCR 3
1134 # define R300_ZS_DECR 4
1135 # define R300_ZS_INVERT 5
1136 # define R300_ZS_INCR_WRAP 6
1137 # define R300_ZS_DECR_WRAP 7
1139 /* front and back refer to operations done for front
1140 and back faces, i.e. separate stencil function support */
1141 # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
1142 # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
1143 # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
1144 # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
1145 # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
1146 # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15
1147 # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18
1148 # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
1149 # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
1153 #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
1154 # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
1155 # define R300_RB3D_ZS2_STENCIL_MASK 0xFF
1156 # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
1157 # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
1160 #define R300_RB3D_DEPTHOFFSET 0x4F20
1161 #define R300_RB3D_DEPTHPITCH 0x4F24
1162 # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
1163 # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
1164 # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
1165 # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1166 # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1167 # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1169 /* BEGIN: Vertex program instruction set
1170 // Every instruction is four dwords long:
1171 // DWORD 0: output and opcode
1172 // DWORD 1: first argument
1173 // DWORD 2: second argument
1174 // DWORD 3: third argument
1177 // - ABS r, a is implemented as MAX r, a, -a
1178 // - MOV is implemented as ADD to zero
1179 // - XPD is implemented as MUL + MAD
1180 // - FLR is implemented as FRC + ADD
1181 // - apparently, fglrx tries to schedule instructions so that there is at least
1182 // one instruction between the write to a temporary and the first read
1183 // from said temporary; however, violations of this scheduling are allowed
1184 // - register indices seem to be unrelated with OpenGL aliasing to conventional state
1185 // - only one attribute and one parameter can be loaded at a time; however, the
1186 // same attribute/parameter can be used for more than one argument
1187 // - the second software argument for POW is the third hardware argument (no idea why)
1188 // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1190 // There is some magic surrounding LIT:
1191 // The single argument is replicated across all three inputs, but swizzled:
1192 // First argument: xyzy
1193 // Second argument: xyzx
1194 // Third argument: xyzw
1195 // Whenever the result is used later in the fragment program, fglrx forces x and w
1196 // to be 1.0 in the input selection; I don't know whether this is strictly necessary */
1197 #define R300_VPI_OUT_OP_DOT (1 << 0)
1198 #define R300_VPI_OUT_OP_MUL (2 << 0)
1199 #define R300_VPI_OUT_OP_ADD (3 << 0)
1200 #define R300_VPI_OUT_OP_MAD (4 << 0)
1201 #define R300_VPI_OUT_OP_DST (5 << 0)
1202 #define R300_VPI_OUT_OP_FRC (6 << 0)
1203 #define R300_VPI_OUT_OP_MAX (7 << 0)
1204 #define R300_VPI_OUT_OP_MIN (8 << 0)
1205 #define R300_VPI_OUT_OP_SGE (9 << 0)
1206 #define R300_VPI_OUT_OP_SLT (10 << 0)
1207 #define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1208 #define R300_VPI_OUT_OP_EXP (65 << 0)
1209 #define R300_VPI_OUT_OP_LOG (66 << 0)
1210 #define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */
1211 #define R300_VPI_OUT_OP_LIT (68 << 0)
1212 #define R300_VPI_OUT_OP_POW (69 << 0)
1213 #define R300_VPI_OUT_OP_RCP (70 << 0)
1214 #define R300_VPI_OUT_OP_RSQ (72 << 0)
1215 #define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1216 #define R300_VPI_OUT_OP_EX2 (75 << 0)
1217 #define R300_VPI_OUT_OP_LG2 (76 << 0)
1218 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1220 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1221 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1222 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1224 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
1225 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */
1227 #define R300_VPI_OUT_WRITE_X (1 << 20)
1228 #define R300_VPI_OUT_WRITE_Y (1 << 21)
1229 #define R300_VPI_OUT_WRITE_Z (1 << 22)
1230 #define R300_VPI_OUT_WRITE_W (1 << 23)
1232 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
1233 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1234 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1235 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1236 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */
1238 #define R300_VPI_IN_REG_INDEX_SHIFT 5
1239 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */
1241 /* The R300 can select components from the input register arbitrarily.
1242 // Use the following constants, shifted by the component shift you
1243 // want to select */
1244 #define R300_VPI_IN_SELECT_X 0
1245 #define R300_VPI_IN_SELECT_Y 1
1246 #define R300_VPI_IN_SELECT_Z 2
1247 #define R300_VPI_IN_SELECT_W 3
1248 #define R300_VPI_IN_SELECT_ZERO 4
1249 #define R300_VPI_IN_SELECT_ONE 5
1250 #define R300_VPI_IN_SELECT_MASK 7
1252 #define R300_VPI_IN_X_SHIFT 13
1253 #define R300_VPI_IN_Y_SHIFT 16
1254 #define R300_VPI_IN_Z_SHIFT 19
1255 #define R300_VPI_IN_W_SHIFT 22
1257 #define R300_VPI_IN_NEG_X (1 << 25)
1258 #define R300_VPI_IN_NEG_Y (1 << 26)
1259 #define R300_VPI_IN_NEG_Z (1 << 27)
1260 #define R300_VPI_IN_NEG_W (1 << 28)
1263 //BEGIN: Packet 3 commands
1265 // A primitive emission dword.
1266 #define R300_PRIM_TYPE_NONE (0 << 0)
1267 #define R300_PRIM_TYPE_POINT (1 << 0)
1268 #define R300_PRIM_TYPE_LINE (2 << 0)
1269 #define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
1270 #define R300_PRIM_TYPE_TRI_LIST (4 << 0)
1271 #define R300_PRIM_TYPE_TRI_FAN (5 << 0)
1272 #define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
1273 #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1274 #define R300_PRIM_TYPE_RECT_LIST (8 << 0)
1275 #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1276 #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1277 #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200)
1278 #define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
1279 #define R300_PRIM_TYPE_QUADS (13 << 0)
1280 #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
1281 #define R300_PRIM_TYPE_POLYGON (15 << 0)
1282 #define R300_PRIM_TYPE_MASK 0xF
1283 #define R300_PRIM_WALK_IND (1 << 4)
1284 #define R300_PRIM_WALK_LIST (2 << 4)
1285 #define R300_PRIM_WALK_RING (3 << 4)
1286 #define R300_PRIM_WALK_MASK (3 << 4)
1287 #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200)
1288 #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS
1289 #define R300_PRIM_NUM_VERTICES_SHIFT 16
1291 // Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
1292 // Two parameter dwords:
1293 // 0. The first parameter appears to be always 0
1294 // 1. The second parameter is a standard primitive emission dword.
1295 #define R300_PACKET3_3D_DRAW_VBUF 0x00002800
1297 // Specify the full set of vertex arrays as (address, stride).
1298 // The first parameter is the number of vertex arrays specified.
1299 // The rest of the command is a variable length list of blocks, where
1300 // each block is three dwords long and specifies two arrays.
1301 // The first dword of a block is split into two words, the lower significant
1302 // word refers to the first array, the more significant word to the second
1303 // array in the block.
1304 // The low byte of each word contains the size of an array entry in dwords,
1305 // the high byte contains the stride of the array.
1306 // The second dword of a block contains the pointer to the first array,
1307 // the third dword of a block contains the pointer to the second array.
1308 // Note that if the total number of arrays is odd, the third dword of
1309 // the last block is omitted.
1310 #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
1312 #define R300_PACKET3_INDX_BUFFER 0x00003300
1313 # define R300_EB_UNK1_SHIFT 24
1314 # define R300_EB_UNK1 (0x80<<24)
1315 # define R300_EB_UNK2 0x0810
1316 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
1320 #endif /* _R300_REG_H */
projects / mesa.git / blob