5 This file contains registers and constants for the R300. They have been
6 found mostly by examining command buffers captured using glxtest, as well
7 as by extrapolating some known registers and constants from the R200.
9 I am fairly certain that they are correct unless stated otherwise in comments.
12 #define R300_SE_VPORT_XSCALE 0x1D98
13 #define R300_SE_VPORT_XOFFSET 0x1D9C
14 #define R300_SE_VPORT_YSCALE 0x1DA0
15 #define R300_SE_VPORT_YOFFSET 0x1DA4
16 #define R300_SE_VPORT_ZSCALE 0x1DA8
17 #define R300_SE_VPORT_ZOFFSET 0x1DAC
20 // BEGIN: Wild guesses
21 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
22 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
23 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
24 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) // GUESS
25 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) // GUESS
26 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) // GUESS
27 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) // GUESS
29 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
30 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
31 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
32 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
33 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
34 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
35 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
36 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
37 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
40 // BEGIN: Vertex data assembly - lots of uncertainties
42 // Where do we get our vertex data?
44 // Vertex data either comes either from immediate mode registers or from
46 // There appears to be no mixed mode (though we can force the pitch of
47 // vertex arrays to 0, effectively reusing the same element over and over
50 // Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
51 // if these registers influence vertex array processing.
53 // Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
55 // In both cases, vertex attributes are then passed through INPUT_ROUTE.
57 // Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
58 // into the vertex processor's input registers.
59 // The first word routes the first input, the second word the second, etc.
60 // The corresponding input is routed into the register with the given index.
61 // The list is ended by a word with INPUT_ROUTE_END set.
63 // Always set COMPONENTS_4 in immediate mode.
64 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
65 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
66 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
67 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
68 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
69 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) // GUESS
70 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
71 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) // GUESS
72 # define R300_VAP_INPUT_ROUTE_END (1 << 13)
73 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) // GUESS
74 # define R300_INPUT_ROUTE_FLOAT (1 << 14) // GUESS
75 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) // GUESS
76 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) // GUESS
77 #define R300_VAP_INPUT_ROUTE_0_1 0x2154
78 #define R300_VAP_INPUT_ROUTE_0_2 0x2158
79 #define R300_VAP_INPUT_ROUTE_0_3 0x215C
83 // - always set up to produce at least two attributes:
84 // if vertex program uses only position, fglrx will set normal, too
85 // - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal
86 #define R300_VAP_INPUT_CNTL_0 0x2180
87 # define R300_INPUT_CNTL_0_COLOR 0x00000001
88 #define R300_VAP_INPUT_CNTL_1 0x2184
89 # define R300_INPUT_CNTL_POS 0x00000001
90 # define R300_INPUT_CNTL_NORMAL 0x00000002
91 # define R300_INPUT_CNTL_COLOR 0x00000004
92 # define R300_INPUT_CNTL_TC0 0x00000400
93 # define R300_INPUT_CNTL_TC1 0x00000800
94 # define R300_INPUT_CNTL_TC2 0x00001000 // GUESS
95 # define R300_INPUT_CNTL_TC3 0x00002000 // GUESS
96 # define R300_INPUT_CNTL_TC4 0x00004000 // GUESS
97 # define R300_INPUT_CNTL_TC5 0x00008000 // GUESS
98 # define R300_INPUT_CNTL_TC6 0x00010000 // GUESS
99 # define R300_INPUT_CNTL_TC7 0x00020000 // GUESS
102 // Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
103 // are set to a swizzling bit pattern, other words are 0.
105 // In immediate mode, the pattern is always set to xyzw. In vertex array
106 // mode, the swizzling pattern is e.g. used to set zw components in texture
107 // coordinates with only tweo components.
108 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
109 # define R300_INPUT_ROUTE_SELECT_X 0
110 # define R300_INPUT_ROUTE_SELECT_Y 1
111 # define R300_INPUT_ROUTE_SELECT_Z 2
112 # define R300_INPUT_ROUTE_SELECT_W 3
113 # define R300_INPUT_ROUTE_SELECT_ZERO 4
114 # define R300_INPUT_ROUTE_SELECT_ONE 5
115 # define R300_INPUT_ROUTE_SELECT_MASK 7
116 # define R300_INPUT_ROUTE_X_SHIFT 0
117 # define R300_INPUT_ROUTE_Y_SHIFT 3
118 # define R300_INPUT_ROUTE_Z_SHIFT 6
119 # define R300_INPUT_ROUTE_W_SHIFT 9
120 # define R300_INPUT_ROUTE_ENABLE (15 << 12)
121 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
122 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
123 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
128 // BEGIN: Upload vertex program and data
129 // The programmable vertex shader unit has a memory bank of unknown size
130 // that can be written to in 16 byte units by writing the address into
131 // UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
133 // Pointers into the memory bank are always in multiples of 16 bytes.
135 // The memory bank is divided into areas with fixed meaning.
137 // Starting at address UPLOAD_PROGRAM: Vertex program instructions.
138 // Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
139 // whereas the difference between known addresses suggests size 512.
141 // Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
142 // Native reported limits and the VPI layout suggest size 256, whereas
143 // difference between known addresses suggests size 512.
145 // Multiple vertex programs and parameter sets can be loaded at once,
146 // which could explain the size discrepancy.
147 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
148 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
149 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
150 # define R300_PVS_UPLOAD_UNKNOWN 0x00000400
152 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
156 // I do not know the purpose of this register. However, I do know that
157 // it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
158 // for normal rendering.
159 #define R300_VAP_UNKNOWN_221C 0x221C
160 # define R300_221C_NORMAL 0x00000000
161 # define R300_221C_CLEAR 0x0001C000
164 // Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
165 // rendering commands and overwriting vertex program parameters.
166 // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
167 // avoids bugs caused by still running shaders reading bad data from memory.
168 #define R300_VAP_PVS_WAITIDLE 0x2284 // GUESS
170 // Absolutely no clue what this register is about.
171 #define R300_VAP_UNKNOWN_2288 0x2288
172 # define R300_2288_R300 0x00750000 // -- nh
173 # define R300_2288_RV350 0x0000FFFF // -- Vladimir
176 // Addresses are relative to the vertex program instruction area of the
177 // memory bank. PROGRAM_END points to the last instruction of the active
180 // The meaning of the two UNKNOWN fields is obviously not known. However,
181 // experiments so far have shown that both *must* point to an instruction
182 // inside the vertex program, otherwise the GPU locks up.
183 // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
184 // CNTL_1_UNKNOWN somewhere in the middle, but the criteria are not clear.
185 #define R300_VAP_PVS_CNTL_1 0x22D0
186 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
187 # define R300_PVS_CNTL_1_UNKNOWN_SHIFT 10
188 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
189 // Addresses are relative the the vertex program parameters area.
190 #define R300_VAP_PVS_CNTL_2 0x22D4
191 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
192 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
193 #define R300_VAP_PVS_CNTL_3 0x22D8
194 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
196 // The entire range from 0x2300 to 0x2AC inclusive seems to be used for
197 // immediate vertices
198 #define R300_VAP_VTX_COLOR_R 0x2464
199 #define R300_VAP_VTX_COLOR_G 0x2468
200 #define R300_VAP_VTX_COLOR_B 0x246C
201 #define R300_VAP_VTX_POS_0_X_1 0x2490 // used for glVertex2*()
202 #define R300_VAP_VTX_POS_0_Y_1 0x2494
203 #define R300_VAP_VTX_COLOR_PKD 0x249C // RGBA
204 #define R300_VAP_VTX_POS_0_X_2 0x24A0 // used for glVertex3*()
205 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
206 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
207 #define R300_VAP_VTX_END_OF_PKT 0x24AC // write 0 to indicate end of packet?
210 // BEGIN: !unverified!
211 #define R300_GB_TILE_CONFIG 0x4018
212 #define R300_GB_TILE_ENABLE (1 << 0)
213 #define R300_GB_TILE_PIPE_COUNT_R300 (0 << 1)
214 #define R300_GB_TILE_PIPE_COUNT_RV300 (3 << 1)
215 #define R300_GB_TILE_SIZE_8 (0 << 4)
216 #define R300_GB_TILE_SIZE_16 (1 << 4)
217 #define R300_GB_TILE_SIZE_32 (2 << 4)
218 #define R300_GB_SUPER_SIZE_1 (0 << 6)
219 #define R300_GB_SUPER_SIZE_2 (1 << 6)
220 #define R300_GB_SUPER_SIZE_4 (2 << 6)
221 #define R300_GB_SUPER_SIZE_8 (3 << 6)
222 #define R300_GB_SUPER_SIZE_16 (4 << 6)
223 #define R300_GB_SUPER_SIZE_32 (5 << 6)
224 #define R300_GB_SUPER_SIZE_64 (6 << 6)
225 #define R300_GB_SUPER_SIZE_128 (7 << 6)
226 #define R300_GB_SUPER_X_SHIFT 9 // 3 bits wide
227 #define R300_GB_SUPER_Y_SHIFT 12 // 3 bits wide
228 #define R300_GB_SUPER_TILE_A (0 << 15)
229 #define R300_GB_SUPER_TILE_B (1 << 15)
230 #define R300_GB_SUBPIXEL_1_12 (0 << 16)
231 #define R300_GB_SUBPIXEL_1_16 (1 << 16)
235 // The upper enable bits are guessed, based on fglrx reported limits.
236 #define R300_TX_ENABLE 0x4104
237 # define R300_TX_ENABLE_0 (1 << 0)
238 # define R300_TX_ENABLE_1 (1 << 1)
239 # define R300_TX_ENABLE_2 (1 << 2)
240 # define R300_TX_ENABLE_3 (1 << 3)
241 # define R300_TX_ENABLE_4 (1 << 4)
242 # define R300_TX_ENABLE_5 (1 << 5)
243 # define R300_TX_ENABLE_6 (1 << 6)
244 # define R300_TX_ENABLE_7 (1 << 7)
245 # define R300_TX_ENABLE_8 (1 << 8)
246 # define R300_TX_ENABLE_9 (1 << 9)
247 # define R300_TX_ENABLE_10 (1 << 10)
248 # define R300_TX_ENABLE_11 (1 << 11)
249 # define R300_TX_ENABLE_12 (1 << 12)
250 # define R300_TX_ENABLE_13 (1 << 13)
251 # define R300_TX_ENABLE_14 (1 << 14)
252 # define R300_TX_ENABLE_15 (1 << 15)
254 // No idea what the purpose is, but it is set to 421C_CLEAR just before
255 // issuing the clear command and then reset to 421C_NORMAL afterwards.
256 #define R300_UNKNOWN_421C 0x421C
257 # define R300_421C_NORMAL 0x00060006
258 # define R300_421C_CLEAR 0x0F000B40
260 // BEGIN: Rasterization / Interpolators - many guesses
261 // So far, 0_UNKOWN_7 has always been set.
262 // 0_UNKNOWN_18 has always been set except for clear operations.
263 // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
264 // on the vertex program, *not* the fragment program)
265 #define R300_RS_CNTL_0 0x4300
266 # define R300_RS_CNTL_TC_CNT_SHIFT 2
267 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
268 # define R300_RS_CNTL_0_UNKNOWN_7 (1 << 7)
269 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
270 // Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register.
271 #define R300_RS_CNTL_1 0x4304
274 // Only used for texture coordinates (color seems to be always interpolated).
275 // Use the source field to route texture coordinate input from the vertex program
276 // to the desired interpolator. Note that the source field is relative to the
277 // outputs the vertex program *actually* writes. If a vertex program only writes
278 // texcoord[1], this will be source index 0.
279 // Set INTERP_USED on all interpolators that produce data used by the
280 // fragment program. INTERP_USED looks like a swizzling mask, but
281 // I haven't seen it used that way.
283 // Note: The _UNKNOWN constants are always set in their respective register.
284 // I don't know if this is necessary.
285 #define R300_RS_INTERP_0 0x4310
286 #define R300_RS_INTERP_1 0x4314
287 # define R300_RS_INTERP_1_UNKNOWN 0x40
288 #define R300_RS_INTERP_2 0x4318
289 # define R300_RS_INTERP_2_UNKNOWN 0x80
290 #define R300_RS_INTERP_3 0x431C
291 # define R300_RS_INTERP_3_UNKNOWN 0xC0
292 #define R300_RS_INTERP_4 0x4320
293 #define R300_RS_INTERP_5 0x4324
294 #define R300_RS_INTERP_6 0x4328
295 #define R300_RS_INTERP_7 0x432C
296 # define R300_RS_INTERP_SRC_SHIFT 2
297 # define R300_RS_INTERP_SRC_MASK (7 << 2)
298 # define R300_RS_INTERP_USED 0x00D10000
300 // These DWORDs control how vertex data is routed into fragment program
301 // registers, after interpolators.
302 #define R300_RS_ROUTE_0 0x4330
303 #define R300_RS_ROUTE_1 0x4334
304 #define R300_RS_ROUTE_2 0x4338
305 #define R300_RS_ROUTE_3 0x433C // GUESS
306 #define R300_RS_ROUTE_4 0x4340 // GUESS
307 #define R300_RS_ROUTE_5 0x4344 // GUESS
308 #define R300_RS_ROUTE_6 0x4348 // GUESS
309 #define R300_RS_ROUTE_7 0x434C // GUESS
310 # define R300_RS_ROUTE_SOURCE_INTERP_0 0
311 # define R300_RS_ROUTE_SOURCE_INTERP_1 1
312 # define R300_RS_ROUTE_SOURCE_INTERP_2 2
313 # define R300_RS_ROUTE_SOURCE_INTERP_3 3
314 # define R300_RS_ROUTE_SOURCE_INTERP_4 4
315 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 // GUESS
316 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 // GUESS
317 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 // GUESS
318 # define R300_RS_ROUTE_ENABLE (1 << 3) // GUESS
319 # define R300_RS_ROUTE_DEST_SHIFT 6
320 # define R300_RS_ROUTE_DEST_MASK (31 << 6) // GUESS
322 // Special handling for color: When the fragment program uses color,
323 // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
324 // color register index.
325 # define R300_RS_ROUTE_0_COLOR (1 << 14)
326 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT (1 << 17)
327 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 6) // GUESS
330 // BEGIN: Texture specification
331 // The texture specification dwords are grouped by meaning and not by texture unit.
332 // This means that e.g. the offset for texture image unit N is found in register
333 // TX_OFFSET_0 + (4*N)
334 #define R300_TX_FILTER_0 0x4400
335 # define R300_TX_REPEAT 0
336 # define R300_TX_CLAMP_TO_EDGE 1
337 # define R300_TX_CLAMP 2
338 # define R300_TX_CLAMP_TO_BORDER 3
340 # define R300_TX_WRAP_S_SHIFT 1
341 # define R300_TX_WRAP_S_MASK (3 << 1)
342 # define R300_TX_WRAP_T_SHIFT 4
343 # define R300_TX_WRAP_T_MASK (3 << 4)
344 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
345 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
346 # define R300_TX_MAG_FILTER_MASK (3 << 9)
347 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
348 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
349 #define R300_TX_UNK1_0 0x4440
350 #define R300_TX_SIZE_0 0x4480
351 # define R300_TX_WIDTHMASK_SHIFT 0
352 # define R300_TX_WIDTHMASK_MASK (2047 << 0)
353 # define R300_TX_HEIGHTMASK_SHIFT 11
354 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
355 # define R300_TX_SIZE_SHIFT 26 // largest of width, height
356 # define R300_TX_SIZE_MASK (15 << 26)
357 #define R300_TX_FORMAT_0 0x44C0
358 #define R300_TX_OFFSET_0 0x4540
359 // BEGIN: Guess from R200
360 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
361 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
362 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
363 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
364 # define R300_TXO_OFFSET_MASK 0xffffffe0
365 # define R300_TXO_OFFSET_SHIFT 5
367 #define R300_TX_UNK4_0 0x4580
368 #define R300_TX_UNK5_0 0x45C0
371 // BEGIN: Fragment program instruction set
372 // Fragment programs are written directly into register space.
373 // There are separate instruction streams for texture instructions and ALU
375 // In order to synchronize these streams, the program is divided into up
376 // to 4 nodes. Each node begins with a number of TEX operations, followed
377 // by a number of ALU operations.
378 // The first node can have zero TEX ops, all subsequent nodes must have at least
380 // All nodes must have at least one ALU op.
382 // The index of the last node is stored in PFS_CNTL_0: A value of 0 means
383 // 1 node, a value of 3 means 4 nodes.
384 // The total amount of instructions is defined in PFS_CNTL_2. The offsets are
385 // offsets into the respective instruction streams, while *_END points to the
386 // last instruction relative to this offset.
387 #define R300_PFS_CNTL_0 0x4600
388 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
389 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
390 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
391 #define R300_PFS_CNTL_1 0x4604
392 // There is an unshifted value here which has so far always been equal to the
393 // index of the highest used temporary register.
394 #define R300_PFS_CNTL_2 0x4608
395 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
396 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
397 # define R300_PFS_CNTL_ALU_END_SHIFT 6
398 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0)
399 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
400 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) // GUESS
401 # define R300_PFS_CNTL_TEX_END_SHIFT 18
402 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) // GUESS
405 // Nodes are stored backwards. The last active node is always stored in
407 // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
408 // first node is stored in NODE_2, the second node is stored in NODE_3.
410 // Offsets are relative to the master offset from PFS_CNTL_2.
411 // LAST_NODE is set for the last node, and only for the last node.
412 #define R300_PFS_NODE_0 0x4610
413 #define R300_PFS_NODE_1 0x4614
414 #define R300_PFS_NODE_2 0x4618
415 #define R300_PFS_NODE_3 0x461C
416 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0
417 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)
418 # define R300_PFS_NODE_ALU_END_SHIFT 6
419 # define R300_PFS_NODE_ALU_END_MASK (63 << 6)
420 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12
421 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
422 # define R300_PFS_NODE_TEX_END_SHIFT 17
423 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
424 # define R300_PFS_NODE_LAST_NODE (1 << 22)
427 // As far as I can tell, texture instructions cannot write into output
428 // registers directly. A subsequent ALU instruction is always necessary,
429 // even if it's just MAD o0, r0, 1, 0
430 #define R300_PFS_TEXI_0 0x4620
431 # define R300_FPITX_SRC_SHIFT 0
432 # define R300_FPITX_SRC_MASK (31 << 0)
433 # define R300_FPITX_SRC_CONST (1 << 5) // GUESS
434 # define R300_FPITX_DST_SHIFT 6
435 # define R300_FPITX_DST_MASK (31 << 6)
436 # define R300_FPITX_IMAGE_SHIFT 11
437 # define R300_FPITX_IMAGE_MASK (15 << 11) // GUESS based on layout and native limits
440 // The ALU instructions register blocks are enumerated according to the order
441 // in which fglrx. I assume there is space for 64 instructions, since
442 // each block has space for a maximum of 64 DWORDs, and this matches reported
445 // The basic functional block seems to be one MAD for each color and alpha,
446 // and an adder that adds all components after the MUL.
447 // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
448 // - DP4: Use OUTC_DP4, OUTA_DP4
449 // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
450 // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
451 // - CMP: If ARG2 < 0, return ARG1, else return ARG0
452 // - FLR: use FRC+MAD
453 // - XPD: use MAD+MAD
454 // - SGE, SLT: use MAD+CMP
455 // - RSQ: use ABS modifier for argument
456 // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP)
457 // into color register
458 // - apparently, there's no quick DST operation
459 // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
460 // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
461 // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
464 // First stage selects three sources from the available registers and
465 // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
466 // fglrx sorts the three source fields: Registers before constants,
467 // lower indices before higher indices; I do not know whether this is necessary.
468 // fglrx fills unused sources with "read constant 0"
469 // According to specs, you cannot select more than two different constants.
471 // Second stage selects the operands from the sources. This is defined in
472 // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
474 // Swizzling and negation happens in this stage, as well.
476 // Important: Color and alpha seem to be mostly separate, i.e. their sources
477 // selection appears to be fully independent (the register storage is probably
478 // physically split into a color and an alpha section).
479 // However (because of the apparent physical split), there is some interaction
480 // WRT swizzling. If, for example, you want to load an R component into an
481 // Alpha operand, this R component is taken from a *color* source, not from
482 // an alpha source. The corresponding register doesn't even have to appear in
483 // the alpha sources list. (I hope this alll makes sense to you)
485 // Destination selection
486 // The destination register index is in FPI1 (color) and FPI3 (alpha) together
488 // There are separate enable bits for writing into temporary registers
489 // (DSTC_REG_*/DSTA_REG) and and program output registers (DSTC_OUTPUT_*/DSTA_OUTPUT).
490 // You can write to both at once, or not write at all (the same index
491 // must be used for both).
493 // Note: There is a special form for LRP
494 // - Argument order is the same as in ARB_fragment_program.
495 // - Operation is MAD
496 // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
497 // - Set FPI0/FPI2_SPECIAL_LRP
498 // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
499 #define R300_PFS_INSTR1_0 0x46C0
500 # define R300_FPI1_SRC0C_SHIFT 0
501 # define R300_FPI1_SRC0C_MASK (31 << 0)
502 # define R300_FPI1_SRC0C_CONST (1 << 5)
503 # define R300_FPI1_SRC1C_SHIFT 6
504 # define R300_FPI1_SRC1C_MASK (31 << 6)
505 # define R300_FPI1_SRC1C_CONST (1 << 11)
506 # define R300_FPI1_SRC2C_SHIFT 12
507 # define R300_FPI1_SRC2C_MASK (31 << 12)
508 # define R300_FPI1_SRC2C_CONST (1 << 17)
509 # define R300_FPI1_DSTC_SHIFT 18
510 # define R300_FPI1_DSTC_MASK (31 << 18)
511 # define R300_FPI1_DSTC_REG_X (1 << 23)
512 # define R300_FPI1_DSTC_REG_Y (1 << 24)
513 # define R300_FPI1_DSTC_REG_Z (1 << 25)
514 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26)
515 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)
516 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)
518 #define R300_PFS_INSTR3_0 0x47C0
519 # define R300_FPI3_SRC0A_SHIFT 0
520 # define R300_FPI3_SRC0A_MASK (31 << 0)
521 # define R300_FPI3_SRC0A_CONST (1 << 5)
522 # define R300_FPI3_SRC1A_SHIFT 6
523 # define R300_FPI3_SRC1A_MASK (31 << 6)
524 # define R300_FPI3_SRC1A_CONST (1 << 11)
525 # define R300_FPI3_SRC2A_SHIFT 12
526 # define R300_FPI3_SRC2A_MASK (31 << 12)
527 # define R300_FPI3_SRC2A_CONST (1 << 17)
528 # define R300_FPI3_DSTA_SHIFT 18
529 # define R300_FPI3_DSTA_MASK (31 << 18)
530 # define R300_FPI3_DSTA_REG (1 << 23)
531 # define R300_FPI3_DSTA_OUTPUT (1 << 24)
533 #define R300_PFS_INSTR0_0 0x48C0
534 # define R300_FPI0_ARGC_SRC0C_XYZ 0
535 # define R300_FPI0_ARGC_SRC0C_XXX 1
536 # define R300_FPI0_ARGC_SRC0C_YYY 2
537 # define R300_FPI0_ARGC_SRC0C_ZZZ 3
538 # define R300_FPI0_ARGC_SRC1C_XYZ 4
539 # define R300_FPI0_ARGC_SRC1C_XXX 5
540 # define R300_FPI0_ARGC_SRC1C_YYY 6
541 # define R300_FPI0_ARGC_SRC1C_ZZZ 7
542 # define R300_FPI0_ARGC_SRC2C_XYZ 8
543 # define R300_FPI0_ARGC_SRC2C_XXX 9
544 # define R300_FPI0_ARGC_SRC2C_YYY 10
545 # define R300_FPI0_ARGC_SRC2C_ZZZ 11
546 # define R300_FPI0_ARGC_SRC0A 12
547 # define R300_FPI0_ARGC_SRC1A 13
548 # define R300_FPI0_ARGC_SRC2A 14
549 # define R300_FPI0_ARGC_SRC1C_LRP 15
550 # define R300_FPI0_ARGC_ZERO 20
551 # define R300_FPI0_ARGC_ONE 21
552 # define R300_FPI0_ARGC_HALF 22 // GUESS
553 # define R300_FPI0_ARGC_SRC0C_YZX 23
554 # define R300_FPI0_ARGC_SRC1C_YZX 24
555 # define R300_FPI0_ARGC_SRC2C_YZX 25
556 # define R300_FPI0_ARGC_SRC0C_ZXY 26
557 # define R300_FPI0_ARGC_SRC1C_ZXY 27
558 # define R300_FPI0_ARGC_SRC2C_ZXY 28
559 # define R300_FPI0_ARGC_SRC0CA_WZY 29
560 # define R300_FPI0_ARGC_SRC1CA_WZY 30
561 # define R300_FPI0_ARGC_SRC2CA_WZY 31
563 # define R300_FPI0_ARG0C_SHIFT 0
564 # define R300_FPI0_ARG0C_MASK (31 << 0)
565 # define R300_FPI0_ARG0C_NEG (1 << 5)
566 # define R300_FPI0_ARG0C_ABS (1 << 6)
567 # define R300_FPI0_ARG1C_SHIFT 7
568 # define R300_FPI0_ARG1C_MASK (31 << 7)
569 # define R300_FPI0_ARG1C_NEG (1 << 12)
570 # define R300_FPI0_ARG1C_ABS (1 << 13)
571 # define R300_FPI0_ARG2C_SHIFT 14
572 # define R300_FPI0_ARG2C_MASK (31 << 14)
573 # define R300_FPI0_ARG2C_NEG (1 << 19)
574 # define R300_FPI0_ARG2C_ABS (1 << 20)
575 # define R300_FPI0_SPECIAL_LRP (1 << 21)
576 # define R300_FPI0_OUTC_MAD (0 << 23)
577 # define R300_FPI0_OUTC_DP3 (1 << 23)
578 # define R300_FPI0_OUTC_DP4 (2 << 23)
579 # define R300_FPI0_OUTC_MIN (4 << 23)
580 # define R300_FPI0_OUTC_MAX (5 << 23)
581 # define R300_FPI0_OUTC_CMP (8 << 23)
582 # define R300_FPI0_OUTC_FRC (9 << 23)
583 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
584 # define R300_FPI0_OUTC_SAT (1 << 30)
585 # define R300_FPI0_UNKNOWN_31 (1 << 31)
587 #define R300_PFS_INSTR2_0 0x49C0
588 # define R300_FPI2_ARGA_SRC0C_X 0
589 # define R300_FPI2_ARGA_SRC0C_Y 1
590 # define R300_FPI2_ARGA_SRC0C_Z 2
591 # define R300_FPI2_ARGA_SRC1C_X 3
592 # define R300_FPI2_ARGA_SRC1C_Y 4
593 # define R300_FPI2_ARGA_SRC1C_Z 5
594 # define R300_FPI2_ARGA_SRC2C_X 6
595 # define R300_FPI2_ARGA_SRC2C_Y 7
596 # define R300_FPI2_ARGA_SRC2C_Z 8
597 # define R300_FPI2_ARGA_SRC0A 9
598 # define R300_FPI2_ARGA_SRC1A 10
599 # define R300_FPI2_ARGA_SRC2A 11
600 # define R300_FPI2_ARGA_SRC1A_LRP 15
601 # define R300_FPI2_ARGA_ZERO 16
602 # define R300_FPI2_ARGA_ONE 17
603 # define R300_FPI2_ARGA_HALF 18 // GUESS
605 # define R300_FPI2_ARG0A_SHIFT 0
606 # define R300_FPI2_ARG0A_MASK (31 << 0)
607 # define R300_FPI2_ARG0A_NEG (1 << 5)
608 # define R300_FPI2_ARG1A_SHIFT 7
609 # define R300_FPI2_ARG1A_MASK (31 << 7)
610 # define R300_FPI2_ARG1A_NEG (1 << 12)
611 # define R300_FPI2_ARG2A_SHIFT 14
612 # define R300_FPI2_AEG2A_MASK (31 << 14)
613 # define R300_FPI2_ARG2A_NEG (1 << 19)
614 # define R300_FPI2_SPECIAL_LRP (1 << 21)
615 # define R300_FPI2_OUTA_MAD (0 << 23)
616 # define R300_FPI2_OUTA_DP4 (1 << 23)
617 # define R300_RPI2_OUTA_MIN (2 << 23)
618 # define R300_RPI2_OUTA_MAX (3 << 23)
619 # define R300_FPI2_OUTA_CMP (6 << 23)
620 # define R300_FPI2_OUTA_FRC (7 << 23)
621 # define R300_FPI2_OUTA_EX2 (8 << 23)
622 # define R300_FPI2_OUTA_LG2 (9 << 23)
623 # define R300_FPI2_OUTA_RCP (10 << 23)
624 # define R300_FPI2_OUTA_RSQ (11 << 23)
625 # define R300_FPI2_OUTA_SAT (1 << 30)
626 # define R300_FPI2_UNKNOWN_31 (1 << 31)
630 #define R300_PP_ALPHA_TEST 0x4BD4
631 # define R300_REF_ALPHA_MASK 0x000000ff
632 # define R300_ALPHA_TEST_FAIL (0 << 8)
633 # define R300_ALPHA_TEST_LESS (1 << 8)
634 # define R300_ALPHA_TEST_LEQUAL (2 << 8)
635 # define R300_ALPHA_TEST_EQUAL (3 << 8)
636 # define R300_ALPHA_TEST_GEQUAL (4 << 8)
637 # define R300_ALPHA_TEST_GREATER (5 << 8)
638 # define R300_ALPHA_TEST_NEQUAL (6 << 8)
639 # define R300_ALPHA_TEST_PASS (7 << 8)
640 # define R300_ALPHA_TEST_OP_MASK (7 << 8)
641 # define R300_ALPHA_TEST_ENABLE (1 << 11)
644 // Fragment program parameters in 7.16 floating point
645 #define R300_PFS_PARAM_0_X 0x4C00
646 #define R300_PFS_PARAM_0_Y 0x4C04
647 #define R300_PFS_PARAM_0_Z 0x4C08
648 #define R300_PFS_PARAM_0_W 0x4C0C
649 // GUESS: PARAM_31 is last, based on native limits reported by fglrx
650 #define R300_PFS_PARAM_31_X 0x4DF0
651 #define R300_PFS_PARAM_31_Y 0x4DF4
652 #define R300_PFS_PARAM_31_Z 0x4DF8
653 #define R300_PFS_PARAM_31_W 0x4DFC
656 // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application
657 // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same
658 // function (both registers are always set up completely in any case)
659 // - Most blend flags are simply copied from R200 and not tested yet
660 #define R300_RB3D_CBLEND 0x4E04
661 #define R300_RB3D_ABLEND 0x4E08
662 /* the following only appear in CBLEND */
663 # define R300_BLEND_ENABLE (1 << 0)
664 # define R300_BLEND_UNKNOWN (3 << 1)
665 # define R300_BLEND_NO_SEPARATE (1 << 3)
666 /* the following are shared between CBLEND and ABLEND */
667 # define R300_FCN_MASK (3 << 12)
668 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
669 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
670 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
671 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
672 # define R300_SRC_BLEND_GL_ZERO (32 << 16)
673 # define R300_SRC_BLEND_GL_ONE (33 << 16)
674 # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16)
675 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
676 # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16)
677 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
678 # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
679 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
680 # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16)
681 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
682 # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
683 # define R300_SRC_BLEND_MASK (63 << 16)
684 # define R300_DST_BLEND_GL_ZERO (32 << 24)
685 # define R300_DST_BLEND_GL_ONE (33 << 24)
686 # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24)
687 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
688 # define R300_DST_BLEND_GL_DST_COLOR (36 << 24)
689 # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
690 # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24)
691 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
692 # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24)
693 # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
694 # define R300_DST_BLEND_MASK (63 << 24)
695 #define R300_RB3D_COLORMASK 0x4E0C
696 # define R300_COLORMASK0_B (1<<0)
697 # define R300_COLORMASK0_G (1<<1)
698 # define R300_COLORMASK0_R (1<<2)
699 # define R300_COLORMASK0_A (1<<3)
702 #define R300_RB3D_COLOROFFSET0 0x4E28
703 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 // GUESS
704 #define R300_RB3D_COLOROFFSET1 0x4E2C // GUESS
705 #define R300_RB3D_COLOROFFSET2 0x4E30 // GUESS
706 #define R300_RB3D_COLOROFFSET3 0x4E34 // GUESS
708 // Bit 16: Larger tiles
710 // Bit 18: Extremely weird tile like, but some pixels duplicated?
711 #define R300_RB3D_COLORPITCH0 0x4E38
712 # define R300_COLORPITCH_MASK 0x00001FF8 // GUESS
713 # define R300_COLOR_TILE_ENABLE (1 << 16) // GUESS
714 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) // GUESS
715 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) // GUESS
716 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) // GUESS
717 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) // GUESS
718 # define R300_COLOR_UNKNOWN_22_23 (3 << 22) // GUESS: Format?
719 #define R300_RB3D_COLORPITCH1 0x4E3C // GUESS
720 #define R300_RB3D_COLORPITCH2 0x4E40 // GUESS
721 #define R300_RB3D_COLORPITCH3 0x4E44 // GUESS
724 // Guess by Vladimir.
725 // Set to 0A before 3D operations, set to 02 afterwards.
726 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
727 # define R300_RB3D_DSTCACHE_02 0x00000002
728 # define R300_RB3D_DSTCACHE_0A 0x0000000A
731 // There seems to be no "write only" setting, so use Z-test = ALWAYS for this.
732 #define R300_RB3D_ZCNTL_0 0x4F00
733 # define R300_RB3D_Z_DISABLED_1 0x00000010 // GUESS
734 # define R300_RB3D_Z_DISABLED_2 0x00000014 // GUESS
735 # define R300_RB3D_Z_TEST 0x00000012
736 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
737 #define R300_RB3D_ZCNTL_1 0x4F04
738 # define R300_RB3D_Z_TEST_NEVER (0 << 0) // GUESS (based on R200)
739 # define R300_RB3D_Z_TEST_LESS (1 << 0)
740 # define R300_RB3D_Z_TEST_LEQUAL (2 << 0)
741 # define R300_RB3D_Z_TEST_EQUAL (3 << 0) // GUESS
742 # define R300_RB3D_Z_TEST_GEQUAL (4 << 0) // GUESS
743 # define R300_RB3D_Z_TEST_GREATER (5 << 0) // GUESS
744 # define R300_RB3D_Z_TEST_NEQUAL (6 << 0)
745 # define R300_RB3D_Z_TEST_ALWAYS (7 << 0)
746 # define R300_RB3D_Z_TEST_MASK (7 << 0)
748 #define R300_RB3D_DEPTHOFFSET 0x4F20
749 #define R300_RB3D_DEPTHPITCH 0x4F24
750 # define R300_DEPTHPITCH_MASK 0x00001FF8 // GUESS
751 # define R300_DEPTH_TILE_ENABLE (1 << 16) // GUESS
752 # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) // GUESS
753 # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) // GUESS
754 # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) // GUESS
755 # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) // GUESS
757 // BEGIN: Vertex program instruction set
758 // Every instruction is four dwords long:
759 // DWORD 0: output and opcode
760 // DWORD 1: first argument
761 // DWORD 2: second argument
762 // DWORD 3: third argument
765 // - ABS r, a is implemented as MAX r, a, -a
766 // - MOV is implemented as ADD to zero
767 // - XPD is implemented as MUL + MAD
768 // - FLR is implemented as FRC + ADD
769 // - apparently, fglrx tries to schedule instructions so that there is at least
770 // one instruction between the write to a temporary and the first read
771 // from said temporary; however, violations of this scheduling are allowed
772 // - register indices seem to be unrelated with OpenGL aliasing to conventional state
773 // - only one attribute and one parameter can be loaded at a time; however, the
774 // same attribute/parameter can be used for more than one argument
775 // - the second software argument for POW is the third hardware argument (no idea why)
776 // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
778 // There is some magic surrounding LIT:
779 // The single argument is replicated across all three inputs, but swizzled:
780 // First argument: xyzy
781 // Second argument: xyzx
782 // Third argument: xyzw
783 // Whenever the result is used later in the fragment program, fglrx forces x and w
784 // to be 1.0 in the input selection; I don't know whether this is strictly necessary
785 #define R300_VPI_OUT_OP_DOT (1 << 0)
786 #define R300_VPI_OUT_OP_MUL (2 << 0)
787 #define R300_VPI_OUT_OP_ADD (3 << 0)
788 #define R300_VPI_OUT_OP_MAD (4 << 0)
789 #define R300_VPI_OUT_OP_FRC (6 << 0)
790 #define R300_VPI_OUT_OP_MAX (7 << 0)
791 #define R300_VPI_OUT_OP_MIN (8 << 0)
792 #define R300_VPI_OUT_OP_SGE (9 << 0)
793 #define R300_VPI_OUT_OP_SLT (10 << 0)
794 #define R300_VPI_OUT_OP_EXP (65 << 0)
795 #define R300_VPI_OUT_OP_LOG (66 << 0)
796 #define R300_VPI_OUT_OP_LIT (68 << 0)
797 #define R300_VPI_OUT_OP_POW (69 << 0)
798 #define R300_VPI_OUT_OP_RCP (70 << 0)
799 #define R300_VPI_OUT_OP_RSQ (72 << 0)
800 #define R300_VPI_OUT_OP_EX2 (75 << 0)
801 #define R300_VPI_OUT_OP_LG2 (76 << 0)
802 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
804 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
805 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
806 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
808 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
809 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) // GUESS based on fglrx native limits
811 #define R300_VPI_OUT_WRITE_X (1 << 20)
812 #define R300_VPI_OUT_WRITE_Y (1 << 21)
813 #define R300_VPI_OUT_WRITE_Z (1 << 22)
814 #define R300_VPI_OUT_WRITE_W (1 << 23)
816 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
817 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
818 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
819 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
820 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) // GUESS
822 #define R300_VPI_IN_REG_INDEX_SHIFT 5
823 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) // GUESS based on fglrx native limits
825 // The R300 can select components from the input register arbitrarily.
826 // Use the following constants, shifted by the component shift you
828 #define R300_VPI_IN_SELECT_X 0
829 #define R300_VPI_IN_SELECT_Y 1
830 #define R300_VPI_IN_SELECT_Z 2
831 #define R300_VPI_IN_SELECT_W 3
832 #define R300_VPI_IN_SELECT_ZERO 4
833 #define R300_VPI_IN_SELECT_ONE 5
834 #define R300_VPI_IN_SELECT_MASK 7
836 #define R300_VPI_IN_X_SHIFT 13
837 #define R300_VPI_IN_Y_SHIFT 16
838 #define R300_VPI_IN_Z_SHIFT 19
839 #define R300_VPI_IN_W_SHIFT 22
841 #define R300_VPI_IN_NEG_X (1 << 25)
842 #define R300_VPI_IN_NEG_Y (1 << 26)
843 #define R300_VPI_IN_NEG_Z (1 << 27)
844 #define R300_VPI_IN_NEG_W (1 << 28)
847 #endif // _R300_REG_H
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