src/mesa/drivers/dri/r300/r300_render.c

   1 /**************************************************************************
   2
   3 Copyright (C) 2004 Nicolai Haehnle.
   4
   5 All Rights Reserved.
   6
   7 Permission is hereby granted, free of charge, to any person obtaining a
   8 copy of this software and associated documentation files (the "Software"),
   9 to deal in the Software without restriction, including without limitation
  10 on the rights to use, copy, modify, merge, publish, distribute, sub
  11 license, and/or sell copies of the Software, and to permit persons to whom
  12 the Software is furnished to do so, subject to the following conditions:
  13
  14 The above copyright notice and this permission notice (including the next
  15 paragraph) shall be included in all copies or substantial portions of the
  16 Software.
  17
  18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21 ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24 USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26 **************************************************************************/
  27
  28 /**
  29  * \file
  30  *
  31  * \brief R300 Render (Vertex Buffer Implementation)
  32  *
  33  * The immediate implementation has been removed from CVS in favor of the vertex
  34  * buffer implementation.
  35  *
  36  * The render functions are called by the pipeline manager to render a batch of
  37  * primitives. They return TRUE to pass on to the next stage (i.e. software
  38  * rasterization) or FALSE to indicate that the pipeline has finished after
  39  * rendering something.
  40  *
  41  * When falling back to software TCL still attempt to use hardware
  42  * rasterization.
  43  *
  44  * I am not sure that the cache related registers are setup correctly, but
  45  * obviously this does work... Further investigation is needed.
  46  *
  47  * \author Nicolai Haehnle <prefect_@gmx.net>
  48  *
  49  * \todo Add immediate implementation back? Perhaps this is useful if there are
  50  * no bugs...
  51  */
  52
  53 #include "r300_render.h"
  54
  55 #include "main/glheader.h"
  56 #include "main/state.h"
  57 #include "main/imports.h"
  58 #include "main/enums.h"
  59 #include "main/macros.h"
  60 #include "main/context.h"
  61 #include "main/dd.h"
  62 #include "main/simple_list.h"
  63 #include "main/api_arrayelt.h"
  64 #include "swrast/swrast.h"
  65 #include "swrast_setup/swrast_setup.h"
  66 #include "vbo/vbo.h"
  67 #include "tnl/tnl.h"
  68 #include "tnl/t_vp_build.h"
  69 #include "radeon_reg.h"
  70 #include "radeon_macros.h"
  71 #include "r300_context.h"
  72 #include "r300_ioctl.h"
  73 #include "r300_state.h"
  74 #include "r300_reg.h"
  75 #include "r300_tex.h"
  76 #include "r300_emit.h"
  77 #include "r300_fragprog_common.h"
  78 #include "r300_swtcl.h"
  79
  80 /**
  81  * \brief Convert a OpenGL primitive type into a R300 primitive type.
  82  */
  83 int r300PrimitiveType(r300ContextPtr rmesa, int prim)
  84 {
  85         switch (prim & PRIM_MODE_MASK) {
  86         case GL_POINTS:
  87                 return R300_VAP_VF_CNTL__PRIM_POINTS;
  88                 break;
  89         case GL_LINES:
  90                 return R300_VAP_VF_CNTL__PRIM_LINES;
  91                 break;
  92         case GL_LINE_STRIP:
  93                 return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
  94                 break;
  95         case GL_LINE_LOOP:
  96                 return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
  97                 break;
  98         case GL_TRIANGLES:
  99                 return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
 100                 break;
 101         case GL_TRIANGLE_STRIP:
 102                 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
 103                 break;
 104         case GL_TRIANGLE_FAN:
 105                 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
 106                 break;
 107         case GL_QUADS:
 108                 return R300_VAP_VF_CNTL__PRIM_QUADS;
 109                 break;
 110         case GL_QUAD_STRIP:
 111                 return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
 112                 break;
 113         case GL_POLYGON:
 114                 return R300_VAP_VF_CNTL__PRIM_POLYGON;
 115                 break;
 116         default:
 117                 assert(0);
 118                 return -1;
 119                 break;
 120         }
 121 }
 122
 123 int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
 124 {
 125         int verts_off = 0;
 126
 127         switch (prim & PRIM_MODE_MASK) {
 128         case GL_POINTS:
 129                 verts_off = 0;
 130                 break;
 131         case GL_LINES:
 132                 verts_off = num_verts % 2;
 133                 break;
 134         case GL_LINE_STRIP:
 135                 if (num_verts < 2)
 136                         verts_off = num_verts;
 137                 break;
 138         case GL_LINE_LOOP:
 139                 if (num_verts < 2)
 140                         verts_off = num_verts;
 141                 break;
 142         case GL_TRIANGLES:
 143                 verts_off = num_verts % 3;
 144                 break;
 145         case GL_TRIANGLE_STRIP:
 146                 if (num_verts < 3)
 147                         verts_off = num_verts;
 148                 break;
 149         case GL_TRIANGLE_FAN:
 150                 if (num_verts < 3)
 151                         verts_off = num_verts;
 152                 break;
 153         case GL_QUADS:
 154                 verts_off = num_verts % 4;
 155                 break;
 156         case GL_QUAD_STRIP:
 157                 if (num_verts < 4)
 158                         verts_off = num_verts;
 159                 else
 160                         verts_off = num_verts % 2;
 161                 break;
 162         case GL_POLYGON:
 163                 if (num_verts < 3)
 164                         verts_off = num_verts;
 165                 break;
 166         default:
 167                 assert(0);
 168                 return -1;
 169                 break;
 170         }
 171
 172         return num_verts - verts_off;
 173 }
 174
 175 static void r300EmitElts(GLcontext * ctx, unsigned long n_elts)
 176 {
 177         r300ContextPtr rmesa = R300_CONTEXT(ctx);
 178         void *out;
 179         GLuint size;
 180
 181         size = ((rmesa->ind_buf.is_32bit ? 4 : 2) * n_elts + 3) & ~3;
 182
 183         radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
 184                              &rmesa->radeon.tcl.elt_dma_offset, size, 4);
 185         radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 186         out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 187         memcpy(out, rmesa->ind_buf.ptr, size);
 188         radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 189 }
 190
 191 static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
 192 {
 193         BATCH_LOCALS(&rmesa->radeon);
 194
 195     r300_emit_scissor(rmesa->radeon.glCtx);
 196         if (vertex_count > 0) {
 197                 int size;
 198
 199                 BEGIN_BATCH(10);
 200                 OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0);
 201                 if (rmesa->ind_buf.is_32bit) {
 202                         size = vertex_count;
 203                         OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
 204                           ((vertex_count + 0) << 16) | type |
 205                           R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
 206                 } else {
 207                         size = (vertex_count + 1) >> 1;
 208                         OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
 209                            ((vertex_count + 0) << 16) | type);
 210                 }
 211
 212                 if (!rmesa->radeon.radeonScreen->kernel_mm) {
 213                         OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
 214                         OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
 215                                  (R300_VAP_PORT_IDX0 >> 2));
 216                         OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
 217                                         rmesa->radeon.tcl.elt_dma_bo,
 218                                         rmesa->radeon.tcl.elt_dma_offset,
 219                                         RADEON_GEM_DOMAIN_GTT, 0, 0);
 220                         OUT_BATCH(size);
 221                 } else {
 222                         OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
 223                         OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
 224                                  (R300_VAP_PORT_IDX0 >> 2));
 225                         OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 226                         OUT_BATCH(size);
 227                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 228                                               rmesa->radeon.tcl.elt_dma_bo,
 229                                               RADEON_GEM_DOMAIN_GTT, 0, 0);
 230                 }
 231                 END_BATCH();
 232         }
 233 }
 234
 235 static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
 236 {
 237         BATCH_LOCALS(&rmesa->radeon);
 238         uint32_t voffset;
 239         int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 240         int i;
 241
 242         if (RADEON_DEBUG & DEBUG_VERTS)
 243                 fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
 244                         offset);
 245
 246         if (!rmesa->radeon.radeonScreen->kernel_mm) {
 247                 BEGIN_BATCH(sz+2+(nr * 2));
 248                 OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
 249                 OUT_BATCH(nr);
 250
 251                 for (i = 0; i + 1 < nr; i += 2) {
 252                         OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 253                                   (rmesa->radeon.tcl.aos[i].stride << 8) |
 254                                   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 255                                   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 256
 257                         voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 258                                 offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 259                         OUT_BATCH_RELOC(voffset,
 260                                         rmesa->radeon.tcl.aos[i].bo,
 261                                         voffset,
 262                                         RADEON_GEM_DOMAIN_GTT,
 263                                         0, 0);
 264                         voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 265                           offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 266                         OUT_BATCH_RELOC(voffset,
 267                                         rmesa->radeon.tcl.aos[i+1].bo,
 268                                         voffset,
 269                                         RADEON_GEM_DOMAIN_GTT,
 270                                         0, 0);
 271                 }
 272
 273                 if (nr & 1) {
 274                         OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 275                                   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 276                         voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 277                                 offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 278                         OUT_BATCH_RELOC(voffset,
 279                                         rmesa->radeon.tcl.aos[nr - 1].bo,
 280                                         voffset,
 281                                         RADEON_GEM_DOMAIN_GTT,
 282                                         0, 0);
 283                 }
 284                 END_BATCH();
 285         } else {
 286
 287                 BEGIN_BATCH(sz+2+(nr * 2));
 288                 OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
 289                 OUT_BATCH(nr);
 290
 291                 for (i = 0; i + 1 < nr; i += 2) {
 292                         OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 293                                   (rmesa->radeon.tcl.aos[i].stride << 8) |
 294                                   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 295                                   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 296
 297                         voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 298                                 offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 299                         OUT_BATCH(voffset);
 300                         voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 301                                 offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 302                         OUT_BATCH(voffset);
 303                 }
 304
 305                 if (nr & 1) {
 306                         OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 307                           (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 308                         voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 309                                 offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 310                         OUT_BATCH(voffset);
 311                 }
 312                 for (i = 0; i + 1 < nr; i += 2) {
 313                         voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 314                                 offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 315                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 316                                               rmesa->radeon.tcl.aos[i+0].bo,
 317                                               RADEON_GEM_DOMAIN_GTT,
 318                                               0, 0);
 319                         voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 320                                 offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 321                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 322                                               rmesa->radeon.tcl.aos[i+1].bo,
 323                                               RADEON_GEM_DOMAIN_GTT,
 324                                               0, 0);
 325                 }
 326                 if (nr & 1) {
 327                         voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 328                                 offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 329                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 330                                               rmesa->radeon.tcl.aos[nr-1].bo,
 331                                               RADEON_GEM_DOMAIN_GTT,
 332                                               0, 0);
 333                 }
 334                 END_BATCH();
 335         }
 336
 337 }
 338
 339 static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type)
 340 {
 341         BATCH_LOCALS(&rmesa->radeon);
 342
 343     r300_emit_scissor(rmesa->radeon.glCtx);
 344         BEGIN_BATCH(3);
 345         OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
 346         OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
 347         END_BATCH();
 348 }
 349
 350 void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
 351 {
 352         r300ContextPtr rmesa = R300_CONTEXT(ctx);
 353         BATCH_LOCALS(&rmesa->radeon);
 354         int type, num_verts;
 355
 356         type = r300PrimitiveType(rmesa, prim);
 357         num_verts = r300NumVerts(rmesa, end - start, prim);
 358
 359         if (type < 0 || num_verts <= 0)
 360                 return;
 361
 362         /* Make space for at least 64 dwords.
 363          * This is supposed to ensure that we can get all rendering
 364          * commands into a single command buffer.
 365          */
 366         rcommonEnsureCmdBufSpace(&rmesa->radeon, 128, __FUNCTION__);
 367
 368         if (rmesa->ind_buf.ptr) {
 369                 if (num_verts > 65535) {
 370                         /* not implemented yet */
 371                         WARN_ONCE("Too many elts\n");
 372                         return;
 373                 }
 374                 /* Note: The following is incorrect, but it's the best I can do
 375                  * without a major refactoring of how DMA memory is handled.
 376                  * The problem: Ensuring that both vertex arrays *and* index
 377                  * arrays are at the right position, and then ensuring that
 378                  * the LOAD_VBPNTR, DRAW_INDX and INDX_BUFFER packets are emitted
 379                  * at once.
 380                  *
 381                  * So why is the following incorrect? Well, it seems like
 382                  * allocating the index array might actually evict the vertex
 383                  * arrays. *sigh*
 384                  */
 385                 r300EmitElts(ctx, num_verts);
 386                 /* don't pass start if we are split up */
 387                 r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, 0);
 388                 if (rmesa->radeon.radeonScreen->kernel_mm) {
 389                         BEGIN_BATCH_NO_AUTOSTATE(2);
 390                         OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1);
 391                         OUT_BATCH(rmesa->radeon.tcl.aos[0].count);
 392                         END_BATCH();
 393                 }
 394                 r300FireEB(rmesa, num_verts, type);
 395         } else {
 396                 r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
 397                 r300FireAOS(rmesa, num_verts, type);
 398         }
 399         COMMIT_BATCH();
 400 }
 401
 402 static void r300RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage)
 403 {
 404         r300ContextPtr rmesa = R300_CONTEXT(ctx);
 405         int i;
 406         TNLcontext *tnl = TNL_CONTEXT(ctx);
 407         struct vertex_buffer *vb = &tnl->vb;
 408
 409         if (RADEON_DEBUG & DEBUG_PRIMS)
 410                 fprintf(stderr, "%s\n", __FUNCTION__);
 411
 412         r300UpdateShaders(rmesa);
 413         r300EmitArrays(ctx);
 414
 415         r300UpdateShaderStates(rmesa);
 416
 417         r300EmitCacheFlush(rmesa);
 418         radeonEmitState(&rmesa->radeon);
 419
 420         for (i = 0; i < vb->PrimitiveCount; i++) {
 421                 GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
 422                 GLuint start = vb->Primitive[i].start;
 423                 GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
 424                 r300RunRenderPrimitive(ctx, start, end, prim);
 425         }
 426
 427         r300EmitCacheFlush(rmesa);
 428
 429         radeonReleaseArrays(ctx, ~0);
 430 }
 431
 432
 433 static const char *getFallbackString(uint32_t bit)
 434 {
 435         switch (bit) {
 436                 case R300_FALLBACK_VERTEX_PROGRAM :
 437                         return "vertex program";
 438                 case R300_FALLBACK_LINE_SMOOTH:
 439                         return "smooth lines";
 440                 case R300_FALLBACK_POINT_SMOOTH:
 441                         return "smooth points";
 442                 case R300_FALLBACK_POLYGON_SMOOTH:
 443                         return "smooth polygons";
 444                 case R300_FALLBACK_LINE_STIPPLE:
 445                         return "line stipple";
 446                 case R300_FALLBACK_POLYGON_STIPPLE:
 447                         return "polygon stipple";
 448                 case R300_FALLBACK_STENCIL_TWOSIDE:
 449                         return "two-sided stencil";
 450                 case R300_FALLBACK_RENDER_MODE:
 451                         return "render mode != GL_RENDER";
 452                 case R300_FALLBACK_FRAGMENT_PROGRAM:
 453                         return "fragment program";
 454                 case R300_FALLBACK_AOS_LIMIT:
 455                         return "aos limit";
 456                 case R300_FALLBACK_INVALID_BUFFERS:
 457                         return "invalid buffers";
 458                 default:
 459                         return "unknown";
 460         }
 461 }
 462
 463 void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode)
 464 {
 465         TNLcontext *tnl = TNL_CONTEXT(ctx);
 466         r300ContextPtr rmesa = R300_CONTEXT(ctx);
 467         uint32_t old_fallback = rmesa->fallback;
 468         static uint32_t fallback_warn = 0;
 469
 470         if (mode) {
 471                 if ((fallback_warn & bit) == 0) {
 472                         _mesa_fprintf(stderr, "WARNING! Falling back to software for %s\n", getFallbackString(bit));
 473                         fallback_warn |= bit;
 474                 }
 475                 rmesa->fallback |= bit;
 476
 477                 /* update only if we change from no tcl fallbacks to some tcl fallbacks */
 478                 if (rmesa->options.hw_tcl_enabled) {
 479                         if (((old_fallback & R300_TCL_FALLBACK_MASK) == 0) &&
 480                                 ((bit & R300_TCL_FALLBACK_MASK) > 0)) {
 481                                 R300_STATECHANGE(rmesa, vap_cntl_status);
 482                                 rmesa->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
 483                         }
 484                 }
 485
 486                 /* update only if we change from no raster fallbacks to some raster fallbacks */
 487                 if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) &&
 488                         ((bit & R300_RASTER_FALLBACK_MASK) > 0)) {
 489
 490                         radeon_firevertices(&rmesa->radeon);
 491                         rmesa->radeon.swtcl.RenderIndex = ~0;
 492                         _swsetup_Wakeup( ctx );
 493                 }
 494         } else {
 495                 rmesa->fallback &= ~bit;
 496
 497                 /* update only if we have disabled all tcl fallbacks */
 498                 if (rmesa->options.hw_tcl_enabled) {
 499                         if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) {
 500                                 R300_STATECHANGE(rmesa, vap_cntl_status);
 501                                 rmesa->hw.vap_cntl_status.cmd[1] &= ~R300_VAP_TCL_BYPASS;
 502                         }
 503                 }
 504
 505                 /* update only if we have disabled all raster fallbacks */
 506                 if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) {
 507                         _swrast_flush( ctx );
 508
 509                         tnl->Driver.Render.Start = r300RenderStart;
 510                         tnl->Driver.Render.Finish = r300RenderFinish;
 511                         tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
 512                         tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
 513                         tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 514                         tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 515                         tnl->Driver.Render.Interp = _tnl_interp;
 516
 517                         _tnl_invalidate_vertex_state( ctx, ~0 );
 518                         _tnl_invalidate_vertices( ctx, ~0 );
 519                 }
 520         }
 521
 522 }
 523
 524 static GLboolean r300RunNonTCLRender(GLcontext * ctx,
 525                                      struct tnl_pipeline_stage *stage)
 526 {
 527         r300ContextPtr rmesa = R300_CONTEXT(ctx);
 528
 529         if (RADEON_DEBUG & DEBUG_PRIMS)
 530                 fprintf(stderr, "%s\n", __FUNCTION__);
 531
 532         if (rmesa->fallback & R300_RASTER_FALLBACK_MASK)
 533                 return GL_TRUE;
 534
 535         if (rmesa->options.hw_tcl_enabled == GL_FALSE)
 536                 return GL_TRUE;
 537
 538         r300RunRender(ctx, stage);
 539
 540         return GL_FALSE;
 541 }
 542
 543 const struct tnl_pipeline_stage _r300_render_stage = {
 544         "r300 Hardware Rasterization",
 545         NULL,
 546         NULL,
 547         NULL,
 548         NULL,
 549         r300RunNonTCLRender
 550 };