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[mesa.git] / src / mesa / drivers / dri / r300 / r300_state.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Nicolai Haehnle <prefect_@gmx.net>
36 */
37
38 #include "main/glheader.h"
39 #include "main/state.h"
40 #include "main/imports.h"
41 #include "main/enums.h"
42 #include "main/macros.h"
43 #include "main/context.h"
44 #include "main/dd.h"
45 #include "main/simple_list.h"
46 #include "main/api_arrayelt.h"
47 #include "main/texformat.h"
48
49 #include "swrast/swrast.h"
50 #include "swrast_setup/swrast_setup.h"
51 #include "shader/prog_parameter.h"
52 #include "shader/prog_statevars.h"
53 #include "vbo/vbo.h"
54 #include "tnl/tnl.h"
55
56 #include "r300_context.h"
57 #include "r300_ioctl.h"
58 #include "r300_state.h"
59 #include "r300_reg.h"
60 #include "r300_emit.h"
61 #include "r300_fragprog.h"
62 #include "r300_tex.h"
63
64 #include "drirenderbuffer.h"
65
66 extern int future_hw_tcl_on;
67 extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx);
68
69 static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4])
70 {
71 r300ContextPtr rmesa = R300_CONTEXT(ctx);
72
73 R300_STATECHANGE(rmesa, blend_color);
74
75 if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
76 GLuint r = IROUND(cf[0]*1023.0f);
77 GLuint g = IROUND(cf[1]*1023.0f);
78 GLuint b = IROUND(cf[2]*1023.0f);
79 GLuint a = IROUND(cf[3]*1023.0f);
80
81 rmesa->hw.blend_color.cmd[1] = r | (a << 16);
82 rmesa->hw.blend_color.cmd[2] = b | (g << 16);
83 } else {
84 GLubyte color[4];
85 CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]);
86 CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
87 CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
88 CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
89
90 rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0],
91 color[1], color[2]);
92 }
93 }
94
95 /**
96 * Calculate the hardware blend factor setting. This same function is used
97 * for source and destination of both alpha and RGB.
98 *
99 * \returns
100 * The hardware register value for the specified blend factor. This value
101 * will need to be shifted into the correct position for either source or
102 * destination factor.
103 *
104 * \todo
105 * Since the two cases where source and destination are handled differently
106 * are essentially error cases, they should never happen. Determine if these
107 * cases can be removed.
108 */
109 static int blend_factor(GLenum factor, GLboolean is_src)
110 {
111 switch (factor) {
112 case GL_ZERO:
113 return R300_BLEND_GL_ZERO;
114 break;
115 case GL_ONE:
116 return R300_BLEND_GL_ONE;
117 break;
118 case GL_DST_COLOR:
119 return R300_BLEND_GL_DST_COLOR;
120 break;
121 case GL_ONE_MINUS_DST_COLOR:
122 return R300_BLEND_GL_ONE_MINUS_DST_COLOR;
123 break;
124 case GL_SRC_COLOR:
125 return R300_BLEND_GL_SRC_COLOR;
126 break;
127 case GL_ONE_MINUS_SRC_COLOR:
128 return R300_BLEND_GL_ONE_MINUS_SRC_COLOR;
129 break;
130 case GL_SRC_ALPHA:
131 return R300_BLEND_GL_SRC_ALPHA;
132 break;
133 case GL_ONE_MINUS_SRC_ALPHA:
134 return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA;
135 break;
136 case GL_DST_ALPHA:
137 return R300_BLEND_GL_DST_ALPHA;
138 break;
139 case GL_ONE_MINUS_DST_ALPHA:
140 return R300_BLEND_GL_ONE_MINUS_DST_ALPHA;
141 break;
142 case GL_SRC_ALPHA_SATURATE:
143 return (is_src) ? R300_BLEND_GL_SRC_ALPHA_SATURATE :
144 R300_BLEND_GL_ZERO;
145 break;
146 case GL_CONSTANT_COLOR:
147 return R300_BLEND_GL_CONST_COLOR;
148 break;
149 case GL_ONE_MINUS_CONSTANT_COLOR:
150 return R300_BLEND_GL_ONE_MINUS_CONST_COLOR;
151 break;
152 case GL_CONSTANT_ALPHA:
153 return R300_BLEND_GL_CONST_ALPHA;
154 break;
155 case GL_ONE_MINUS_CONSTANT_ALPHA:
156 return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA;
157 break;
158 default:
159 fprintf(stderr, "unknown blend factor %x\n", factor);
160 return (is_src) ? R300_BLEND_GL_ONE : R300_BLEND_GL_ZERO;
161 break;
162 }
163 }
164
165 /**
166 * Sets both the blend equation and the blend function.
167 * This is done in a single
168 * function because some blend equations (i.e., \c GL_MIN and \c GL_MAX)
169 * change the interpretation of the blend function.
170 * Also, make sure that blend function and blend equation are set to their
171 * default value if color blending is not enabled, since at least blend
172 * equations GL_MIN and GL_FUNC_REVERSE_SUBTRACT will cause wrong results
173 * otherwise for unknown reasons.
174 */
175
176 /* helper function */
177 static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn,
178 int cbits, int funcA, int eqnA)
179 {
180 GLuint new_ablend, new_cblend;
181
182 #if 0
183 fprintf(stderr,
184 "eqnA=%08x funcA=%08x eqn=%08x func=%08x cbits=%08x\n",
185 eqnA, funcA, eqn, func, cbits);
186 #endif
187 new_ablend = eqnA | funcA;
188 new_cblend = eqn | func;
189
190 /* Some blend factor combinations don't seem to work when the
191 * BLEND_NO_SEPARATE bit is set.
192 *
193 * Especially problematic candidates are the ONE_MINUS_* flags,
194 * but I can't see a real pattern.
195 */
196 #if 0
197 if (new_ablend == new_cblend) {
198 new_cblend |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
199 }
200 #endif
201 new_cblend |= cbits;
202
203 if ((new_ablend != r300->hw.bld.cmd[R300_BLD_ABLEND]) ||
204 (new_cblend != r300->hw.bld.cmd[R300_BLD_CBLEND])) {
205 R300_STATECHANGE(r300, bld);
206 r300->hw.bld.cmd[R300_BLD_ABLEND] = new_ablend;
207 r300->hw.bld.cmd[R300_BLD_CBLEND] = new_cblend;
208 }
209 }
210
211 static void r300SetBlendState(GLcontext * ctx)
212 {
213 r300ContextPtr r300 = R300_CONTEXT(ctx);
214 int func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
215 (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
216 int eqn = R300_COMB_FCN_ADD_CLAMP;
217 int funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
218 (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
219 int eqnA = R300_COMB_FCN_ADD_CLAMP;
220
221 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
222 r300SetBlendCntl(r300, func, eqn, 0, func, eqn);
223 return;
224 }
225
226 func =
227 (blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE) <<
228 R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstRGB,
229 GL_FALSE) <<
230 R300_DST_BLEND_SHIFT);
231
232 switch (ctx->Color.BlendEquationRGB) {
233 case GL_FUNC_ADD:
234 eqn = R300_COMB_FCN_ADD_CLAMP;
235 break;
236
237 case GL_FUNC_SUBTRACT:
238 eqn = R300_COMB_FCN_SUB_CLAMP;
239 break;
240
241 case GL_FUNC_REVERSE_SUBTRACT:
242 eqn = R300_COMB_FCN_RSUB_CLAMP;
243 break;
244
245 case GL_MIN:
246 eqn = R300_COMB_FCN_MIN;
247 func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
248 (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
249 break;
250
251 case GL_MAX:
252 eqn = R300_COMB_FCN_MAX;
253 func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
254 (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
255 break;
256
257 default:
258 fprintf(stderr,
259 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
260 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
261 return;
262 }
263
264 funcA =
265 (blend_factor(ctx->Color.BlendSrcA, GL_TRUE) <<
266 R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstA,
267 GL_FALSE) <<
268 R300_DST_BLEND_SHIFT);
269
270 switch (ctx->Color.BlendEquationA) {
271 case GL_FUNC_ADD:
272 eqnA = R300_COMB_FCN_ADD_CLAMP;
273 break;
274
275 case GL_FUNC_SUBTRACT:
276 eqnA = R300_COMB_FCN_SUB_CLAMP;
277 break;
278
279 case GL_FUNC_REVERSE_SUBTRACT:
280 eqnA = R300_COMB_FCN_RSUB_CLAMP;
281 break;
282
283 case GL_MIN:
284 eqnA = R300_COMB_FCN_MIN;
285 funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
286 (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
287 break;
288
289 case GL_MAX:
290 eqnA = R300_COMB_FCN_MAX;
291 funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
292 (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
293 break;
294
295 default:
296 fprintf(stderr,
297 "[%s:%u] Invalid A blend equation (0x%04x).\n",
298 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
299 return;
300 }
301
302 r300SetBlendCntl(r300,
303 func, eqn,
304 (R300_SEPARATE_ALPHA_ENABLE |
305 R300_READ_ENABLE |
306 R300_ALPHA_BLEND_ENABLE), funcA, eqnA);
307 }
308
309 static void r300BlendEquationSeparate(GLcontext * ctx,
310 GLenum modeRGB, GLenum modeA)
311 {
312 r300SetBlendState(ctx);
313 }
314
315 static void r300BlendFuncSeparate(GLcontext * ctx,
316 GLenum sfactorRGB, GLenum dfactorRGB,
317 GLenum sfactorA, GLenum dfactorA)
318 {
319 r300SetBlendState(ctx);
320 }
321
322 /**
323 * Translate LogicOp enums into hardware representation.
324 * Both use a very logical bit-wise layout, but unfortunately the order
325 * of bits is reversed.
326 */
327 static GLuint translate_logicop(GLenum logicop)
328 {
329 GLuint bits = logicop - GL_CLEAR;
330 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
331 return bits << R300_RB3D_ROPCNTL_ROP_SHIFT;
332 }
333
334 /**
335 * Used internally to update the r300->hw hardware state to match the
336 * current OpenGL state.
337 */
338 static void r300SetLogicOpState(GLcontext *ctx)
339 {
340 r300ContextPtr r300 = R300_CONTEXT(ctx);
341 R300_STATECHANGE(r300, rop);
342 if (RGBA_LOGICOP_ENABLED(ctx)) {
343 r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE |
344 translate_logicop(ctx->Color.LogicOp);
345 } else {
346 r300->hw.rop.cmd[1] = 0;
347 }
348 }
349
350 /**
351 * Called by Mesa when an application program changes the LogicOp state
352 * via glLogicOp.
353 */
354 static void r300LogicOpcode(GLcontext *ctx, GLenum logicop)
355 {
356 if (RGBA_LOGICOP_ENABLED(ctx))
357 r300SetLogicOpState(ctx);
358 }
359
360 static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
361 {
362 r300ContextPtr rmesa = R300_CONTEXT(ctx);
363 GLint p;
364 GLint *ip;
365
366 /* no VAP UCP on non-TCL chipsets */
367 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
368 return;
369
370 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
371 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
372
373 R300_STATECHANGE( rmesa, vpucp[p] );
374 rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
375 rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
376 rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
377 rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
378 }
379
380 static void r300SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
381 {
382 r300ContextPtr r300 = R300_CONTEXT(ctx);
383 GLuint p;
384
385 /* no VAP UCP on non-TCL chipsets */
386 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
387 return;
388
389 p = cap - GL_CLIP_PLANE0;
390 R300_STATECHANGE(r300, vap_clip_cntl);
391 if (state) {
392 r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p);
393 r300ClipPlane(ctx, cap, NULL);
394 } else {
395 r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p);
396 }
397 }
398
399 /**
400 * Update our tracked culling state based on Mesa's state.
401 */
402 static void r300UpdateCulling(GLcontext * ctx)
403 {
404 r300ContextPtr r300 = R300_CONTEXT(ctx);
405 uint32_t val = 0;
406
407 if (ctx->Polygon.CullFlag) {
408 switch (ctx->Polygon.CullFaceMode) {
409 case GL_FRONT:
410 val = R300_CULL_FRONT;
411 break;
412 case GL_BACK:
413 val = R300_CULL_BACK;
414 break;
415 case GL_FRONT_AND_BACK:
416 val = R300_CULL_FRONT | R300_CULL_BACK;
417 break;
418 default:
419 break;
420 }
421 }
422
423 switch (ctx->Polygon.FrontFace) {
424 case GL_CW:
425 val |= R300_FRONT_FACE_CW;
426 break;
427 case GL_CCW:
428 val |= R300_FRONT_FACE_CCW;
429 break;
430 default:
431 break;
432 }
433
434 R300_STATECHANGE(r300, cul);
435 r300->hw.cul.cmd[R300_CUL_CULL] = val;
436 }
437
438 static void r300SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
439 {
440 r300ContextPtr r300 = R300_CONTEXT(ctx);
441
442 R300_STATECHANGE(r300, occlusion_cntl);
443 if (state) {
444 r300->hw.occlusion_cntl.cmd[1] |= (3 << 0);
445 } else {
446 r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
447 }
448 }
449
450 static GLboolean current_fragment_program_writes_depth(GLcontext* ctx)
451 {
452 r300ContextPtr r300 = R300_CONTEXT(ctx);
453
454 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
455 struct r300_fragment_program *fp = (struct r300_fragment_program *)
456 (char *)ctx->FragmentProgram._Current;
457 return (fp && fp->WritesDepth);
458 } else {
459 struct r500_fragment_program* fp =
460 (struct r500_fragment_program*)(char*)
461 ctx->FragmentProgram._Current;
462 return (fp && fp->writes_depth);
463 }
464 }
465
466 static void r300SetEarlyZState(GLcontext * ctx)
467 {
468 r300ContextPtr r300 = R300_CONTEXT(ctx);
469 GLuint topZ = R300_ZTOP_ENABLE;
470
471 if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
472 topZ = R300_ZTOP_DISABLE;
473 if (current_fragment_program_writes_depth(ctx))
474 topZ = R300_ZTOP_DISABLE;
475
476 if (topZ != r300->hw.zstencil_format.cmd[2]) {
477 /* Note: This completely reemits the stencil format.
478 * I have not tested whether this is strictly necessary,
479 * or if emitting a write to ZB_ZTOP is enough.
480 */
481 R300_STATECHANGE(r300, zstencil_format);
482 r300->hw.zstencil_format.cmd[2] = topZ;
483 }
484 }
485
486 static void r300SetAlphaState(GLcontext * ctx)
487 {
488 r300ContextPtr r300 = R300_CONTEXT(ctx);
489 GLubyte refByte;
490 uint32_t pp_misc = 0x0;
491 GLboolean really_enabled = ctx->Color.AlphaEnabled;
492
493 CLAMPED_FLOAT_TO_UBYTE(refByte, ctx->Color.AlphaRef);
494
495 switch (ctx->Color.AlphaFunc) {
496 case GL_NEVER:
497 pp_misc |= R300_FG_ALPHA_FUNC_NEVER;
498 break;
499 case GL_LESS:
500 pp_misc |= R300_FG_ALPHA_FUNC_LESS;
501 break;
502 case GL_EQUAL:
503 pp_misc |= R300_FG_ALPHA_FUNC_EQUAL;
504 break;
505 case GL_LEQUAL:
506 pp_misc |= R300_FG_ALPHA_FUNC_LE;
507 break;
508 case GL_GREATER:
509 pp_misc |= R300_FG_ALPHA_FUNC_GREATER;
510 break;
511 case GL_NOTEQUAL:
512 pp_misc |= R300_FG_ALPHA_FUNC_NOTEQUAL;
513 break;
514 case GL_GEQUAL:
515 pp_misc |= R300_FG_ALPHA_FUNC_GE;
516 break;
517 case GL_ALWAYS:
518 /*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */
519 really_enabled = GL_FALSE;
520 break;
521 }
522
523 if (really_enabled) {
524 pp_misc |= R300_FG_ALPHA_FUNC_ENABLE;
525 pp_misc |= R500_FG_ALPHA_FUNC_8BIT;
526 pp_misc |= (refByte & R300_FG_ALPHA_FUNC_VAL_MASK);
527 } else {
528 pp_misc = 0x0;
529 }
530
531 R300_STATECHANGE(r300, at);
532 r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc;
533 r300->hw.at.cmd[R300_AT_UNKNOWN] = 0;
534
535 r300SetEarlyZState(ctx);
536 }
537
538 static void r300AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref)
539 {
540 (void)func;
541 (void)ref;
542 r300SetAlphaState(ctx);
543 }
544
545 static int translate_func(int func)
546 {
547 switch (func) {
548 case GL_NEVER:
549 return R300_ZS_NEVER;
550 case GL_LESS:
551 return R300_ZS_LESS;
552 case GL_EQUAL:
553 return R300_ZS_EQUAL;
554 case GL_LEQUAL:
555 return R300_ZS_LEQUAL;
556 case GL_GREATER:
557 return R300_ZS_GREATER;
558 case GL_NOTEQUAL:
559 return R300_ZS_NOTEQUAL;
560 case GL_GEQUAL:
561 return R300_ZS_GEQUAL;
562 case GL_ALWAYS:
563 return R300_ZS_ALWAYS;
564 }
565 return 0;
566 }
567
568 static void r300SetDepthState(GLcontext * ctx)
569 {
570 r300ContextPtr r300 = R300_CONTEXT(ctx);
571
572 R300_STATECHANGE(r300, zs);
573 r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_STENCIL_ENABLE|R300_STENCIL_FRONT_BACK;
574 r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
575
576 if (ctx->Depth.Test) {
577 r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE;
578 if (ctx->Depth.Mask)
579 r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE;
580 r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
581 translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT;
582 }
583
584 r300SetEarlyZState(ctx);
585 }
586
587 static void r300SetStencilState(GLcontext * ctx, GLboolean state)
588 {
589 r300ContextPtr r300 = R300_CONTEXT(ctx);
590
591 if (r300->radeon.state.stencil.hwBuffer) {
592 R300_STATECHANGE(r300, zs);
593 if (state) {
594 r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
595 R300_STENCIL_ENABLE;
596 } else {
597 r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
598 ~R300_STENCIL_ENABLE;
599 }
600 } else {
601 #if R200_MERGED
602 FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state);
603 #endif
604 }
605 }
606
607 static void r300UpdatePolygonMode(GLcontext * ctx)
608 {
609 r300ContextPtr r300 = R300_CONTEXT(ctx);
610 uint32_t hw_mode = R300_GA_POLY_MODE_DISABLE;
611
612 /* Only do something if a polygon mode is wanted, default is GL_FILL */
613 if (ctx->Polygon.FrontMode != GL_FILL ||
614 ctx->Polygon.BackMode != GL_FILL) {
615 GLenum f, b;
616
617 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
618 * correctly by selecting the correct front and back face
619 */
620 if (ctx->Polygon.FrontFace == GL_CCW) {
621 f = ctx->Polygon.FrontMode;
622 b = ctx->Polygon.BackMode;
623 } else {
624 f = ctx->Polygon.BackMode;
625 b = ctx->Polygon.FrontMode;
626 }
627
628 /* Enable polygon mode */
629 hw_mode |= R300_GA_POLY_MODE_DUAL;
630
631 switch (f) {
632 case GL_LINE:
633 hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_LINE;
634 break;
635 case GL_POINT:
636 hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_POINT;
637 break;
638 case GL_FILL:
639 hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_TRI;
640 break;
641 }
642
643 switch (b) {
644 case GL_LINE:
645 hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_LINE;
646 break;
647 case GL_POINT:
648 hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_POINT;
649 break;
650 case GL_FILL:
651 hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_TRI;
652 break;
653 }
654 }
655
656 if (r300->hw.polygon_mode.cmd[1] != hw_mode) {
657 R300_STATECHANGE(r300, polygon_mode);
658 r300->hw.polygon_mode.cmd[1] = hw_mode;
659 }
660
661 r300->hw.polygon_mode.cmd[2] = 0x00000001;
662 r300->hw.polygon_mode.cmd[3] = 0x00000000;
663 }
664
665 /**
666 * Change the culling mode.
667 *
668 * \note Mesa already filters redundant calls to this function.
669 */
670 static void r300CullFace(GLcontext * ctx, GLenum mode)
671 {
672 (void)mode;
673
674 r300UpdateCulling(ctx);
675 }
676
677 /**
678 * Change the polygon orientation.
679 *
680 * \note Mesa already filters redundant calls to this function.
681 */
682 static void r300FrontFace(GLcontext * ctx, GLenum mode)
683 {
684 (void)mode;
685
686 r300UpdateCulling(ctx);
687 r300UpdatePolygonMode(ctx);
688 }
689
690 /**
691 * Change the depth testing function.
692 *
693 * \note Mesa already filters redundant calls to this function.
694 */
695 static void r300DepthFunc(GLcontext * ctx, GLenum func)
696 {
697 (void)func;
698 r300SetDepthState(ctx);
699 }
700
701 /**
702 * Enable/Disable depth writing.
703 *
704 * \note Mesa already filters redundant calls to this function.
705 */
706 static void r300DepthMask(GLcontext * ctx, GLboolean mask)
707 {
708 (void)mask;
709 r300SetDepthState(ctx);
710 }
711
712 /**
713 * Handle glColorMask()
714 */
715 static void r300ColorMask(GLcontext * ctx,
716 GLboolean r, GLboolean g, GLboolean b, GLboolean a)
717 {
718 r300ContextPtr r300 = R300_CONTEXT(ctx);
719 int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
720 (g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
721 (b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
722 (a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0);
723
724 if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
725 R300_STATECHANGE(r300, cmk);
726 r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask;
727 }
728 }
729
730 /* =============================================================
731 * Point state
732 */
733 static void r300PointSize(GLcontext * ctx, GLfloat size)
734 {
735 r300ContextPtr r300 = R300_CONTEXT(ctx);
736 /* same size limits for AA, non-AA points */
737 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
738
739 R300_STATECHANGE(r300, ps);
740 r300->hw.ps.cmd[R300_PS_POINTSIZE] =
741 ((int)(size * 6) << R300_POINTSIZE_X_SHIFT) |
742 ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT);
743 }
744
745 static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param)
746 {
747 r300ContextPtr r300 = R300_CONTEXT(ctx);
748
749 switch (pname) {
750 case GL_POINT_SIZE_MIN:
751 R300_STATECHANGE(r300, ga_point_minmax);
752 r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK;
753 r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
754 break;
755 case GL_POINT_SIZE_MAX:
756 R300_STATECHANGE(r300, ga_point_minmax);
757 r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK;
758 r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
759 << R300_GA_POINT_MINMAX_MAX_SHIFT;
760 break;
761 case GL_POINT_DISTANCE_ATTENUATION:
762 break;
763 case GL_POINT_FADE_THRESHOLD_SIZE:
764 break;
765 default:
766 break;
767 }
768 }
769
770 /* =============================================================
771 * Line state
772 */
773 static void r300LineWidth(GLcontext * ctx, GLfloat widthf)
774 {
775 r300ContextPtr r300 = R300_CONTEXT(ctx);
776
777 widthf = CLAMP(widthf,
778 ctx->Const.MinPointSize,
779 ctx->Const.MaxPointSize);
780 R300_STATECHANGE(r300, lcntl);
781 r300->hw.lcntl.cmd[1] =
782 R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0);
783 }
784
785 static void r300PolygonMode(GLcontext * ctx, GLenum face, GLenum mode)
786 {
787 (void)face;
788 (void)mode;
789
790 r300UpdatePolygonMode(ctx);
791 }
792
793 /* =============================================================
794 * Stencil
795 */
796
797 static int translate_stencil_op(int op)
798 {
799 switch (op) {
800 case GL_KEEP:
801 return R300_ZS_KEEP;
802 case GL_ZERO:
803 return R300_ZS_ZERO;
804 case GL_REPLACE:
805 return R300_ZS_REPLACE;
806 case GL_INCR:
807 return R300_ZS_INCR;
808 case GL_DECR:
809 return R300_ZS_DECR;
810 case GL_INCR_WRAP_EXT:
811 return R300_ZS_INCR_WRAP;
812 case GL_DECR_WRAP_EXT:
813 return R300_ZS_DECR_WRAP;
814 case GL_INVERT:
815 return R300_ZS_INVERT;
816 default:
817 WARN_ONCE("Do not know how to translate stencil op");
818 return R300_ZS_KEEP;
819 }
820 return 0;
821 }
822
823 static void r300ShadeModel(GLcontext * ctx, GLenum mode)
824 {
825 r300ContextPtr rmesa = R300_CONTEXT(ctx);
826
827 R300_STATECHANGE(rmesa, shade);
828 rmesa->hw.shade.cmd[1] = 0x00000002;
829 switch (mode) {
830 case GL_FLAT:
831 rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_FLAT;
832 break;
833 case GL_SMOOTH:
834 rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH;
835 break;
836 default:
837 return;
838 }
839 rmesa->hw.shade.cmd[3] = 0x00000000;
840 rmesa->hw.shade.cmd[4] = 0x00000000;
841 }
842
843 static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
844 GLenum func, GLint ref, GLuint mask)
845 {
846 r300ContextPtr rmesa = R300_CONTEXT(ctx);
847 GLuint refmask =
848 ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT)
849 | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT);
850 const unsigned back = ctx->Stencil._BackFace;
851 GLuint flag;
852
853 R300_STATECHANGE(rmesa, zs);
854 rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK;
855 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK <<
856 R300_S_FRONT_FUNC_SHIFT)
857 | (R300_ZS_MASK <<
858 R300_S_BACK_FUNC_SHIFT));
859
860 rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
861 ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
862 (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
863
864 flag = translate_func(ctx->Stencil.Function[0]);
865 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
866 (flag << R300_S_FRONT_FUNC_SHIFT);
867
868 flag = translate_func(ctx->Stencil.Function[back]);
869
870 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
871 (flag << R300_S_BACK_FUNC_SHIFT);
872 rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask;
873 }
874
875 static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
876 {
877 r300ContextPtr rmesa = R300_CONTEXT(ctx);
878
879 R300_STATECHANGE(rmesa, zs);
880 rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
881 ~(R300_STENCILREF_MASK <<
882 R300_STENCILWRITEMASK_SHIFT);
883 rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
884 (ctx->Stencil.
885 WriteMask[0] & R300_STENCILREF_MASK) <<
886 R300_STENCILWRITEMASK_SHIFT;
887 }
888
889 static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
890 GLenum fail, GLenum zfail, GLenum zpass)
891 {
892 r300ContextPtr rmesa = R300_CONTEXT(ctx);
893 const unsigned back = ctx->Stencil._BackFace;
894
895 R300_STATECHANGE(rmesa, zs);
896 /* It is easier to mask what's left.. */
897 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &=
898 (R300_ZS_MASK << R300_Z_FUNC_SHIFT) |
899 (R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) |
900 (R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT);
901
902 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
903 (translate_stencil_op(ctx->Stencil.FailFunc[0]) <<
904 R300_S_FRONT_SFAIL_OP_SHIFT)
905 | (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) <<
906 R300_S_FRONT_ZFAIL_OP_SHIFT)
907 | (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) <<
908 R300_S_FRONT_ZPASS_OP_SHIFT);
909
910 rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
911 (translate_stencil_op(ctx->Stencil.FailFunc[back]) <<
912 R300_S_BACK_SFAIL_OP_SHIFT)
913 | (translate_stencil_op(ctx->Stencil.ZFailFunc[back]) <<
914 R300_S_BACK_ZFAIL_OP_SHIFT)
915 | (translate_stencil_op(ctx->Stencil.ZPassFunc[back]) <<
916 R300_S_BACK_ZPASS_OP_SHIFT);
917 }
918
919 /* =============================================================
920 * Window position and viewport transformation
921 */
922
923 /*
924 * To correctly position primitives:
925 */
926 #define SUBPIXEL_X 0.125
927 #define SUBPIXEL_Y 0.125
928
929 static void r300UpdateWindow(GLcontext * ctx)
930 {
931 r300ContextPtr rmesa = R300_CONTEXT(ctx);
932 __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
933 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
934 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
935 const GLfloat *v = ctx->Viewport._WindowMap.m;
936 const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0);
937 GLfloat y_scale, y_bias;
938
939 if (render_to_fbo) {
940 y_scale = 1.0;
941 y_bias = 0;
942 } else {
943 y_scale = -1.0;
944 y_bias = yoffset;
945 }
946
947 GLfloat sx = v[MAT_SX];
948 GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
949 GLfloat sy = v[MAT_SY] * y_scale;
950 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y;
951 GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale;
952 GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale;
953
954 R300_STATECHANGE(rmesa, vpt);
955
956 rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
957 rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
958 rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy);
959 rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
960 rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz);
961 rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz);
962 }
963
964 static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
965 GLsizei width, GLsizei height)
966 {
967 /* Don't pipeline viewport changes, conflict with window offset
968 * setting below. Could apply deltas to rescue pipelined viewport
969 * values, or keep the originals hanging around.
970 */
971 r300UpdateWindow(ctx);
972
973 radeon_viewport(ctx, x, y, width, height);
974 }
975
976 static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
977 {
978 r300UpdateWindow(ctx);
979 }
980
981 void r300UpdateViewportOffset(GLcontext * ctx)
982 {
983 r300ContextPtr rmesa = R300_CONTEXT(ctx);
984 __DRIdrawablePrivate *dPriv = ((radeonContextPtr) rmesa)->dri.drawable;
985 GLfloat xoffset = (GLfloat) dPriv->x;
986 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
987 const GLfloat *v = ctx->Viewport._WindowMap.m;
988
989 GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
990 GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
991
992 if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) ||
993 rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) {
994 /* Note: this should also modify whatever data the context reset
995 * code uses...
996 */
997 R300_STATECHANGE(rmesa, vpt);
998 rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
999 rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
1000
1001 }
1002
1003 radeonUpdateScissor(ctx);
1004 }
1005
1006 static void
1007 r300FetchStateParameter(GLcontext * ctx,
1008 const gl_state_index state[STATE_LENGTH],
1009 GLfloat * value)
1010 {
1011 r300ContextPtr r300 = R300_CONTEXT(ctx);
1012
1013 switch (state[0]) {
1014 case STATE_INTERNAL:
1015 switch (state[1]) {
1016 case STATE_R300_WINDOW_DIMENSION:
1017 value[0] = r300->radeon.dri.drawable->w * 0.5f; /* width*0.5 */
1018 value[1] = r300->radeon.dri.drawable->h * 0.5f; /* height*0.5 */
1019 value[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */
1020 value[3] = 1.0F; /* not used */
1021 break;
1022
1023 case STATE_R300_TEXRECT_FACTOR:{
1024 struct gl_texture_object *t =
1025 ctx->Texture.Unit[state[2]].CurrentTex[TEXTURE_RECT_INDEX];
1026
1027 if (t && t->Image[0][t->BaseLevel]) {
1028 struct gl_texture_image *image =
1029 t->Image[0][t->BaseLevel];
1030 value[0] = 1.0 / image->Width2;
1031 value[1] = 1.0 / image->Height2;
1032 } else {
1033 value[0] = 1.0;
1034 value[1] = 1.0;
1035 }
1036 value[2] = 1.0;
1037 value[3] = 1.0;
1038 break;
1039 }
1040
1041 default:
1042 break;
1043 }
1044 break;
1045
1046 default:
1047 break;
1048 }
1049 }
1050
1051 /**
1052 * Update R300's own internal state parameters.
1053 * For now just STATE_R300_WINDOW_DIMENSION
1054 */
1055 void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state)
1056 {
1057 struct r300_fragment_program *fp;
1058 struct gl_program_parameter_list *paramList;
1059 GLuint i;
1060
1061 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
1062 return;
1063
1064 fp = (struct r300_fragment_program *)ctx->FragmentProgram._Current;
1065 if (!fp)
1066 return;
1067
1068 paramList = fp->mesa_program.Base.Parameters;
1069
1070 if (!paramList)
1071 return;
1072
1073 for (i = 0; i < paramList->NumParameters; i++) {
1074 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR) {
1075 r300FetchStateParameter(ctx,
1076 paramList->Parameters[i].
1077 StateIndexes,
1078 paramList->ParameterValues[i]);
1079 }
1080 }
1081 }
1082
1083 /* =============================================================
1084 * Polygon state
1085 */
1086 static void r300PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units)
1087 {
1088 r300ContextPtr rmesa = R300_CONTEXT(ctx);
1089 GLfloat constant = units;
1090
1091 switch (ctx->Visual.depthBits) {
1092 case 16:
1093 constant *= 4.0;
1094 break;
1095 case 24:
1096 constant *= 2.0;
1097 break;
1098 }
1099
1100 factor *= 12.0;
1101
1102 /* fprintf(stderr, "%s f:%f u:%f\n", __FUNCTION__, factor, constant); */
1103
1104 R300_STATECHANGE(rmesa, zbs);
1105 rmesa->hw.zbs.cmd[R300_ZBS_T_FACTOR] = r300PackFloat32(factor);
1106 rmesa->hw.zbs.cmd[R300_ZBS_T_CONSTANT] = r300PackFloat32(constant);
1107 rmesa->hw.zbs.cmd[R300_ZBS_W_FACTOR] = r300PackFloat32(factor);
1108 rmesa->hw.zbs.cmd[R300_ZBS_W_CONSTANT] = r300PackFloat32(constant);
1109 }
1110
1111 /* Routing and texture-related */
1112
1113 /* r300 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST.
1114 * Since texwrap produces same results for GL_CLAMP and GL_CLAMP_TO_EDGE we use them instead.
1115 * We need to recalculate wrap modes whenever filter mode is changed because someone might do:
1116 * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
1117 * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP);
1118 * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
1119 * Since r300 completely ignores R300_TX_CLAMP when either min or mag is nearest it cant handle
1120 * combinations where only one of them is nearest.
1121 */
1122 static unsigned long gen_fixed_filter(unsigned long f)
1123 {
1124 unsigned long mag, min, needs_fixing = 0;
1125 //return f;
1126
1127 /* We ignore MIRROR bit so we dont have to do everything twice */
1128 if ((f & ((7 - 1) << R300_TX_WRAP_S_SHIFT)) ==
1129 (R300_TX_CLAMP << R300_TX_WRAP_S_SHIFT)) {
1130 needs_fixing |= 1;
1131 }
1132 if ((f & ((7 - 1) << R300_TX_WRAP_T_SHIFT)) ==
1133 (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) {
1134 needs_fixing |= 2;
1135 }
1136 if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) ==
1137 (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) {
1138 needs_fixing |= 4;
1139 }
1140
1141 if (!needs_fixing)
1142 return f;
1143
1144 mag = f & R300_TX_MAG_FILTER_MASK;
1145 min = f & (R300_TX_MIN_FILTER_MASK|R300_TX_MIN_FILTER_MIP_MASK);
1146
1147 /* TODO: Check for anisto filters too */
1148 if ((mag != R300_TX_MAG_FILTER_NEAREST)
1149 && (min != R300_TX_MIN_FILTER_NEAREST))
1150 return f;
1151
1152 /* r300 cant handle these modes hence we force nearest to linear */
1153 if ((mag == R300_TX_MAG_FILTER_NEAREST)
1154 && (min != R300_TX_MIN_FILTER_NEAREST)) {
1155 f &= ~R300_TX_MAG_FILTER_NEAREST;
1156 f |= R300_TX_MAG_FILTER_LINEAR;
1157 return f;
1158 }
1159
1160 if ((min == R300_TX_MIN_FILTER_NEAREST)
1161 && (mag != R300_TX_MAG_FILTER_NEAREST)) {
1162 f &= ~R300_TX_MIN_FILTER_NEAREST;
1163 f |= R300_TX_MIN_FILTER_LINEAR;
1164 return f;
1165 }
1166
1167 /* Both are nearest */
1168 if (needs_fixing & 1) {
1169 f &= ~((7 - 1) << R300_TX_WRAP_S_SHIFT);
1170 f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT;
1171 }
1172 if (needs_fixing & 2) {
1173 f &= ~((7 - 1) << R300_TX_WRAP_T_SHIFT);
1174 f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT;
1175 }
1176 if (needs_fixing & 4) {
1177 f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT);
1178 f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT;
1179 }
1180 return f;
1181 }
1182
1183 static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
1184 {
1185 r300ContextPtr r300 = R300_CONTEXT(ctx);
1186 int i;
1187 struct r300_fragment_program *fp = (struct r300_fragment_program *)
1188 (char *)ctx->FragmentProgram._Current;
1189 struct r300_fragment_program_code *code = &fp->code;
1190
1191 R300_STATECHANGE(r300, fpt);
1192
1193 for (i = 0; i < code->tex.length; i++) {
1194 int unit;
1195 int opcode;
1196 unsigned long val;
1197
1198 unit = code->tex.inst[i] >> R300_TEX_ID_SHIFT;
1199 unit &= 15;
1200
1201 val = code->tex.inst[i];
1202 val &= ~R300_TEX_ID_MASK;
1203
1204 opcode =
1205 (val & R300_TEX_INST_MASK) >> R300_TEX_INST_SHIFT;
1206 if (opcode == R300_TEX_OP_KIL) {
1207 r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
1208 } else {
1209 if (tmu_mappings[unit] >= 0) {
1210 val |=
1211 tmu_mappings[unit] <<
1212 R300_TEX_ID_SHIFT;
1213 r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
1214 } else {
1215 // We get here when the corresponding texture image is incomplete
1216 // (e.g. incomplete mipmaps etc.)
1217 r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
1218 }
1219 }
1220 }
1221
1222 r300->hw.fpt.cmd[R300_FPT_CMD_0] =
1223 cmdpacket0(r300->radeon.radeonScreen,
1224 R300_US_TEX_INST_0, code->tex.length);
1225 }
1226
1227 static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
1228 {
1229 int i;
1230 struct r500_fragment_program *fp = (struct r500_fragment_program *)
1231 (char *)ctx->FragmentProgram._Current;
1232 struct r500_fragment_program_code *code = &fp->code;
1233
1234 /* find all the texture instructions and relocate the texture units */
1235 for (i = 0; i < code->inst_end + 1; i++) {
1236 if ((code->inst[i].inst0 & 0x3) == R500_INST_TYPE_TEX) {
1237 uint32_t val;
1238 int unit, opcode, new_unit;
1239
1240 val = code->inst[i].inst1;
1241
1242 unit = (val >> 16) & 0xf;
1243
1244 val &= ~(0xf << 16);
1245
1246 opcode = val & (0x7 << 22);
1247 if (opcode == R500_TEX_INST_TEXKILL) {
1248 new_unit = 0;
1249 } else {
1250 if (tmu_mappings[unit] >= 0) {
1251 new_unit = tmu_mappings[unit];
1252 } else {
1253 new_unit = 0;
1254 }
1255 }
1256 val |= R500_TEX_ID(new_unit);
1257 code->inst[i].inst1 = val;
1258 }
1259 }
1260 }
1261
1262 static GLuint translate_lod_bias(GLfloat bias)
1263 {
1264 GLint b = (int)(bias*32);
1265 if (b >= (1 << 9))
1266 b = (1 << 9)-1;
1267 else if (b < -(1 << 9))
1268 b = -(1 << 9);
1269 return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1270 }
1271
1272 static void r300SetupTextures(GLcontext * ctx)
1273 {
1274 int i, mtu;
1275 struct radeon_tex_obj *t;
1276 r300ContextPtr r300 = R300_CONTEXT(ctx);
1277 int hw_tmu = 0;
1278 int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */
1279 int tmu_mappings[R300_MAX_TEXTURE_UNITS] = { -1, };
1280 struct r300_fragment_program *fp = (struct r300_fragment_program *)
1281 (char *)ctx->FragmentProgram._Current;
1282
1283 R300_STATECHANGE(r300, txe);
1284 R300_STATECHANGE(r300, tex.filter);
1285 R300_STATECHANGE(r300, tex.filter_1);
1286 R300_STATECHANGE(r300, tex.size);
1287 R300_STATECHANGE(r300, tex.format);
1288 R300_STATECHANGE(r300, tex.pitch);
1289 R300_STATECHANGE(r300, tex.offset);
1290 R300_STATECHANGE(r300, tex.chroma_key);
1291 R300_STATECHANGE(r300, tex.border_color);
1292
1293 r300->hw.txe.cmd[R300_TXE_ENABLE] = 0x0;
1294
1295 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
1296 if (RADEON_DEBUG & DEBUG_STATE)
1297 fprintf(stderr, "mtu=%d\n", mtu);
1298
1299 if (mtu > R300_MAX_TEXTURE_UNITS) {
1300 fprintf(stderr,
1301 "Aiiee ! mtu=%d is greater than R300_MAX_TEXTURE_UNITS=%d\n",
1302 mtu, R300_MAX_TEXTURE_UNITS);
1303 _mesa_exit(-1);
1304 }
1305
1306 /* We cannot let disabled tmu offsets pass DRM */
1307 for (i = 0; i < mtu; i++) {
1308 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1309 tmu_mappings[i] = hw_tmu;
1310
1311 t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
1312 if (!t)
1313 continue;
1314
1315 if ((t->pp_txformat & 0xffffff00) == 0xffffff00) {
1316 WARN_ONCE
1317 ("unknown texture format (entry %x) encountered. Help me !\n",
1318 t->pp_txformat & 0xff);
1319 }
1320
1321 if (RADEON_DEBUG & DEBUG_STATE)
1322 fprintf(stderr,
1323 "Activating texture unit %d\n", i);
1324
1325 r300->hw.txe.cmd[R300_TXE_ENABLE] |= (1 << hw_tmu);
1326
1327 r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 +
1328 hw_tmu] =
1329 gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28);
1330 /* Note: There is a LOD bias per texture unit and a LOD bias
1331 * per texture object. We add them here to get the correct behaviour.
1332 * (The per-texture object LOD bias was introduced in OpenGL 1.4
1333 * and is not present in the EXT_texture_object extension).
1334 */
1335 r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] =
1336 t->pp_txfilter_1 |
1337 translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias);
1338 r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] =
1339 t->pp_txsize;
1340 r300->hw.tex.format.cmd[R300_TEX_VALUE_0 +
1341 hw_tmu] = t->pp_txformat;
1342 r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] =
1343 t->pp_txpitch;
1344 r300->hw.textures[hw_tmu] = t;
1345
1346 if (t->tile_bits & R300_TXO_MACRO_TILE) {
1347 WARN_ONCE("macro tiling enabled!\n");
1348 }
1349
1350 if (t->tile_bits & R300_TXO_MICRO_TILE) {
1351 WARN_ONCE("micro tiling enabled!\n");
1352 }
1353
1354 r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 +
1355 hw_tmu] = 0x0;
1356 r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 +
1357 hw_tmu] =
1358 t->pp_border_color;
1359
1360 last_hw_tmu = hw_tmu;
1361
1362 hw_tmu++;
1363 }
1364 }
1365
1366 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
1367 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1);
1368 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
1369 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1);
1370 r300->hw.tex.size.cmd[R300_TEX_CMD_0] =
1371 cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1);
1372 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
1373 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1);
1374 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] =
1375 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1);
1376 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
1377 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1);
1378 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
1379 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
1380 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
1381 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
1382
1383 if (!fp) /* should only happenen once, just after context is created */
1384 return;
1385
1386 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
1387 if (fp->mesa_program.UsesKill && last_hw_tmu < 0) {
1388 // The KILL operation requires the first texture unit
1389 // to be enabled.
1390 r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
1391 r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
1392 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
1393 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1);
1394 }
1395 r300SetupFragmentShaderTextures(ctx, tmu_mappings);
1396 } else
1397 r500SetupFragmentShaderTextures(ctx, tmu_mappings);
1398
1399 if (RADEON_DEBUG & DEBUG_STATE)
1400 fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
1401 r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
1402 }
1403
1404 union r300_outputs_written {
1405 GLuint vp_outputs; /* hw_tcl_on */
1406 DECLARE_RENDERINPUTS(index_bitset); /* !hw_tcl_on */
1407 };
1408
1409 #define R300_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \
1410 ((hw_tcl_on) ? (ow).vp_outputs & (1 << (vp_result)) : \
1411 RENDERINPUTS_TEST( (ow.index_bitset), (tnl_attrib) ))
1412
1413 static void r300SetupRSUnit(GLcontext * ctx)
1414 {
1415 r300ContextPtr r300 = R300_CONTEXT(ctx);
1416 TNLcontext *tnl = TNL_CONTEXT(ctx);
1417 struct vertex_buffer *VB = &tnl->vb;
1418 union r300_outputs_written OutputsWritten;
1419 GLuint InputsRead;
1420 int fp_reg, high_rr;
1421 int col_ip, tex_ip;
1422 int rs_tex_count = 0;
1423 int i, count, col_fmt;
1424
1425 if (hw_tcl_on)
1426 OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
1427 else
1428 RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
1429
1430 if (ctx->FragmentProgram._Current)
1431 InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
1432 else {
1433 fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
1434 return; /* This should only ever happen once.. */
1435 }
1436
1437 R300_STATECHANGE(r300, ri);
1438 R300_STATECHANGE(r300, rc);
1439 R300_STATECHANGE(r300, rr);
1440
1441 fp_reg = col_ip = tex_ip = col_fmt = 0;
1442
1443 r300->hw.rc.cmd[1] = 0;
1444 r300->hw.rc.cmd[2] = 0;
1445 for (i=0; i<R300_RR_CMDSIZE-1; ++i)
1446 r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
1447
1448 for (i=0; i<R300_RI_CMDSIZE-1; ++i)
1449 r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
1450
1451
1452 if (InputsRead & FRAG_BIT_COL0) {
1453 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
1454 count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
1455 if (count == 4)
1456 col_fmt = R300_RS_COL_FMT_RGBA;
1457 else if (count == 3)
1458 col_fmt = R300_RS_COL_FMT_RGB1;
1459 else
1460 col_fmt = R300_RS_COL_FMT_0001;
1461
1462 r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt);
1463 r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
1464 InputsRead &= ~FRAG_BIT_COL0;
1465 ++col_ip;
1466 ++fp_reg;
1467 } else {
1468 WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
1469 }
1470 }
1471
1472 if (InputsRead & FRAG_BIT_COL1) {
1473 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
1474 count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
1475 if (count == 4)
1476 col_fmt = R300_RS_COL_FMT_RGBA;
1477 else if (count == 3)
1478 col_fmt = R300_RS_COL_FMT_RGB1;
1479 else
1480 col_fmt = R300_RS_COL_FMT_0001;
1481
1482 r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt);
1483 r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
1484 InputsRead &= ~FRAG_BIT_COL1;
1485 ++col_ip;
1486 ++fp_reg;
1487 } else {
1488 WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
1489 }
1490 }
1491
1492 for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
1493 if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
1494 continue;
1495
1496 if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
1497 WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
1498 continue;
1499 }
1500
1501 int swiz;
1502
1503 /* with TCL we always seem to route 4 components */
1504 if (hw_tcl_on)
1505 count = 4;
1506 else
1507 count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
1508
1509 switch(count) {
1510 case 4: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break;
1511 case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
1512 default:
1513 case 1:
1514 case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
1515 };
1516
1517 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz | R300_RS_TEX_PTR(rs_tex_count);
1518 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
1519 InputsRead &= ~(FRAG_BIT_TEX0 << i);
1520 rs_tex_count += count;
1521 ++tex_ip;
1522 ++fp_reg;
1523 }
1524
1525 if (InputsRead & FRAG_BIT_FOGC) {
1526 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
1527 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count);
1528 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
1529 InputsRead &= ~FRAG_BIT_FOGC;
1530 rs_tex_count += 4;
1531 ++tex_ip;
1532 ++fp_reg;
1533 } else {
1534 WARN_ONCE("fragprog wants fogc, vp doesn't provide it\n");
1535 }
1536 }
1537
1538 if (InputsRead & FRAG_BIT_WPOS) {
1539 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count);
1540 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
1541 InputsRead &= ~FRAG_BIT_WPOS;
1542 rs_tex_count += 4;
1543 ++tex_ip;
1544 ++fp_reg;
1545 }
1546 InputsRead &= ~FRAG_BIT_WPOS;
1547
1548 /* Setup default color if no color or tex was set */
1549 if (rs_tex_count == 0 && col_ip == 0) {
1550 r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
1551 ++col_ip;
1552 }
1553
1554 high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
1555 r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
1556 r300->hw.rc.cmd[2] |= high_rr - 1;
1557
1558 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr);
1559
1560 if (InputsRead)
1561 WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
1562 }
1563
1564 static void r500SetupRSUnit(GLcontext * ctx)
1565 {
1566 r300ContextPtr r300 = R300_CONTEXT(ctx);
1567 TNLcontext *tnl = TNL_CONTEXT(ctx);
1568 struct vertex_buffer *VB = &tnl->vb;
1569 union r300_outputs_written OutputsWritten;
1570 GLuint InputsRead;
1571 int fp_reg, high_rr;
1572 int col_ip, tex_ip;
1573 int rs_tex_count = 0;
1574 int i, count, col_fmt;
1575
1576 if (hw_tcl_on)
1577 OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
1578 else
1579 RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
1580
1581 if (ctx->FragmentProgram._Current)
1582 InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
1583 else {
1584 fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
1585 return; /* This should only ever happen once.. */
1586 }
1587
1588 R300_STATECHANGE(r300, ri);
1589 R300_STATECHANGE(r300, rc);
1590 R300_STATECHANGE(r300, rr);
1591
1592 fp_reg = col_ip = tex_ip = col_fmt = 0;
1593
1594 r300->hw.rc.cmd[1] = 0;
1595 r300->hw.rc.cmd[2] = 0;
1596 for (i=0; i<R300_RR_CMDSIZE-1; ++i)
1597 r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
1598
1599 for (i=0; i<R500_RI_CMDSIZE-1; ++i)
1600 r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
1601
1602
1603 if (InputsRead & FRAG_BIT_COL0) {
1604 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
1605 count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
1606 if (count == 4)
1607 col_fmt = R300_RS_COL_FMT_RGBA;
1608 else if (count == 3)
1609 col_fmt = R300_RS_COL_FMT_RGB1;
1610 else
1611 col_fmt = R300_RS_COL_FMT_0001;
1612
1613 r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
1614 r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
1615 InputsRead &= ~FRAG_BIT_COL0;
1616 ++col_ip;
1617 ++fp_reg;
1618 } else {
1619 WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
1620 }
1621 }
1622
1623 if (InputsRead & FRAG_BIT_COL1) {
1624 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
1625 count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
1626 if (count == 4)
1627 col_fmt = R300_RS_COL_FMT_RGBA;
1628 else if (count == 3)
1629 col_fmt = R300_RS_COL_FMT_RGB1;
1630 else
1631 col_fmt = R300_RS_COL_FMT_0001;
1632
1633 r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
1634 r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
1635 InputsRead &= ~FRAG_BIT_COL1;
1636 ++col_ip;
1637 ++fp_reg;
1638 } else {
1639 WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
1640 }
1641 }
1642
1643
1644 for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
1645 if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
1646 continue;
1647
1648 if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
1649 WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
1650 continue;
1651 }
1652
1653 int swiz = 0;
1654
1655 /* with TCL we always seem to route 4 components */
1656 if (hw_tcl_on)
1657 count = 4;
1658 else
1659 count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
1660
1661 if (count == 4) {
1662 swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
1663 swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
1664 swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT;
1665 swiz |= (rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT;
1666 } else if (count == 3) {
1667 swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
1668 swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
1669 swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT;
1670 swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
1671 } else if (count == 2) {
1672 swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
1673 swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
1674 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
1675 swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
1676 } else if (count == 1) {
1677 swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
1678 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT;
1679 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
1680 swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
1681 } else {
1682 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT;
1683 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT;
1684 swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
1685 swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
1686 }
1687
1688 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz;
1689 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
1690 InputsRead &= ~(FRAG_BIT_TEX0 << i);
1691 rs_tex_count += count;
1692 ++tex_ip;
1693 ++fp_reg;
1694 }
1695
1696 if (InputsRead & FRAG_BIT_FOGC) {
1697 if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
1698 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
1699 ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
1700 ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
1701 ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
1702
1703 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
1704 InputsRead &= ~FRAG_BIT_FOGC;
1705 rs_tex_count += 4;
1706 ++tex_ip;
1707 ++fp_reg;
1708 } else {
1709 WARN_ONCE("fragprog wants fogc, vp doesn't provide it\n");
1710 }
1711 }
1712
1713 if (InputsRead & FRAG_BIT_WPOS) {
1714 r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
1715 ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
1716 ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
1717 ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
1718
1719 r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
1720 InputsRead &= ~FRAG_BIT_WPOS;
1721 rs_tex_count += 4;
1722 ++tex_ip;
1723 ++fp_reg;
1724 }
1725
1726 /* Setup default color if no color or tex was set */
1727 if (rs_tex_count == 0 && col_ip == 0) {
1728 r300->hw.rr.cmd[R300_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001);
1729 ++col_ip;
1730 }
1731
1732 high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
1733 r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
1734 r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1);
1735
1736 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr);
1737
1738 if (InputsRead)
1739 WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
1740 }
1741
1742
1743
1744
1745 #define bump_vpu_count(ptr, new_count) do{\
1746 drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
1747 int _nc=(new_count)/4; \
1748 assert(_nc < 256); \
1749 if(_nc>_p->vpu.count)_p->vpu.count=_nc;\
1750 }while(0)
1751
1752 static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, struct r300_vertex_shader_fragment *vsf)
1753 {
1754 int i;
1755
1756 if (vsf->length == 0)
1757 return;
1758
1759 if (vsf->length & 0x3) {
1760 fprintf(stderr, "VERTEX_SHADER_FRAGMENT must have length divisible by 4\n");
1761 _mesa_exit(-1);
1762 }
1763
1764 switch ((dest >> 8) & 0xf) {
1765 case 0:
1766 R300_STATECHANGE(r300, vpi);
1767 for (i = 0; i < vsf->length; i++)
1768 r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
1769 bump_vpu_count(r300->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff));
1770 break;
1771
1772 case 2:
1773 R300_STATECHANGE(r300, vpp);
1774 for (i = 0; i < vsf->length; i++)
1775 r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
1776 bump_vpu_count(r300->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff));
1777 break;
1778 case 4:
1779 R300_STATECHANGE(r300, vps);
1780 for (i = 0; i < vsf->length; i++)
1781 r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
1782 bump_vpu_count(r300->hw.vps.cmd, vsf->length + 4 * (dest & 0xff));
1783 break;
1784 default:
1785 fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest);
1786 _mesa_exit(-1);
1787 }
1788 }
1789
1790 #define MIN3(a, b, c) ((a) < (b) ? MIN2(a, c) : MIN2(b, c))
1791
1792
1793 static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count,
1794 GLuint output_count, GLuint temp_count)
1795 {
1796 int vtx_mem_size;
1797 int pvs_num_slots;
1798 int pvs_num_cntrls;
1799
1800 /* Flush PVS engine before changing PVS_NUM_SLOTS, PVS_NUM_CNTRLS.
1801 * See r500 docs 6.5.2 - done in emit */
1802
1803 /* avoid division by zero */
1804 if (input_count == 0) input_count = 1;
1805 if (output_count == 0) output_count = 1;
1806 if (temp_count == 0) temp_count = 1;
1807
1808 if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
1809 vtx_mem_size = 128;
1810 else
1811 vtx_mem_size = 72;
1812
1813 pvs_num_slots = MIN3(10, vtx_mem_size/input_count, vtx_mem_size/output_count);
1814 pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count);
1815
1816 R300_STATECHANGE(rmesa, vap_cntl);
1817 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
1818 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] =
1819 (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) |
1820 (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) |
1821 (12 << R300_VF_MAX_VTX_NUM_SHIFT);
1822 if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
1823 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION;
1824 } else
1825 /* not sure about non-tcl */
1826 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
1827 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
1828 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
1829
1830 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
1831 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
1832 else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
1833 (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
1834 (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
1835 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
1836 else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
1837 (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
1838 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
1839 else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
1840 (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
1841 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
1842 else
1843 rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
1844
1845 }
1846
1847 static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
1848 {
1849 struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader);
1850 GLuint o_reg = 0;
1851 GLuint i_reg = 0;
1852 int i;
1853 int inst_count = 0;
1854 int param_count = 0;
1855 int program_end = 0;
1856
1857 for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) {
1858 if (rmesa->state.sw_tcl_inputs[i] != -1) {
1859 prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT);
1860 prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
1861 prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
1862 prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
1863 program_end += 4;
1864 i_reg++;
1865 }
1866 }
1867
1868 prog->program.length = program_end;
1869
1870 r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START,
1871 &(prog->program));
1872 inst_count = (prog->program.length / 4) - 1;
1873
1874 r300VapCntl(rmesa, i_reg, o_reg, 0);
1875
1876 R300_STATECHANGE(rmesa, pvs);
1877 rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] =
1878 (0 << R300_PVS_FIRST_INST_SHIFT) |
1879 (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
1880 (inst_count << R300_PVS_LAST_INST_SHIFT);
1881 rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] =
1882 (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
1883 (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT);
1884 rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] =
1885 (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
1886 }
1887
1888 static int bit_count (int x)
1889 {
1890 x = ((x & 0xaaaaaaaaU) >> 1) + (x & 0x55555555U);
1891 x = ((x & 0xccccccccU) >> 2) + (x & 0x33333333U);
1892 x = (x >> 16) + (x & 0xffff);
1893 x = ((x & 0xf0f0) >> 4) + (x & 0x0f0f);
1894 return (x >> 8) + (x & 0x00ff);
1895 }
1896
1897 static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
1898 {
1899 GLcontext *ctx = rmesa->radeon.glCtx;
1900 struct r300_vertex_program *prog = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
1901 int inst_count = 0;
1902 int param_count = 0;
1903
1904 /* FIXME: r300SetupVertexProgramFragment */
1905 R300_STATECHANGE(rmesa, vpp);
1906 param_count =
1907 r300VertexProgUpdateParams(ctx,
1908 (struct r300_vertex_program_cont *)
1909 ctx->VertexProgram._Current,
1910 (float *)&rmesa->hw.vpp.
1911 cmd[R300_VPP_PARAM_0]);
1912 bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
1913 param_count /= 4;
1914
1915 r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program));
1916 inst_count = (prog->program.length / 4) - 1;
1917
1918 r300VapCntl(rmesa, bit_count(prog->key.InputsRead),
1919 bit_count(prog->key.OutputsWritten), prog->num_temporaries);
1920
1921 R300_STATECHANGE(rmesa, pvs);
1922 rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] =
1923 (0 << R300_PVS_FIRST_INST_SHIFT) |
1924 (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
1925 (inst_count << R300_PVS_LAST_INST_SHIFT);
1926 rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] =
1927 (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
1928 (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT);
1929 rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] =
1930 (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
1931 }
1932
1933
1934 static void r300SetupVertexProgram(r300ContextPtr rmesa)
1935 {
1936 GLcontext *ctx = rmesa->radeon.glCtx;
1937
1938 /* Reset state, in case we don't use something */
1939 ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0;
1940 ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0;
1941 ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0;
1942
1943 /* Not sure why this doesnt work...
1944 0x400 area might have something to do with pixel shaders as it appears right after pfs programming.
1945 0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */
1946 //setup_vertex_shader_fragment(rmesa, 0x406, &unk4);
1947 if (hw_tcl_on && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) {
1948 r300SetupRealVertexProgram(rmesa);
1949 } else {
1950 /* FIXME: This needs to be replaced by vertex shader generation code. */
1951 r300SetupDefaultVertexProgram(rmesa);
1952 }
1953
1954 }
1955
1956 /**
1957 * Enable/Disable states.
1958 *
1959 * \note Mesa already filters redundant calls to this function.
1960 */
1961 static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
1962 {
1963 r300ContextPtr rmesa = R300_CONTEXT(ctx);
1964 if (RADEON_DEBUG & DEBUG_STATE)
1965 fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
1966 _mesa_lookup_enum_by_nr(cap),
1967 state ? "GL_TRUE" : "GL_FALSE");
1968
1969 switch (cap) {
1970 case GL_TEXTURE_1D:
1971 case GL_TEXTURE_2D:
1972 case GL_TEXTURE_3D:
1973 /* empty */
1974 break;
1975 case GL_FOG:
1976 /* empty */
1977 break;
1978 case GL_ALPHA_TEST:
1979 r300SetAlphaState(ctx);
1980 break;
1981 case GL_COLOR_LOGIC_OP:
1982 r300SetLogicOpState(ctx);
1983 /* fall-through, because logic op overrides blending */
1984 case GL_BLEND:
1985 r300SetBlendState(ctx);
1986 break;
1987 case GL_CLIP_PLANE0:
1988 case GL_CLIP_PLANE1:
1989 case GL_CLIP_PLANE2:
1990 case GL_CLIP_PLANE3:
1991 case GL_CLIP_PLANE4:
1992 case GL_CLIP_PLANE5:
1993 r300SetClipPlaneState(ctx, cap, state);
1994 break;
1995 case GL_DEPTH_TEST:
1996 r300SetDepthState(ctx);
1997 break;
1998 case GL_STENCIL_TEST:
1999 r300SetStencilState(ctx, state);
2000 break;
2001 case GL_CULL_FACE:
2002 r300UpdateCulling(ctx);
2003 break;
2004 case GL_POLYGON_OFFSET_POINT:
2005 case GL_POLYGON_OFFSET_LINE:
2006 case GL_POLYGON_OFFSET_FILL:
2007 r300SetPolygonOffsetState(ctx, state);
2008 break;
2009 case GL_SCISSOR_TEST:
2010 radeon_firevertices(&rmesa->radeon);
2011 rmesa->radeon.state.scissor.enabled = state;
2012 radeonUpdateScissor( ctx );
2013 break;
2014 default:
2015 break;
2016 }
2017 }
2018
2019 /**
2020 * Completely recalculates hardware state based on the Mesa state.
2021 */
2022 static void r300ResetHwState(r300ContextPtr r300)
2023 {
2024 GLcontext *ctx = r300->radeon.glCtx;
2025 struct radeon_renderbuffer *rrb;
2026 int has_tcl = 1;
2027
2028 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
2029 has_tcl = 0;
2030
2031 if (RADEON_DEBUG & DEBUG_STATE)
2032 fprintf(stderr, "%s\n", __FUNCTION__);
2033
2034 radeon_firevertices(&r300->radeon);
2035 r300UpdateWindow(ctx);
2036
2037 r300ColorMask(ctx,
2038 ctx->Color.ColorMask[RCOMP],
2039 ctx->Color.ColorMask[GCOMP],
2040 ctx->Color.ColorMask[BCOMP], ctx->Color.ColorMask[ACOMP]);
2041
2042 r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
2043 r300DepthMask(ctx, ctx->Depth.Mask);
2044 r300DepthFunc(ctx, ctx->Depth.Func);
2045
2046 /* stencil */
2047 r300Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
2048 r300StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
2049 r300StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
2050 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
2051 r300StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
2052 ctx->Stencil.ZFailFunc[0],
2053 ctx->Stencil.ZPassFunc[0]);
2054
2055 r300UpdateCulling(ctx);
2056
2057 r300SetBlendState(ctx);
2058 r300SetLogicOpState(ctx);
2059
2060 r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
2061 r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
2062
2063 r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
2064 | R300_VPORT_X_OFFSET_ENA
2065 | R300_VPORT_Y_SCALE_ENA
2066 | R300_VPORT_Y_OFFSET_ENA
2067 | R300_VPORT_Z_SCALE_ENA
2068 | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT;
2069 r300->hw.vte.cmd[2] = 0x00000008;
2070
2071 r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
2072 r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
2073
2074 #ifdef MESA_LITTLE_ENDIAN
2075 r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP;
2076 #else
2077 r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP;
2078 #endif
2079
2080 /* disable VAP/TCL on non-TCL capable chips */
2081 if (!has_tcl)
2082 r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
2083
2084 r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
2085
2086 /* XXX: Other families? */
2087 if (has_tcl) {
2088 r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
2089
2090 r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
2091 r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
2092 r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */
2093 r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */
2094
2095 switch (r300->radeon.radeonScreen->chip_family) {
2096 case CHIP_FAMILY_R300:
2097 r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300;
2098 break;
2099 default:
2100 r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350;
2101 break;
2102 }
2103 }
2104
2105 r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE
2106 | R300_GB_LINE_STUFF_ENABLE
2107 | R300_GB_TRIANGLE_STUFF_ENABLE;
2108
2109 r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
2110 r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
2111
2112 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
2113 R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
2114 switch (r300->radeon.radeonScreen->num_gb_pipes) {
2115 case 1:
2116 default:
2117 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
2118 R300_GB_TILE_PIPE_COUNT_RV300;
2119 break;
2120 case 2:
2121 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
2122 R300_GB_TILE_PIPE_COUNT_R300;
2123 break;
2124 case 3:
2125 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
2126 R300_GB_TILE_PIPE_COUNT_R420_3P;
2127 break;
2128 case 4:
2129 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
2130 R300_GB_TILE_PIPE_COUNT_R420;
2131 break;
2132 }
2133
2134 /* XXX: Enable anti-aliasing? */
2135 r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE;
2136 r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = 0;
2137
2138 r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0);
2139 r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0);
2140 r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0);
2141 r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0);
2142
2143 r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
2144
2145 r300PointSize(ctx, 1.0);
2146
2147 r300->hw.ga_point_minmax.cmd[1] = 0x18000006;
2148 r300->hw.ga_point_minmax.cmd[2] = 0x00020006;
2149 r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0);
2150
2151 r300LineWidth(ctx, 1.0);
2152
2153 r300->hw.ga_line_stipple.cmd[1] = 0;
2154 r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0);
2155 r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0);
2156
2157 r300ShadeModel(ctx, ctx->Light.ShadeModel);
2158
2159 r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
2160 r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
2161 r300->hw.zbias_cntl.cmd[1] = 0x00000000;
2162
2163 r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
2164 ctx->Polygon.OffsetUnits);
2165 r300Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
2166 r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
2167 r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
2168
2169 r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
2170 r300->hw.su_depth_scale.cmd[2] = 0x00000000;
2171
2172 r300->hw.sc_hyperz.cmd[1] = 0x0000001C;
2173 r300->hw.sc_hyperz.cmd[2] = 0x2DA49525;
2174
2175 r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
2176
2177 r300->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 |
2178 R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
2179 r300->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED |
2180 R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
2181 r300->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED |
2182 R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
2183 r300->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED |
2184 R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
2185 r300->hw.us_out_fmt.cmd[5] = R300_W_FMT_W0 | R300_W_SRC_US;
2186
2187 /* disable fog unit */
2188 r300->hw.fogs.cmd[R300_FOGS_STATE] = 0;
2189 r300->hw.fg_depth_src.cmd[1] = R300_FG_DEPTH_SRC_SCAN;
2190
2191 r300->hw.rb3d_cctl.cmd[1] = 0;
2192
2193 r300BlendColor(ctx, ctx->Color.BlendColor);
2194
2195 r300->hw.rb3d_dither_ctl.cmd[1] = 0;
2196 r300->hw.rb3d_dither_ctl.cmd[2] = 0;
2197 r300->hw.rb3d_dither_ctl.cmd[3] = 0;
2198 r300->hw.rb3d_dither_ctl.cmd[4] = 0;
2199 r300->hw.rb3d_dither_ctl.cmd[5] = 0;
2200 r300->hw.rb3d_dither_ctl.cmd[6] = 0;
2201 r300->hw.rb3d_dither_ctl.cmd[7] = 0;
2202 r300->hw.rb3d_dither_ctl.cmd[8] = 0;
2203 r300->hw.rb3d_dither_ctl.cmd[9] = 0;
2204
2205 r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
2206
2207 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
2208 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
2209
2210 rrb = r300->radeon.state.depth.rrb;
2211 if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) {
2212 /* XXX: Turn off when clearing buffers ? */
2213 r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE;
2214
2215 if (ctx->Visual.depthBits == 24)
2216 r300->hw.zb.cmd[R300_ZB_PITCH] |=
2217 R300_DEPTHMICROTILE_TILED;
2218 }
2219
2220 r300->hw.zb_depthclearvalue.cmd[1] = 0;
2221
2222 r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
2223 r300->hw.zstencil_format.cmd[3] = 0x00000003;
2224 r300->hw.zstencil_format.cmd[4] = 0x00000000;
2225 r300SetEarlyZState(ctx);
2226
2227 r300->hw.unk4F30.cmd[1] = 0;
2228 r300->hw.unk4F30.cmd[2] = 0;
2229
2230 r300->hw.zb_hiz_offset.cmd[1] = 0;
2231
2232 r300->hw.zb_hiz_pitch.cmd[1] = 0;
2233
2234 r300VapCntl(r300, 0, 0, 0);
2235 if (has_tcl) {
2236 r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
2237 r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
2238 r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
2239 r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
2240 }
2241
2242 r300->radeon.hw.all_dirty = GL_TRUE;
2243 }
2244
2245 void r300UpdateShaders(r300ContextPtr rmesa)
2246 {
2247 GLcontext *ctx;
2248 struct r300_vertex_program *vp;
2249 int i;
2250
2251 ctx = rmesa->radeon.glCtx;
2252
2253 if (rmesa->radeon.NewGLState && hw_tcl_on) {
2254 rmesa->radeon.NewGLState = 0;
2255
2256 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
2257 rmesa->temp_attrib[i] =
2258 TNL_CONTEXT(ctx)->vb.AttribPtr[i];
2259 TNL_CONTEXT(ctx)->vb.AttribPtr[i] =
2260 &rmesa->dummy_attrib[i];
2261 }
2262
2263 _tnl_UpdateFixedFunctionProgram(ctx);
2264
2265 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
2266 TNL_CONTEXT(ctx)->vb.AttribPtr[i] =
2267 rmesa->temp_attrib[i];
2268 }
2269
2270 r300SelectVertexShader(rmesa);
2271 vp = (struct r300_vertex_program *)
2272 CURRENT_VERTEX_SHADER(ctx);
2273 /*if (vp->translated == GL_FALSE)
2274 r300TranslateVertexShader(vp); */
2275 if (vp->translated == GL_FALSE) {
2276 fprintf(stderr, "Failing back to sw-tcl\n");
2277 hw_tcl_on = future_hw_tcl_on = 0;
2278 r300ResetHwState(rmesa);
2279
2280 r300UpdateStateParameters(ctx, _NEW_PROGRAM);
2281 return;
2282 }
2283 }
2284 r300UpdateStateParameters(ctx, _NEW_PROGRAM);
2285 }
2286
2287 static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx,
2288 struct gl_program *program, struct prog_src_register srcreg)
2289 {
2290 static const GLfloat dummy[4] = { 0, 0, 0, 0 };
2291
2292 switch(srcreg.File) {
2293 case PROGRAM_LOCAL_PARAM:
2294 return program->LocalParams[srcreg.Index];
2295 case PROGRAM_ENV_PARAM:
2296 return ctx->FragmentProgram.Parameters[srcreg.Index];
2297 case PROGRAM_STATE_VAR:
2298 case PROGRAM_NAMED_PARAM:
2299 case PROGRAM_CONSTANT:
2300 return program->Parameters->ParameterValues[srcreg.Index];
2301 default:
2302 _mesa_problem(ctx, "get_fragmentprogram_constant: Unknown\n");
2303 return dummy;
2304 }
2305 }
2306
2307
2308 static void r300SetupPixelShader(r300ContextPtr rmesa)
2309 {
2310 GLcontext *ctx = rmesa->radeon.glCtx;
2311 struct r300_fragment_program *fp = (struct r300_fragment_program *)
2312 (char *)ctx->FragmentProgram._Current;
2313 struct r300_fragment_program_code *code;
2314 int i, k;
2315
2316 if (!fp) /* should only happenen once, just after context is created */
2317 return;
2318
2319 r300TranslateFragmentShader(rmesa, fp);
2320 if (!fp->translated) {
2321 fprintf(stderr, "%s: No valid fragment shader, exiting\n",
2322 __FUNCTION__);
2323 return;
2324 }
2325 code = &fp->code;
2326
2327 r300SetupTextures(ctx);
2328
2329 R300_STATECHANGE(rmesa, fpi[0]);
2330 R300_STATECHANGE(rmesa, fpi[1]);
2331 R300_STATECHANGE(rmesa, fpi[2]);
2332 R300_STATECHANGE(rmesa, fpi[3]);
2333 rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length);
2334 rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length);
2335 rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length);
2336 rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
2337 for (i = 0; i < code->alu.length; i++) {
2338 rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0;
2339 rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1;
2340 rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst2;
2341 rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst3;
2342 }
2343
2344 R300_STATECHANGE(rmesa, fp);
2345 rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3);
2346 rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->max_temp_idx;
2347 rmesa->hw.fp.cmd[R300_FP_CNTL2] =
2348 (0 << R300_PFS_CNTL_ALU_OFFSET_SHIFT) |
2349 ((code->alu.length-1) << R300_PFS_CNTL_ALU_END_SHIFT) |
2350 (0 << R300_PFS_CNTL_TEX_OFFSET_SHIFT) |
2351 ((code->tex.length ? code->tex.length-1 : 0) << R300_PFS_CNTL_TEX_END_SHIFT);
2352 /* I just want to say, the way these nodes are stored.. weird.. */
2353 for (i = 0, k = (4 - (code->cur_node + 1)); i < 4; i++, k++) {
2354 if (i < (code->cur_node + 1)) {
2355 rmesa->hw.fp.cmd[R300_FP_NODE0 + k] =
2356 (code->node[i].alu_offset << R300_ALU_START_SHIFT) |
2357 (code->node[i].alu_end << R300_ALU_SIZE_SHIFT) |
2358 (code->node[i].tex_offset << R300_TEX_START_SHIFT) |
2359 (code->node[i].tex_end << R300_TEX_SIZE_SHIFT) |
2360 code->node[i].flags;
2361 } else {
2362 rmesa->hw.fp.cmd[R300_FP_NODE0 + (3 - i)] = 0;
2363 }
2364 }
2365
2366 R300_STATECHANGE(rmesa, fpp);
2367 rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4);
2368 for (i = 0; i < code->const_nr; i++) {
2369 const GLfloat *constant = get_fragmentprogram_constant(ctx,
2370 &fp->mesa_program.Base, code->constant[i]);
2371 rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]);
2372 rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]);
2373 rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]);
2374 rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]);
2375 }
2376 }
2377
2378 #define bump_r500fp_count(ptr, new_count) do{\
2379 drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
2380 int _nc=(new_count)/6; \
2381 assert(_nc < 256); \
2382 if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
2383 } while(0)
2384
2385 #define bump_r500fp_const_count(ptr, new_count) do{\
2386 drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
2387 int _nc=(new_count)/4; \
2388 assert(_nc < 256); \
2389 if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
2390 } while(0)
2391
2392 static void r500SetupPixelShader(r300ContextPtr rmesa)
2393 {
2394 GLcontext *ctx = rmesa->radeon.glCtx;
2395 struct r500_fragment_program *fp = (struct r500_fragment_program *)
2396 (char *)ctx->FragmentProgram._Current;
2397 int i;
2398 struct r500_fragment_program_code *code;
2399
2400 if (!fp) /* should only happenen once, just after context is created */
2401 return;
2402
2403 ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0;
2404 ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0;
2405
2406 r500TranslateFragmentShader(rmesa, fp);
2407 if (!fp->translated) {
2408 fprintf(stderr, "%s: No valid fragment shader, exiting\n",
2409 __FUNCTION__);
2410 return;
2411 }
2412 code = &fp->code;
2413
2414 r300SetupTextures(ctx);
2415
2416 R300_STATECHANGE(rmesa, fp);
2417 rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx;
2418
2419 rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] =
2420 R500_US_CODE_START_ADDR(code->inst_offset) |
2421 R500_US_CODE_END_ADDR(code->inst_end);
2422 rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] =
2423 R500_US_CODE_RANGE_ADDR(code->inst_offset) |
2424 R500_US_CODE_RANGE_SIZE(code->inst_end);
2425 rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] =
2426 R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */
2427
2428 R300_STATECHANGE(rmesa, r500fp);
2429 /* Emit our shader... */
2430 for (i = 0; i < code->inst_end+1; i++) {
2431 rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0;
2432 rmesa->hw.r500fp.cmd[i*6+2] = code->inst[i].inst1;
2433 rmesa->hw.r500fp.cmd[i*6+3] = code->inst[i].inst2;
2434 rmesa->hw.r500fp.cmd[i*6+4] = code->inst[i].inst3;
2435 rmesa->hw.r500fp.cmd[i*6+5] = code->inst[i].inst4;
2436 rmesa->hw.r500fp.cmd[i*6+6] = code->inst[i].inst5;
2437 }
2438
2439 bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6);
2440
2441 R300_STATECHANGE(rmesa, r500fp_const);
2442 for (i = 0; i < code->const_nr; i++) {
2443 const GLfloat *constant = get_fragmentprogram_constant(ctx,
2444 &fp->mesa_program.Base, code->constant[i]);
2445 rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]);
2446 rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]);
2447 rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]);
2448 rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]);
2449 }
2450 bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4);
2451
2452 }
2453
2454 void r300UpdateShaderStates(r300ContextPtr rmesa)
2455 {
2456 GLcontext *ctx;
2457 ctx = rmesa->radeon.glCtx;
2458
2459 r300SetEarlyZState(ctx);
2460
2461 /* w_fmt value is set to get best performance
2462 * see p.130 R5xx 3D acceleration guide v1.3 */
2463 GLuint w_fmt, fgdepthsrc;
2464 if (current_fragment_program_writes_depth(ctx)) {
2465 fgdepthsrc = R300_FG_DEPTH_SRC_SHADER;
2466 w_fmt = R300_W_FMT_W24 | R300_W_SRC_US;
2467 } else {
2468 fgdepthsrc = R300_FG_DEPTH_SRC_SCAN;
2469 w_fmt = R300_W_FMT_W0 | R300_W_SRC_US;
2470 }
2471
2472 if (w_fmt != rmesa->hw.us_out_fmt.cmd[5]) {
2473 R300_STATECHANGE(rmesa, us_out_fmt);
2474 rmesa->hw.us_out_fmt.cmd[5] = w_fmt;
2475 }
2476
2477 if (fgdepthsrc != rmesa->hw.fg_depth_src.cmd[1]) {
2478 R300_STATECHANGE(rmesa, fg_depth_src);
2479 rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc;
2480 }
2481
2482 if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
2483 r500SetupPixelShader(rmesa);
2484 else
2485 r300SetupPixelShader(rmesa);
2486
2487 if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
2488 r500SetupRSUnit(ctx);
2489 else
2490 r300SetupRSUnit(ctx);
2491
2492 if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
2493 r300SetupVertexProgram(rmesa);
2494
2495 }
2496
2497 /**
2498 * Called by Mesa after an internal state update.
2499 */
2500 static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
2501 {
2502 r300ContextPtr r300 = R300_CONTEXT(ctx);
2503
2504 _swrast_InvalidateState(ctx, new_state);
2505 _swsetup_InvalidateState(ctx, new_state);
2506 _vbo_InvalidateState(ctx, new_state);
2507 _tnl_InvalidateState(ctx, new_state);
2508 _ae_invalidate_state(ctx, new_state);
2509
2510 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
2511 _mesa_update_framebuffer(ctx);
2512 /* this updates the DrawBuffer's Width/Height if it's a FBO */
2513 _mesa_update_draw_buffer_bounds(ctx);
2514
2515 R300_STATECHANGE(r300, cb);
2516 }
2517
2518 r300UpdateStateParameters(ctx, new_state);
2519
2520 r300->radeon.NewGLState |= new_state;
2521 }
2522
2523 /**
2524 * Calculate initial hardware state and register state functions.
2525 * Assumes that the command buffer and state atoms have been
2526 * initialized already.
2527 */
2528 void r300InitState(r300ContextPtr r300)
2529 {
2530 GLcontext *ctx = r300->radeon.glCtx;
2531 GLuint depth_fmt;
2532
2533 /* Only have hw stencil when depth buffer is 24 bits deep */
2534 r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 &&
2535 ctx->Visual.depthBits == 24);
2536
2537 memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
2538
2539 r300ResetHwState(r300);
2540 }
2541
2542 static void r300RenderMode(GLcontext * ctx, GLenum mode)
2543 {
2544 r300ContextPtr rmesa = R300_CONTEXT(ctx);
2545 (void)rmesa;
2546 (void)mode;
2547 }
2548
2549 void r300UpdateClipPlanes( GLcontext *ctx )
2550 {
2551 r300ContextPtr rmesa = R300_CONTEXT(ctx);
2552 GLuint p;
2553
2554 for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
2555 if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
2556 GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
2557
2558 R300_STATECHANGE( rmesa, vpucp[p] );
2559 rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
2560 rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
2561 rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
2562 rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
2563 }
2564 }
2565 }
2566
2567 /**
2568 * Initialize driver's state callback functions
2569 */
2570 void r300InitStateFuncs(struct dd_function_table *functions)
2571 {
2572
2573 functions->UpdateState = r300InvalidateState;
2574 functions->AlphaFunc = r300AlphaFunc;
2575 functions->BlendColor = r300BlendColor;
2576 functions->BlendEquationSeparate = r300BlendEquationSeparate;
2577 functions->BlendFuncSeparate = r300BlendFuncSeparate;
2578 functions->Enable = r300Enable;
2579 functions->ColorMask = r300ColorMask;
2580 functions->DepthFunc = r300DepthFunc;
2581 functions->DepthMask = r300DepthMask;
2582 functions->CullFace = r300CullFace;
2583 functions->FrontFace = r300FrontFace;
2584 functions->ShadeModel = r300ShadeModel;
2585 functions->LogicOpcode = r300LogicOpcode;
2586
2587 /* ARB_point_parameters */
2588 functions->PointParameterfv = r300PointParameter;
2589
2590 /* Stencil related */
2591 functions->StencilFuncSeparate = r300StencilFuncSeparate;
2592 functions->StencilMaskSeparate = r300StencilMaskSeparate;
2593 functions->StencilOpSeparate = r300StencilOpSeparate;
2594
2595 /* Viewport related */
2596 functions->Viewport = r300Viewport;
2597 functions->DepthRange = r300DepthRange;
2598 functions->PointSize = r300PointSize;
2599 functions->LineWidth = r300LineWidth;
2600
2601 functions->PolygonOffset = r300PolygonOffset;
2602 functions->PolygonMode = r300PolygonMode;
2603
2604 functions->RenderMode = r300RenderMode;
2605
2606 functions->ClipPlane = r300ClipPlane;
2607 functions->Scissor = radeonScissor;
2608
2609 functions->DrawBuffer = radeonDrawBuffer;
2610 functions->ReadBuffer = radeonReadBuffer;
2611 }