Port texture allocation code from R200.
[mesa.git] / src / mesa / drivers / dri / r300 / r300_state.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /*
33 * Authors:
34 * Nicolai Haehnle <prefect_@gmx.net>
35 */
36
37 #include "glheader.h"
38 #include "state.h"
39 #include "imports.h"
40 #include "enums.h"
41 #include "macros.h"
42 #include "context.h"
43 #include "dd.h"
44 #include "simple_list.h"
45
46 #include "api_arrayelt.h"
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
49 #include "array_cache/acache.h"
50 #include "tnl/tnl.h"
51
52 #include "radeon_ioctl.h"
53 #include "radeon_state.h"
54 #include "r300_context.h"
55 #include "r300_ioctl.h"
56 #include "r300_state.h"
57 #include "r300_reg.h"
58 #include "r300_program.h"
59
60
61 /**
62 * Update our tracked culling state based on Mesa's state.
63 */
64 static void r300UpdateCulling(GLcontext* ctx)
65 {
66 r300ContextPtr r300 = R300_CONTEXT(ctx);
67 uint32_t val = 0;
68
69 R300_STATECHANGE(r300, cul);
70 if (ctx->Polygon.CullFlag) {
71 if (ctx->Polygon.CullFaceMode == GL_FRONT_AND_BACK)
72 val = R300_CULL_FRONT|R300_CULL_BACK;
73 else if (ctx->Polygon.CullFaceMode == GL_FRONT)
74 val = R300_CULL_FRONT;
75 else
76 val = R300_CULL_BACK;
77
78 if (ctx->Polygon.FrontFace == GL_CW)
79 val |= R300_FRONT_FACE_CW;
80 else
81 val |= R300_FRONT_FACE_CCW;
82 }
83
84 r300->hw.cul.cmd[R300_CUL_CULL] = val;
85 }
86
87
88 /**
89 * Handle glEnable()/glDisable().
90 *
91 * \note Mesa already filters redundant calls to glEnable/glDisable.
92 */
93 static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state)
94 {
95 r300ContextPtr r300 = R300_CONTEXT(ctx);
96 uint32_t newval;
97
98 if (RADEON_DEBUG & DEBUG_STATE)
99 fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
100 _mesa_lookup_enum_by_nr(cap),
101 state ? "GL_TRUE" : "GL_FALSE");
102
103 switch (cap) {
104 case GL_DEPTH_TEST:
105 R300_STATECHANGE(r300, zc);
106
107 if (state) {
108 if (ctx->Depth.Mask)
109 newval = R300_RB3D_Z_TEST_AND_WRITE;
110 else
111 newval = R300_RB3D_Z_TEST;
112 } else
113 newval = 0;
114
115 r300->hw.zc.cmd[R300_ZC_CNTL_0] = newval;
116 break;
117
118 case GL_CULL_FACE:
119 r300UpdateCulling(ctx);
120 break;
121
122 default:
123 radeonEnable(ctx, cap, state);
124 return;
125 }
126 }
127
128
129 /**
130 * Change the culling mode.
131 *
132 * \note Mesa already filters redundant calls to this function.
133 */
134 static void r300CullFace(GLcontext* ctx, GLenum mode)
135 {
136 (void)mode;
137
138 r300UpdateCulling(ctx);
139 }
140
141
142 /**
143 * Change the polygon orientation.
144 *
145 * \note Mesa already filters redundant calls to this function.
146 */
147 static void r300FrontFace(GLcontext* ctx, GLenum mode)
148 {
149 (void)mode;
150
151 r300UpdateCulling(ctx);
152 }
153
154
155 /**
156 * Change the depth testing function.
157 *
158 * \note Mesa already filters redundant calls to this function.
159 */
160 static void r300DepthFunc(GLcontext* ctx, GLenum func)
161 {
162 r300ContextPtr r300 = R300_CONTEXT(ctx);
163
164 R300_STATECHANGE(r300, zc);
165
166 switch(func) {
167 case GL_NEVER:
168 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_NEVER;
169 break;
170 case GL_LESS:
171 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_LESS;
172 break;
173 case GL_EQUAL:
174 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_EQUAL;
175 break;
176 case GL_LEQUAL:
177 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_LEQUAL;
178 break;
179 case GL_GREATER:
180 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_GREATER;
181 break;
182 case GL_NOTEQUAL:
183 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_NEQUAL;
184 break;
185 case GL_GEQUAL:
186 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_GEQUAL;
187 break;
188 case GL_ALWAYS:
189 r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_ALWAYS;
190 break;
191 }
192 }
193
194
195 /**
196 * Enable/Disable depth writing.
197 *
198 * \note Mesa already filters redundant calls to this function.
199 */
200 static void r300DepthMask(GLcontext* ctx, GLboolean mask)
201 {
202 r300ContextPtr r300 = R300_CONTEXT(ctx);
203
204 if (!ctx->Depth.Test)
205 return;
206
207 R300_STATECHANGE(r300, zc);
208 r300->hw.zc.cmd[R300_ZC_CNTL_0] = mask
209 ? R300_RB3D_Z_TEST_AND_WRITE : R300_RB3D_Z_TEST;
210 }
211
212
213 /**
214 * Handle glColorMask()
215 */
216 static void r300ColorMask(GLcontext* ctx,
217 GLboolean r, GLboolean g, GLboolean b, GLboolean a)
218 {
219 r300ContextPtr r300 = R300_CONTEXT(ctx);
220 int mask = (b << 0) | (g << 1) | (r << 2) | (a << 3);
221
222 if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
223 R300_STATECHANGE(r300, cmk);
224 r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask;
225 }
226 }
227
228 /* =============================================================
229 * Window position and viewport transformation
230 */
231
232 /*
233 * To correctly position primitives:
234 */
235 #define SUBPIXEL_X 0.125
236 #define SUBPIXEL_Y 0.125
237
238 void r300UpdateWindow(GLcontext * ctx)
239 {
240 r300ContextPtr rmesa = R300_CONTEXT(ctx);
241 __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
242 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
243 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
244 const GLfloat *v = ctx->Viewport._WindowMap.m;
245
246 GLfloat sx = v[MAT_SX];
247 GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
248 GLfloat sy = -v[MAT_SY];
249 GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
250 GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale;
251 GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale;
252
253 R300_FIREVERTICES(rmesa);
254 R300_STATECHANGE(rmesa, vpt);
255
256 rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
257 rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
258 rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy);
259 rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
260 rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz);
261 rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz);
262 }
263
264 static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
265 GLsizei width, GLsizei height)
266 {
267 /* Don't pipeline viewport changes, conflict with window offset
268 * setting below. Could apply deltas to rescue pipelined viewport
269 * values, or keep the originals hanging around.
270 */
271 R200_FIREVERTICES(R200_CONTEXT(ctx));
272 r300UpdateWindow(ctx);
273 }
274
275 static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
276 {
277 r300UpdateWindow(ctx);
278 }
279
280
281 /**
282 * Called by Mesa after an internal state update.
283 */
284 static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
285 {
286 r300ContextPtr r300 = R300_CONTEXT(ctx);
287
288 _swrast_InvalidateState(ctx, new_state);
289 _swsetup_InvalidateState(ctx, new_state);
290 _ac_InvalidateState(ctx, new_state);
291 _tnl_InvalidateState(ctx, new_state);
292 _ae_invalidate_state(ctx, new_state);
293
294 /* Go inefficiency! */
295 r300ResetHwState(r300);
296 }
297
298
299 /**
300 * Completely recalculates hardware state based on the Mesa state.
301 */
302 void r300ResetHwState(r300ContextPtr r300)
303 {
304 GLcontext* ctx = r300->radeon.glCtx;
305 int i;
306
307 if (RADEON_DEBUG & DEBUG_STATE)
308 fprintf(stderr, "%s\n", __FUNCTION__);
309
310 r300UpdateWindow(ctx);
311
312 r300ColorMask(ctx,
313 ctx->Color.ColorMask[RCOMP],
314 ctx->Color.ColorMask[GCOMP],
315 ctx->Color.ColorMask[BCOMP],
316 ctx->Color.ColorMask[ACOMP]);
317
318 r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
319 r300DepthMask(ctx, ctx->Depth.Mask);
320 r300DepthFunc(ctx, ctx->Depth.Func);
321
322 r300UpdateCulling(ctx);
323
324 //BEGIN: TODO
325 r300->hw.unk2080.cmd[1] = 0x0030045A;
326
327 r300->hw.ovf.cmd[R300_OVF_FMT_0] = 0x00000003;
328 r300->hw.ovf.cmd[R300_OVF_FMT_1] = 0x00000000;
329
330 r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
331 | R300_VPORT_X_OFFSET_ENA
332 | R300_VPORT_Y_SCALE_ENA
333 | R300_VPORT_Y_OFFSET_ENA
334 | R300_VPORT_Z_SCALE_ENA
335 | R300_VPORT_Z_OFFSET_ENA
336 | R300_VTX_W0_FMT;
337 r300->hw.vte.cmd[2] = 0x00000008;
338
339 r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
340 r300->hw.unk2134.cmd[2] = 0x00000000;
341
342 r300->hw.unk2140.cmd[1] = 0x00000000;
343
344 ((drm_r300_cmd_header_t*)r300->hw.vir[0].cmd)->unchecked_state.count = 1;
345 r300->hw.vir[0].cmd[1] = 0x21030003;
346
347 ((drm_r300_cmd_header_t*)r300->hw.vir[1].cmd)->unchecked_state.count = 1;
348 r300->hw.vir[1].cmd[1] = 0xF688F688;
349
350 r300->hw.vic.cmd[R300_VIR_CNTL_0] = 0x00000001;
351 r300->hw.vic.cmd[R300_VIR_CNTL_1] = 0x00000405;
352
353 r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
354
355 r300->hw.unk221C.cmd[1] = R300_221C_NORMAL;
356
357 r300->hw.unk2220.cmd[1] = r300PackFloat32(1.0);
358 r300->hw.unk2220.cmd[2] = r300PackFloat32(1.0);
359 r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
360 r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
361
362 if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
363 r300->hw.unk2288.cmd[1] = R300_2288_R300;
364 else
365 r300->hw.unk2288.cmd[1] = R300_2288_RV350;
366
367 r300->hw.vof.cmd[R300_VOF_CNTL_0] = R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
368 | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT;
369 r300->hw.vof.cmd[R300_VOF_CNTL_1] = 0; /* no textures */
370
371 r300->hw.pvs.cmd[R300_PVS_CNTL_1] = 0;
372 r300->hw.pvs.cmd[R300_PVS_CNTL_2] = 0;
373 r300->hw.pvs.cmd[R300_PVS_CNTL_3] = 0;
374
375 r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE
376 | R300_GB_LINE_STUFF_ENABLE
377 | R300_GB_TRIANGLE_STUFF_ENABLE;
378
379 r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
380 r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
381 if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
382 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
383 | R300_GB_TILE_PIPE_COUNT_R300
384 | R300_GB_TILE_SIZE_16;
385 else
386 r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
387 | R300_GB_TILE_PIPE_COUNT_RV300
388 | R300_GB_TILE_SIZE_16;
389 r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = 0x00000000;
390 r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = 0x00000000; /* No antialiasing */
391
392 r300->hw.txe.cmd[R300_TXE_ENABLE] = 0;
393
394 r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
395 r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
396 r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
397 r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
398
399 r300->hw.unk4214.cmd[1] = 0x00050005;
400
401 r300->hw.ps.cmd[R300_PS_POINTSIZE] = (6 << R300_POINTSIZE_X_SHIFT) |
402 (6 << R300_POINTSIZE_Y_SHIFT);
403
404 r300->hw.unk4230.cmd[1] = 0x01800000;
405 r300->hw.unk4230.cmd[2] = 0x00020006;
406 r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
407
408 r300->hw.unk4260.cmd[1] = 0;
409 r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
410 r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
411
412 r300->hw.unk4274.cmd[1] = 0x00000002;
413 r300->hw.unk4274.cmd[2] = 0x0003AAAA;
414 r300->hw.unk4274.cmd[3] = 0x00000000;
415 r300->hw.unk4274.cmd[4] = 0x00000000;
416
417 r300->hw.unk4288.cmd[1] = 0x00000000;
418 r300->hw.unk4288.cmd[2] = 0x00000001;
419 r300->hw.unk4288.cmd[3] = 0x00000000;
420 r300->hw.unk4288.cmd[4] = 0x00000000;
421 r300->hw.unk4288.cmd[5] = 0x00000000;
422
423 r300->hw.unk42A0.cmd[1] = 0x00000000;
424
425 r300->hw.unk42B4.cmd[1] = 0x00000000;
426
427 r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
428 r300->hw.unk42C0.cmd[2] = 0x00000000;
429
430 /* The second constant is needed to get glxgears display anything .. */
431 r300->hw.rc.cmd[1] = R300_RS_CNTL_0_UNKNOWN_7 | R300_RS_CNTL_0_UNKNOWN_18;
432 r300->hw.rc.cmd[2] = 0;
433
434 for(i = 1; i <= 8; ++i)
435 r300->hw.ri.cmd[i] = 0x00d10000;
436 r300->hw.ri.cmd[R300_RI_INTERP_1] |= R300_RS_INTERP_1_UNKNOWN;
437 r300->hw.ri.cmd[R300_RI_INTERP_2] |= R300_RS_INTERP_2_UNKNOWN;
438 r300->hw.ri.cmd[R300_RI_INTERP_3] |= R300_RS_INTERP_3_UNKNOWN;
439
440 ((drm_r300_cmd_header_t*)r300->hw.rr.cmd)->unchecked_state.count = 1;
441 for(i = 1; i <= 8; ++i)
442 r300->hw.rr.cmd[i] = 0;
443 r300->hw.rr.cmd[R300_RR_ROUTE_0] = 0x4000;
444
445 r300->hw.unk43A4.cmd[1] = 0x0000001C;
446 r300->hw.unk43A4.cmd[2] = 0x2DA49525;
447
448 r300->hw.unk43E8.cmd[1] = 0x00FFFFFF;
449
450 r300->hw.fp.cmd[R300_FP_CNTL0] = 0;
451 r300->hw.fp.cmd[R300_FP_CNTL1] = 0;
452 r300->hw.fp.cmd[R300_FP_CNTL2] = 0;
453 r300->hw.fp.cmd[R300_FP_NODE0] = 0;
454 r300->hw.fp.cmd[R300_FP_NODE1] = 0;
455 r300->hw.fp.cmd[R300_FP_NODE2] = 0;
456 r300->hw.fp.cmd[R300_FP_NODE3] = 0;
457
458 r300->hw.unk46A4.cmd[1] = 0x00001B01;
459 r300->hw.unk46A4.cmd[2] = 0x00001B0F;
460 r300->hw.unk46A4.cmd[3] = 0x00001B0F;
461 r300->hw.unk46A4.cmd[4] = 0x00001B0F;
462 r300->hw.unk46A4.cmd[5] = 0x00000001;
463
464 for(i = 1; i <= 64; ++i) {
465 /* create NOP instructions */
466 r300->hw.fpi[0].cmd[i] = FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO));
467 r300->hw.fpi[1].cmd[i] = FP_SELC(0,XYZ,NO,FP_TMP(0),0,0);
468 r300->hw.fpi[2].cmd[i] = FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO));
469 r300->hw.fpi[3].cmd[i] = FP_SELA(0,W,NO,FP_TMP(0),0,0);
470 }
471
472 r300->hw.unk4BC0.cmd[1] = 0;
473
474 r300->hw.unk4BC8.cmd[1] = 0;
475 r300->hw.unk4BC8.cmd[2] = 0;
476 r300->hw.unk4BC8.cmd[3] = 0;
477
478 r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
479
480 r300->hw.unk4BD8.cmd[1] = 0;
481
482 r300->hw.unk4E00.cmd[1] = 0;
483
484 r300->hw.bld.cmd[R300_BLD_CBLEND] = 0;
485 r300->hw.bld.cmd[R300_BLD_ABLEND] = 0;
486
487 r300->hw.unk4E10.cmd[1] = 0;
488 r300->hw.unk4E10.cmd[2] = 0;
489 r300->hw.unk4E10.cmd[3] = 0;
490
491 r300->hw.cb.cmd[R300_CB_OFFSET] =
492 r300->radeon.radeonScreen->backOffset +
493 r300->radeon.radeonScreen->fbLocation;
494 r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.radeonScreen->backPitch
495 | R300_COLOR_UNKNOWN_22_23;
496
497 r300->hw.unk4E50.cmd[1] = 0;
498 r300->hw.unk4E50.cmd[2] = 0;
499 r300->hw.unk4E50.cmd[3] = 0;
500 r300->hw.unk4E50.cmd[4] = 0;
501 r300->hw.unk4E50.cmd[5] = 0;
502 r300->hw.unk4E50.cmd[6] = 0;
503 r300->hw.unk4E50.cmd[7] = 0;
504 r300->hw.unk4E50.cmd[8] = 0;
505 r300->hw.unk4E50.cmd[9] = 0;
506
507 r300->hw.unk4E88.cmd[1] = 0;
508
509 r300->hw.unk4EA0.cmd[1] = 0x00000000;
510 r300->hw.unk4EA0.cmd[2] = 0xffffffff;
511
512 r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
513
514 r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format?
515 r300->hw.unk4F10.cmd[2] = 0x00000000;
516 r300->hw.unk4F10.cmd[3] = 0x00000003;
517 r300->hw.unk4F10.cmd[4] = 0x00000000;
518
519 r300->hw.zb.cmd[R300_ZB_OFFSET] =
520 r300->radeon.radeonScreen->depthOffset +
521 r300->radeon.radeonScreen->fbLocation;
522 r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch;
523
524 r300->hw.unk4F28.cmd[1] = 0;
525
526 r300->hw.unk4F30.cmd[1] = 0;
527 r300->hw.unk4F30.cmd[2] = 0;
528
529 r300->hw.unk4F44.cmd[1] = 0;
530
531 r300->hw.unk4F54.cmd[1] = 0;
532
533 ((drm_r300_cmd_header_t*)r300->hw.vpi.cmd)->vpu.count = 0;
534 for(i = 1; i < R300_VPI_CMDSIZE; i += 4) {
535 /* MOV t0, t0 */
536 r300->hw.vpi.cmd[i+0] = VP_OUT(ADD,TMP,0,XYZW);
537 r300->hw.vpi.cmd[i+1] = VP_IN(TMP,0);
538 r300->hw.vpi.cmd[i+2] = VP_ZERO();
539 r300->hw.vpi.cmd[i+3] = VP_ZERO();
540 }
541
542 ((drm_r300_cmd_header_t*)r300->hw.vpp.cmd)->vpu.count = 0;
543 for(i = 1; i < R300_VPP_CMDSIZE; ++i)
544 r300->hw.vpp.cmd[i] = 0;
545
546 r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
547 r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
548 r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
549 r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
550
551 /* Initialize texture units */
552 for(i=0;i<r300->radeon.glCtx->Const.MaxTextureUnits;i++){
553 r300->hw.tex.filter.cmd[R300_TEX_VALUE_0+i]=0x0;
554 r300->hw.tex.unknown1.cmd[R300_TEX_VALUE_0+i]=0x0;
555 r300->hw.tex.size.cmd[R300_TEX_VALUE_0+i]=0x0;
556 r300->hw.tex.format.cmd[R300_TEX_VALUE_0+i]=0x0;
557 r300->hw.tex.offset.cmd[R300_TEX_VALUE_0+i]=0x0;
558 r300->hw.tex.unknown4.cmd[R300_TEX_VALUE_0+i]=0x0;
559 r300->hw.tex.unknown5.cmd[R300_TEX_VALUE_0+i]=0x0;
560 }
561 //END: TODO
562
563 r300->hw.all_dirty = GL_TRUE;
564 }
565
566
567
568 /**
569 * Calculate initial hardware state and register state functions.
570 * Assumes that the command buffer and state atoms have been
571 * initialized already.
572 */
573 void r300InitState(r300ContextPtr r300)
574 {
575 radeonInitState(&r300->radeon);
576
577 r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
578
579 r300ResetHwState(r300);
580 }
581
582
583
584 /**
585 * Initialize driver's state callback functions
586 */
587 void r300InitStateFuncs(struct dd_function_table* functions)
588 {
589 radeonInitStateFuncs(functions);
590
591 functions->UpdateState = r300InvalidateState;
592 functions->Enable = r300Enable;
593 functions->ColorMask = r300ColorMask;
594 functions->DepthFunc = r300DepthFunc;
595 functions->DepthMask = r300DepthMask;
596 functions->CullFace = r300CullFace;
597 functions->FrontFace = r300FrontFace;
598
599 /* Viewport related */
600 functions->Viewport = r300Viewport;
601 functions->DepthRange = r300DepthRange;
602 }
603