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[mesa.git] / src / mesa / drivers / dri / r300 / r500_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * \file
30 *
31 * \author Ben Skeggs <darktama@iinet.net.au>
32 *
33 * \author Jerome Glisse <j.glisse@gmail.com>
34 *
35 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
36 *
37 * \todo Depth write, WPOS/FOGC inputs
38 *
39 * \todo FogOption
40 *
41 * \todo Verify results of opcodes for accuracy, I've only checked them in
42 * specific cases.
43 */
44
45 #include "glheader.h"
46 #include "macros.h"
47 #include "enums.h"
48 #include "shader/prog_instruction.h"
49 #include "shader/prog_parameter.h"
50 #include "shader/prog_print.h"
51
52 #include "r300_context.h"
53 #include "r500_fragprog.h"
54 #include "r300_reg.h"
55 #include "r300_state.h"
56
57 /*
58 * Useful macros and values
59 */
60 #define ERROR(fmt, args...) do { \
61 fprintf(stderr, "%s::%s(): " fmt "\n", \
62 __FILE__, __FUNCTION__, ##args); \
63 fp->error = GL_TRUE; \
64 } while(0)
65
66 #define COMPILE_STATE struct r300_pfs_compile_state *cs = fp->cs
67
68 #define R500_US_NUM_TEMP_REGS 128
69 #define R500_US_NUM_CONST_REGS 256
70
71 /* "Register" flags */
72 #define REG_CONSTANT (1 << 8)
73 #define REG_SRC_REL (1 << 9)
74 #define REG_DEST_REL (1 << 7)
75
76 /* Swizzle tools */
77 #define R500_SWIZZLE_ZERO 4
78 #define R500_SWIZZLE_HALF 5
79 #define R500_SWIZZLE_ONE 6
80 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
81 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
82 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
83 /* Swizzles for inst2 */
84 #define MAKE_SWIZ_TEX_STRQ(x) (x << 8)
85 #define MAKE_SWIZ_TEX_RGBA(x) (x << 24)
86 /* Swizzles for inst3 */
87 #define MAKE_SWIZ_RGB_A(x) (x << 2)
88 #define MAKE_SWIZ_RGB_B(x) (x << 15)
89 /* Swizzles for inst4 */
90 #define MAKE_SWIZ_ALPHA_A(x) (x << 14)
91 #define MAKE_SWIZ_ALPHA_B(x) (x << 21)
92 /* Swizzle for inst5 */
93 #define MAKE_SWIZ_RGBA_C(x) (x << 14)
94 #define MAKE_SWIZ_ALPHA_C(x) (x << 27)
95
96 static inline GLuint make_rgb_swizzle(struct prog_src_register src) {
97 GLuint swiz = 0x0;
98 GLuint temp;
99 /* This could be optimized, but it should be plenty fast already. */
100 int i;
101 for (i = 0; i < 3; i++) {
102 temp = (src.Swizzle >> i*3) & 0x7;
103 /* Fix SWIZZLE_ONE */
104 if (temp == 5) temp++;
105 swiz += temp << i*3;
106 }
107 return swiz;
108 }
109
110 static inline GLuint make_alpha_swizzle(struct prog_src_register src) {
111 GLuint swiz = (src.Swizzle >> 12) & 0x7;
112 if (swiz == 5) swiz++;
113 return swiz;
114 }
115
116 static inline GLuint make_strq_swizzle(struct prog_src_register src) {
117 GLuint swiz = 0x0;
118 GLuint temp = src.Swizzle;
119 int i;
120 for (i = 0; i < 4; i++) {
121 swiz += (temp & 0x3) << i*2;
122 temp >>= 3;
123 }
124 return swiz;
125 }
126
127 static int get_temp(struct r500_fragment_program *fp, int slot) {
128
129 COMPILE_STATE;
130
131 int r = slot;
132
133 while (cs->inputs[r].refcount != 0) {
134 /* Crap, taken. */
135 r++;
136 }
137
138 fp->temp_reg_offset = r - slot;
139
140 if (r >= R500_US_NUM_TEMP_REGS) {
141 ERROR("Out of hardware temps!\n");
142 return 0;
143 }
144
145 if (r > fp->max_temp_idx)
146 fp->max_temp_idx = r;
147
148 return r;
149 }
150
151 /* Borrowed verbatim from r300_fragprog since it hasn't changed. */
152 static GLuint emit_const4fv(struct r500_fragment_program *fp,
153 const GLfloat * cp)
154 {
155 GLuint reg = 0x0;
156 int index;
157
158 for (index = 0; index < fp->const_nr; ++index) {
159 if (fp->constant[index] == cp)
160 break;
161 }
162
163 if (index >= fp->const_nr) {
164 if (index >= R500_US_NUM_CONST_REGS) {
165 ERROR("Out of hw constants!\n");
166 return reg;
167 }
168
169 fp->const_nr++;
170 fp->constant[index] = cp;
171 }
172
173 reg = index | REG_CONSTANT;
174 return reg;
175 }
176
177 static GLuint make_src(struct r500_fragment_program *fp, struct prog_src_register src) {
178 COMPILE_STATE;
179 GLuint reg;
180 switch (src.File) {
181 case PROGRAM_TEMPORARY:
182 reg = src.Index + fp->temp_reg_offset;
183 break;
184 case PROGRAM_INPUT:
185 reg = cs->inputs[src.Index].reg;
186 break;
187 case PROGRAM_STATE_VAR:
188 case PROGRAM_NAMED_PARAM:
189 case PROGRAM_CONSTANT:
190 reg = emit_const4fv(fp, fp->mesa_program.Base.Parameters->
191 ParameterValues[src.Index]);
192 break;
193 default:
194 ERROR("Can't handle src.File %x\n", src.File);
195 reg = 0x0;
196 break;
197 }
198 return reg;
199 }
200
201 static GLuint make_dest(struct r500_fragment_program *fp, struct prog_dst_register dest) {
202 GLuint reg;
203 switch (dest.File) {
204 case PROGRAM_TEMPORARY:
205 reg = dest.Index + fp->temp_reg_offset;
206 break;
207 case PROGRAM_OUTPUT:
208 /* Eventually we may need to handle multiple
209 * rendering targets... */
210 reg = dest.Index;
211 break;
212 default:
213 ERROR("Can't handle dest.File %x\n", dest.File);
214 reg = 0x0;
215 break;
216 }
217 return reg;
218 }
219
220 static void emit_tex(struct r500_fragment_program *fp,
221 struct prog_instruction *fpi, int opcode, int dest, int counter)
222 {
223 int hwsrc, hwdest;
224 GLuint mask;
225
226 mask = fpi->DstReg.WriteMask << 11;
227 hwsrc = make_src(fp, fpi->SrcReg[0]);
228
229 fp->inst[counter].inst0 = R500_INST_TYPE_TEX | mask
230 | R500_INST_TEX_SEM_WAIT;
231
232 fp->inst[counter].inst1 = R500_TEX_ID(fpi->TexSrcUnit)
233 | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
234
235 if (fpi->TexSrcTarget == TEXTURE_RECT_INDEX)
236 fp->inst[counter].inst1 |= R500_TEX_UNSCALED;
237
238 switch (opcode) {
239 case OPCODE_KIL:
240 fp->inst[counter].inst1 |= R500_TEX_INST_TEXKILL;
241 break;
242 case OPCODE_TEX:
243 fp->inst[counter].inst1 |= R500_TEX_INST_LD;
244 break;
245 case OPCODE_TXB:
246 fp->inst[counter].inst1 |= R500_TEX_INST_LODBIAS;
247 break;
248 case OPCODE_TXP:
249 fp->inst[counter].inst1 |= R500_TEX_INST_PROJ;
250 break;
251 default:
252 ERROR("emit_tex can't handle opcode %x\n", opcode);
253 }
254
255 fp->inst[counter].inst2 = R500_TEX_SRC_ADDR(hwsrc)
256 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
257 | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G
258 | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A
259 | R500_TEX_DST_ADDR(dest)
260 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
261 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
262
263
264
265 fp->inst[counter].inst3 = 0x0;
266 fp->inst[counter].inst4 = 0x0;
267 fp->inst[counter].inst5 = 0x0;
268 }
269
270 static void dumb_shader(struct r500_fragment_program *fp)
271 {
272 fp->inst[0].inst0 = R500_INST_TYPE_TEX
273 | R500_INST_TEX_SEM_WAIT
274 | R500_INST_RGB_WMASK_R
275 | R500_INST_RGB_WMASK_G
276 | R500_INST_RGB_WMASK_B
277 | R500_INST_ALPHA_WMASK
278 | R500_INST_RGB_CLAMP
279 | R500_INST_ALPHA_CLAMP;
280 fp->inst[0].inst1 = R500_TEX_ID(0)
281 | R500_TEX_INST_LD
282 | R500_TEX_SEM_ACQUIRE
283 | R500_TEX_IGNORE_UNCOVERED;
284 fp->inst[0].inst2 = R500_TEX_SRC_ADDR(0)
285 | R500_TEX_SRC_S_SWIZ_R
286 | R500_TEX_SRC_T_SWIZ_G
287 | R500_TEX_DST_ADDR(0)
288 | R500_TEX_DST_R_SWIZ_R
289 | R500_TEX_DST_G_SWIZ_G
290 | R500_TEX_DST_B_SWIZ_B
291 | R500_TEX_DST_A_SWIZ_A;
292 fp->inst[0].inst3 = R500_DX_ADDR(0)
293 | R500_DX_S_SWIZ_R
294 | R500_DX_T_SWIZ_R
295 | R500_DX_R_SWIZ_R
296 | R500_DX_Q_SWIZ_R
297 | R500_DY_ADDR(0)
298 | R500_DY_S_SWIZ_R
299 | R500_DY_T_SWIZ_R
300 | R500_DY_R_SWIZ_R
301 | R500_DY_Q_SWIZ_R;
302 fp->inst[0].inst4 = 0x0;
303 fp->inst[0].inst5 = 0x0;
304
305 fp->inst[1].inst0 = R500_INST_TYPE_OUT |
306 R500_INST_TEX_SEM_WAIT |
307 R500_INST_LAST |
308 R500_INST_RGB_OMASK_R |
309 R500_INST_RGB_OMASK_G |
310 R500_INST_RGB_OMASK_B |
311 R500_INST_ALPHA_OMASK;
312 fp->inst[1].inst1 = R500_RGB_ADDR0(0) |
313 R500_RGB_ADDR1(0) |
314 R500_RGB_ADDR1_CONST |
315 R500_RGB_ADDR2(0) |
316 R500_RGB_ADDR2_CONST |
317 R500_RGB_SRCP_OP_1_MINUS_2RGB0;
318 fp->inst[1].inst2 = R500_ALPHA_ADDR0(0) |
319 R500_ALPHA_ADDR1(0) |
320 R500_ALPHA_ADDR1_CONST |
321 R500_ALPHA_ADDR2(0) |
322 R500_ALPHA_ADDR2_CONST |
323 R500_ALPHA_SRCP_OP_1_MINUS_2A0;
324 fp->inst[1].inst3 = R500_ALU_RGB_SEL_A_SRC0 |
325 R500_ALU_RGB_R_SWIZ_A_R |
326 R500_ALU_RGB_G_SWIZ_A_G |
327 R500_ALU_RGB_B_SWIZ_A_B |
328 R500_ALU_RGB_SEL_B_SRC0 |
329 R500_ALU_RGB_R_SWIZ_B_1 |
330 R500_ALU_RGB_B_SWIZ_B_1 |
331 R500_ALU_RGB_G_SWIZ_B_1;
332 fp->inst[1].inst4 = R500_ALPHA_OP_MAD |
333 R500_ALPHA_SWIZ_A_A |
334 R500_ALPHA_SWIZ_B_1;
335 fp->inst[1].inst5 = R500_ALU_RGBA_OP_MAD |
336 R500_ALU_RGBA_R_SWIZ_0 |
337 R500_ALU_RGBA_G_SWIZ_0 |
338 R500_ALU_RGBA_B_SWIZ_0 |
339 R500_ALU_RGBA_A_SWIZ_0;
340
341 fp->cs->nrslots = 2;
342 fp->translated = GL_TRUE;
343 }
344
345 static void emit_alu(struct r500_fragment_program *fp, int counter, struct prog_instruction *fpi) {
346 if (fpi->DstReg.Index == PROGRAM_OUTPUT) {
347 fp->inst[counter].inst0 = R500_INST_TYPE_OUT
348 /* output_mask */
349 | (fpi->DstReg.WriteMask << 14);
350 } else {
351 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
352 /* pixel_mask */
353 | (fpi->DstReg.WriteMask << 11);
354 }
355
356 fp->inst[counter].inst0 |= R500_INST_TEX_SEM_WAIT;
357 }
358
359 static void emit_mov(struct r500_fragment_program *fp, int counter, struct prog_src_register src, GLuint dest) {
360 /* The r3xx shader uses MAD to implement MOV. We are using CMP, since
361 * it is technically more accurate and recommended by ATI/AMD. */
362 GLuint src_reg = make_src(fp, src);
363 fp->inst[counter].inst1 = R500_RGB_ADDR0(src_reg);
364 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src_reg);
365 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
366 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(src))
367 | R500_ALU_RGB_SEL_B_SRC0
368 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(src))
369 | R500_ALU_RGB_OMOD_DISABLE;
370 fp->inst[counter].inst4 = R500_ALPHA_OP_CMP
371 | R500_ALPHA_ADDRD(dest)
372 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(src))
373 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(src))
374 | R500_ALPHA_OMOD_DISABLE;
375 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP
376 | R500_ALU_RGBA_ADDRD(dest)
377 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
378 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
379 }
380
381 static GLboolean parse_program(struct r500_fragment_program *fp)
382 {
383 struct gl_fragment_program *mp = &fp->mesa_program;
384 const struct prog_instruction *inst = mp->Base.Instructions;
385 struct prog_instruction *fpi;
386 GLuint src[3], dest, temp[2];
387 int flags, pixel_mask = 0, output_mask = 0, counter = 0;
388
389 if (!inst || inst[0].Opcode == OPCODE_END) {
390 ERROR("The program is empty!\n");
391 return GL_FALSE;
392 }
393
394 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
395
396 if (fpi->Opcode != OPCODE_KIL) {
397 dest = make_dest(fp, fpi->DstReg);
398
399 pixel_mask = fpi->DstReg.WriteMask << 11;
400 output_mask = fpi->DstReg.WriteMask << 14;
401 }
402
403 switch (fpi->Opcode) {
404 case OPCODE_ABS:
405 emit_alu(fp, counter, fpi);
406 emit_mov(fp, counter, fpi->SrcReg[0], dest);
407 fp->inst[counter].inst3 |= R500_ALU_RGB_MOD_A_ABS
408 | R500_ALU_RGB_MOD_B_ABS;
409 fp->inst[counter].inst4 |= R500_ALPHA_MOD_A_ABS
410 | R500_ALPHA_MOD_B_ABS;
411 break;
412 case OPCODE_ADD:
413 src[0] = make_src(fp, fpi->SrcReg[0]);
414 src[1] = make_src(fp, fpi->SrcReg[1]);
415 /* Variation on MAD: 1*src0+src1 */
416 emit_alu(fp, counter, fpi);
417 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
418 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(0);
419 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
420 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(0);
421 fp->inst[counter].inst3 = /* 1 */
422 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
423 | R500_ALU_RGB_SEL_B_SRC0 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
424 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
425 | R500_ALPHA_ADDRD(dest)
426 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
427 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
428 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
429 | R500_ALU_RGBA_ADDRD(dest)
430 | R500_ALU_RGBA_SEL_C_SRC1
431 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
432 | R500_ALU_RGBA_ALPHA_SEL_C_SRC1
433 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]));
434 break;
435 case OPCODE_CMP:
436 src[0] = make_src(fp, fpi->SrcReg[0]);
437 src[1] = make_src(fp, fpi->SrcReg[1]);
438 src[2] = make_src(fp, fpi->SrcReg[2]);
439 emit_alu(fp, counter, fpi);
440 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
441 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
442 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
443 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
444 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
445 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
446 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
447 fp->inst[counter].inst4 = R500_ALPHA_OP_CMP
448 | R500_ALPHA_ADDRD(dest)
449 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
450 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
451 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP
452 | R500_ALU_RGBA_ADDRD(dest)
453 | R500_ALU_RGBA_SEL_C_SRC2
454 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
455 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
456 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
457 break;
458 case OPCODE_COS:
459 src[0] = make_src(fp, fpi->SrcReg[0]);
460 emit_alu(fp, counter, fpi);
461 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
462 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
463 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
464 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
465 fp->inst[counter].inst4 = R500_ALPHA_OP_COS
466 | R500_ALPHA_ADDRD(dest)
467 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
468 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
469 | R500_ALU_RGBA_ADDRD(dest);
470 break;
471 case OPCODE_DP3:
472 src[0] = make_src(fp, fpi->SrcReg[0]);
473 src[1] = make_src(fp, fpi->SrcReg[1]);
474 emit_alu(fp, counter, fpi);
475 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
476 | R500_RGB_ADDR1(src[1]);
477 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
478 | R500_ALPHA_ADDR1(src[1]);
479 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
480 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
481 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
482 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
483 | R500_ALPHA_ADDRD(dest)
484 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
485 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
486 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP3
487 | R500_ALU_RGBA_ADDRD(dest);
488 break;
489 case OPCODE_DP4:
490 src[0] = make_src(fp, fpi->SrcReg[0]);
491 src[1] = make_src(fp, fpi->SrcReg[1]);
492 /* Based on DP3 */
493 emit_alu(fp, counter, fpi);
494 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
495 | R500_RGB_ADDR1(src[1]);
496 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
497 | R500_ALPHA_ADDR1(src[1]);
498 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
499 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
500 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
501 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
502 | R500_ALPHA_ADDRD(dest)
503 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
504 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
505 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4
506 | R500_ALU_RGBA_ADDRD(dest);
507 break;
508 case OPCODE_DPH:
509 src[0] = make_src(fp, fpi->SrcReg[0]);
510 src[1] = make_src(fp, fpi->SrcReg[1]);
511 /* Based on DP3 */
512 emit_alu(fp, counter, fpi);
513 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
514 | R500_RGB_ADDR1(src[1]);
515 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
516 | R500_ALPHA_ADDR1(src[1]);
517 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
518 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
519 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
520 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
521 | R500_ALPHA_ADDRD(dest)
522 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
523 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
524 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4
525 | R500_ALU_RGBA_ADDRD(dest);
526 break;
527 case OPCODE_EX2:
528 src[0] = make_src(fp, fpi->SrcReg[0]);
529 emit_alu(fp, counter, fpi);
530 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
531 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
532 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
533 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
534 fp->inst[counter].inst4 = R500_ALPHA_OP_EX2
535 | R500_ALPHA_ADDRD(dest)
536 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
537 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
538 | R500_ALU_RGBA_ADDRD(dest);
539 break;
540 case OPCODE_FRC:
541 src[0] = make_src(fp, fpi->SrcReg[0]);
542 emit_alu(fp, counter, fpi);
543 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
544 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
545 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
546 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
547 fp->inst[counter].inst4 = R500_ALPHA_OP_FRC
548 | R500_ALPHA_ADDRD(dest)
549 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
550 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC
551 | R500_ALU_RGBA_ADDRD(dest);
552 break;
553 case OPCODE_KIL:
554 emit_tex(fp, fpi, OPCODE_KIL, dest, counter);
555 break;
556 case OPCODE_LG2:
557 src[0] = make_src(fp, fpi->SrcReg[0]);
558 emit_alu(fp, counter, fpi);
559 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
560 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
561 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
562 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
563 fp->inst[counter].inst4 = R500_ALPHA_OP_LN2
564 | R500_ALPHA_ADDRD(dest)
565 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
566 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
567 | R500_ALU_RGBA_ADDRD(dest);
568 break;
569 case OPCODE_MAD:
570 src[0] = make_src(fp, fpi->SrcReg[0]);
571 src[1] = make_src(fp, fpi->SrcReg[1]);
572 src[2] = make_src(fp, fpi->SrcReg[2]);
573 emit_alu(fp, counter, fpi);
574 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
575 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
576 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
577 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
578 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
579 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
580 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
581 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
582 | R500_ALPHA_ADDRD(dest)
583 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
584 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
585 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
586 | R500_ALU_RGBA_ADDRD(dest)
587 | R500_ALU_RGBA_SEL_C_SRC2
588 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
589 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
590 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
591 break;
592 case OPCODE_MAX:
593 src[0] = make_src(fp, fpi->SrcReg[0]);
594 src[1] = make_src(fp, fpi->SrcReg[1]);
595 emit_alu(fp, counter, fpi);
596 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
597 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
598 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
599 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
600 | R500_ALU_RGB_SEL_B_SRC1
601 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
602 fp->inst[counter].inst4 = R500_ALPHA_OP_MAX
603 | R500_ALPHA_ADDRD(dest)
604 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
605 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
606 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX
607 | R500_ALU_RGBA_ADDRD(dest);
608 break;
609 case OPCODE_MIN:
610 src[0] = make_src(fp, fpi->SrcReg[0]);
611 src[1] = make_src(fp, fpi->SrcReg[1]);
612 emit_alu(fp, counter, fpi);
613 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
614 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
615 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
616 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
617 | R500_ALU_RGB_SEL_B_SRC1
618 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
619 fp->inst[counter].inst4 = R500_ALPHA_OP_MIN
620 | R500_ALPHA_ADDRD(dest)
621 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
622 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
623 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MIN
624 | R500_ALU_RGBA_ADDRD(dest);
625 break;
626 case OPCODE_MOV:
627 emit_alu(fp, counter, fpi);
628 emit_mov(fp, counter, fpi->SrcReg[0], dest);
629 break;
630 case OPCODE_MUL:
631 src[0] = make_src(fp, fpi->SrcReg[0]);
632 src[1] = make_src(fp, fpi->SrcReg[1]);
633 /* Variation on MAD: src0*src1+0 */
634 emit_alu(fp, counter, fpi);
635 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
636 | R500_RGB_ADDR1(src[1]);
637 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
638 | R500_ALPHA_ADDR1(src[1]);
639 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
640 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
641 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
642 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
643 | R500_ALPHA_ADDRD(dest)
644 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
645 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
646 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
647 | R500_ALU_RGBA_ADDRD(dest)
648 // | R500_ALU_RGBA_SEL_C_SRC2
649 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
650 // | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
651 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
652 break;
653 case OPCODE_RCP:
654 src[0] = make_src(fp, fpi->SrcReg[0]);
655 emit_alu(fp, counter, fpi);
656 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
657 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
658 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
659 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
660 fp->inst[counter].inst4 = R500_ALPHA_OP_RCP
661 | R500_ALPHA_ADDRD(dest)
662 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
663 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
664 | R500_ALU_RGBA_ADDRD(dest);
665 break;
666 case OPCODE_RSQ:
667 src[0] = make_src(fp, fpi->SrcReg[0]);
668 emit_alu(fp, counter, fpi);
669 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
670 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
671 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
672 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
673 fp->inst[counter].inst4 = R500_ALPHA_OP_RSQ
674 | R500_ALPHA_ADDRD(dest)
675 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
676 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
677 | R500_ALU_RGBA_ADDRD(dest);
678 break;
679 case OPCODE_SCS:
680 /* TODO: Make this elegant! */
681 /* Do a cosine, then a sine, masking out the channels we want to protect. */
682 src[0] = make_src(fp, fpi->SrcReg[0]);
683 /* Cosine only goes in R (x) channel. */
684 fpi->DstReg.WriteMask = 0x1;
685 emit_alu(fp, counter, fpi);
686 if (fpi->DstReg.File == PROGRAM_OUTPUT) {
687 fp->inst[counter].inst0 = R500_INST_TYPE_OUT
688 | R500_INST_TEX_SEM_WAIT | 0x1 << 14;
689 } else {
690 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
691 | R500_INST_TEX_SEM_WAIT | 0x1 << 11;
692 }
693 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
694 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
695 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
696 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
697 fp->inst[counter].inst4 = R500_ALPHA_OP_COS
698 | R500_ALPHA_ADDRD(dest)
699 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
700 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
701 | R500_ALU_RGBA_ADDRD(dest);
702 counter++;
703 /* Sine only goes in G (y) channel. */
704 fpi->DstReg.WriteMask = 0x2;
705 emit_alu(fp, counter, fpi);
706 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
707 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
708 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
709 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
710 fp->inst[counter].inst4 = R500_ALPHA_OP_SIN
711 | R500_ALPHA_ADDRD(dest)
712 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
713 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
714 | R500_ALU_RGBA_ADDRD(dest);
715 counter++;
716 /* Put 0 into B,A (z,w) channels. */
717 fpi->DstReg.WriteMask = 0xC;
718 emit_alu(fp, counter, fpi);
719 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
720 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
721 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
722 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ZERO)
723 | R500_ALU_RGB_SEL_B_SRC0
724 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ZERO);
725 fp->inst[counter].inst4 = R500_ALPHA_OP_CMP
726 | R500_ALPHA_ADDRD(dest)
727 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ZERO)
728 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(R500_SWIZZLE_ZERO);
729 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP
730 | R500_ALU_RGBA_ADDRD(dest)
731 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
732 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
733 break;
734 case OPCODE_SIN:
735 src[0] = make_src(fp, fpi->SrcReg[0]);
736 emit_alu(fp, counter, fpi);
737 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
738 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
739 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
740 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
741 fp->inst[counter].inst4 = R500_ALPHA_OP_SIN
742 | R500_ALPHA_ADDRD(dest)
743 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
744 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
745 | R500_ALU_RGBA_ADDRD(dest);
746 break;
747 case OPCODE_SUB:
748 src[0] = make_src(fp, fpi->SrcReg[0]);
749 src[1] = make_src(fp, fpi->SrcReg[1]);
750 /* Variation on MAD: 1*src0-src1 */
751 emit_alu(fp, counter, fpi);
752 fp->inst[counter].inst1 = R500_RGB_ADDR1(src[0])
753 | R500_RGB_ADDR2(src[1]);
754 fp->inst[counter].inst2 = R500_ALPHA_ADDR1(src[0])
755 | R500_ALPHA_ADDR2(src[1]);
756 fp->inst[counter].inst3 = /* 1 */
757 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
758 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
759 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
760 | R500_ALPHA_ADDRD(dest)
761 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
762 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
763 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
764 | R500_ALU_RGBA_ADDRD(dest)
765 | R500_ALU_RGBA_SEL_C_SRC2
766 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
767 | R500_ALU_RGBA_MOD_C_NEG
768 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
769 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]))
770 | R500_ALU_RGBA_ALPHA_MOD_C_NEG;
771 break;
772 case OPCODE_SWZ:
773 /* TODO: Negation masks! */
774 emit_alu(fp, counter, fpi);
775 emit_mov(fp, counter, fpi->SrcReg[0], dest);
776 break;
777 case OPCODE_TEX:
778 emit_tex(fp, fpi, OPCODE_TEX, dest, counter);
779 break;
780 case OPCODE_TXB:
781 emit_tex(fp, fpi, OPCODE_TXB, dest, counter);
782 break;
783 case OPCODE_TXP:
784 emit_tex(fp, fpi, OPCODE_TXP, dest, counter);
785 break;
786 default:
787 ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
788 break;
789 }
790
791 /* Finishing touches */
792 if (fpi->SaturateMode == SATURATE_ZERO_ONE) {
793 fp->inst[counter].inst0 |= R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP;
794 }
795
796 counter++;
797
798 if (fp->error)
799 return GL_FALSE;
800
801 }
802
803 /* Finish him! (If it's an ALU/OUT instruction...) */
804 if ((fp->inst[counter-1].inst0 & 0x3) == 1) {
805 fp->inst[counter-1].inst0 |= R500_INST_LAST;
806 } else {
807 /* We still need to put an output inst, right? */
808 fp->inst[counter].inst0 = R500_INST_TYPE_OUT
809 | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
810 output_mask;
811 fp->inst[counter].inst1 = R500_RGB_ADDR0(dest);
812 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(dest);
813 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
814 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB)
815 | R500_ALU_RGB_SEL_B_SRC0
816 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE);
817 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
818 | R500_ALPHA_ADDRD(0)
819 | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SEL_B_SRC0
820 | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1;
821 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
822 | R500_ALU_RGBA_ADDRD(0)
823 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
824 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
825 counter++;
826 }
827
828 fp->cs->nrslots = counter;
829
830 fp->max_temp_idx++;
831
832 return GL_TRUE;
833 }
834
835 static void init_program(r300ContextPtr r300, struct r500_fragment_program *fp)
836 {
837 struct r300_pfs_compile_state *cs = NULL;
838 struct gl_fragment_program *mp = &fp->mesa_program;
839 struct prog_instruction *fpi;
840 GLuint InputsRead = mp->Base.InputsRead;
841 GLuint temps_used = 0; /* for fp->temps[] */
842 int i, j;
843
844 /* New compile, reset tracking data */
845 fp->optimization =
846 driQueryOptioni(&r300->radeon.optionCache, "fp_optimization");
847 fp->translated = GL_FALSE;
848 fp->error = GL_FALSE;
849 fp->cs = cs = &(R300_CONTEXT(fp->ctx)->state.pfs_compile);
850 fp->cur_node = 0;
851 fp->first_node_has_tex = 0;
852 fp->const_nr = 0;
853 /* Size of pixel stack, plus 1. */
854 fp->max_temp_idx = 1;
855 /* Temp register offset. */
856 fp->temp_reg_offset = 0;
857 fp->node[0].alu_end = -1;
858 fp->node[0].tex_end = -1;
859
860 _mesa_memset(cs, 0, sizeof(*fp->cs));
861 for (i = 0; i < PFS_MAX_ALU_INST; i++) {
862 for (j = 0; j < 3; j++) {
863 cs->slot[i].vsrc[j] = SRC_CONST;
864 cs->slot[i].ssrc[j] = SRC_CONST;
865 }
866 }
867
868 /* Work out what temps the Mesa inputs correspond to, this must match
869 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
870 * configures itself based on the fragprog's InputsRead
871 *
872 * NOTE: this depends on get_hw_temp() allocating registers in order,
873 * starting from register 0, so we're just going to do that instead.
874 */
875
876 /* Texcoords come first */
877 for (i = 0; i < fp->ctx->Const.MaxTextureUnits; i++) {
878 if (InputsRead & (FRAG_BIT_TEX0 << i)) {
879 cs->inputs[FRAG_ATTRIB_TEX0 + i].refcount = 0;
880 cs->inputs[FRAG_ATTRIB_TEX0 + i].reg =
881 fp->temp_reg_offset;
882 fp->temp_reg_offset++;
883 }
884 }
885 InputsRead &= ~FRAG_BITS_TEX_ANY;
886
887 /* fragment position treated as a texcoord */
888 if (InputsRead & FRAG_BIT_WPOS) {
889 cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0;
890 cs->inputs[FRAG_ATTRIB_WPOS].reg =
891 fp->temp_reg_offset;
892 fp->temp_reg_offset++;
893 }
894 InputsRead &= ~FRAG_BIT_WPOS;
895
896 /* Then primary colour */
897 if (InputsRead & FRAG_BIT_COL0) {
898 cs->inputs[FRAG_ATTRIB_COL0].refcount = 0;
899 cs->inputs[FRAG_ATTRIB_COL0].reg =
900 fp->temp_reg_offset;
901 fp->temp_reg_offset++;
902 }
903 InputsRead &= ~FRAG_BIT_COL0;
904
905 /* Secondary color */
906 if (InputsRead & FRAG_BIT_COL1) {
907 cs->inputs[FRAG_ATTRIB_COL1].refcount = 0;
908 cs->inputs[FRAG_ATTRIB_COL1].reg =
909 fp->temp_reg_offset;
910 fp->temp_reg_offset++;
911 }
912 InputsRead &= ~FRAG_BIT_COL1;
913
914 /* Anything else */
915 if (InputsRead) {
916 WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead);
917 /* force read from hwreg 0 for now */
918 for (i = 0; i < 32; i++)
919 if (InputsRead & (1 << i))
920 cs->inputs[i].reg = 0;
921 }
922
923 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
924 * That way, we can free up the reg when it's no longer needed
925 */
926 if (!mp->Base.Instructions) {
927 ERROR("No instructions found in program, going to go die now.\n");
928 return;
929 }
930
931 #if 0
932 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
933 int idx;
934 for (i = 0; i < 3; i++) {
935 idx = fpi->SrcReg[i].Index;
936 if (fpi->SrcReg[i].File == PROGRAM_INPUT) {
937 cs->inputs[idx].refcount++;
938 if (fp->max_temp_idx < idx)
939 fp->max_temp_idx = idx;
940 }
941 }
942 }
943 #endif
944
945 fp->max_temp_idx = fp->temp_reg_offset + 1;
946
947 cs->temp_in_use = temps_used;
948 }
949
950 static void update_params(struct r500_fragment_program *fp)
951 {
952 struct gl_fragment_program *mp = &fp->mesa_program;
953
954 /* Ask Mesa nicely to fill in ParameterValues for us */
955 if (mp->Base.Parameters)
956 _mesa_load_state_parameters(fp->ctx, mp->Base.Parameters);
957 }
958
959 void r500TranslateFragmentShader(r300ContextPtr r300,
960 struct r500_fragment_program *fp)
961 {
962
963 struct r300_pfs_compile_state *cs = NULL;
964
965 if (!fp->translated) {
966
967 /* I need to see what I'm working with! */
968 fprintf(stderr, "Mesa program:\n");
969 fprintf(stderr, "-------------\n");
970 _mesa_print_program(&fp->mesa_program.Base);
971 fflush(stdout);
972
973 init_program(r300, fp);
974 cs = fp->cs;
975
976 if (parse_program(fp) == GL_FALSE) {
977 ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n");
978 dumb_shader(fp);
979 fp->inst_offset = 0;
980 fp->inst_end = cs->nrslots - 1;
981 return;
982 }
983 fp->inst_offset = 0;
984 fp->inst_end = cs->nrslots - 1;
985
986 fp->translated = GL_TRUE;
987 r300UpdateStateParameters(fp->ctx, _NEW_PROGRAM);
988 }
989
990 update_params(fp);
991 }