2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "r500_fragprog.h"
30 #include "radeon_nqssadce.h"
31 #include "radeon_program_alu.h"
34 static void reset_srcreg(struct prog_src_register
* reg
)
36 _mesa_bzero(reg
, sizeof(*reg
));
37 reg
->Swizzle
= SWIZZLE_NOOP
;
40 static struct prog_src_register
shadow_ambient(struct gl_program
*program
, int tmu
)
42 gl_state_index fail_value_tokens
[STATE_LENGTH
] = {
43 STATE_INTERNAL
, STATE_SHADOW_AMBIENT
, 0, 0, 0
45 struct prog_src_register reg
= { 0, };
47 fail_value_tokens
[2] = tmu
;
48 reg
.File
= PROGRAM_STATE_VAR
;
49 reg
.Index
= _mesa_add_state_reference(program
->Parameters
, fail_value_tokens
);
50 reg
.Swizzle
= SWIZZLE_WWWW
;
55 * Transform TEX, TXP, TXB, and KIL instructions in the following way:
56 * - premultiply texture coordinates for RECT
57 * - extract operand swizzles
58 * - introduce a temporary register when write masks are needed
61 static GLboolean
transform_TEX(
62 struct radeon_transform_context
*t
,
63 struct prog_instruction
* orig_inst
, void* data
)
65 struct r500_fragment_program_compiler
*compiler
=
66 (struct r500_fragment_program_compiler
*)data
;
67 struct prog_instruction inst
= *orig_inst
;
68 struct prog_instruction
* tgt
;
69 GLboolean destredirect
= GL_FALSE
;
71 if (inst
.Opcode
!= OPCODE_TEX
&&
72 inst
.Opcode
!= OPCODE_TXB
&&
73 inst
.Opcode
!= OPCODE_TXP
&&
74 inst
.Opcode
!= OPCODE_KIL
)
77 /* ARB_shadow & EXT_shadow_funcs */
78 if (inst
.Opcode
!= OPCODE_KIL
&&
79 t
->Program
->ShadowSamplers
& (1 << inst
.TexSrcUnit
)) {
80 GLuint comparefunc
= GL_NEVER
+ compiler
->fp
->state
.unit
[inst
.TexSrcUnit
].texture_compare_func
;
82 if (comparefunc
== GL_NEVER
|| comparefunc
== GL_ALWAYS
) {
83 tgt
= radeonAppendInstructions(t
->Program
, 1);
85 tgt
->Opcode
= OPCODE_MOV
;
86 tgt
->DstReg
= inst
.DstReg
;
87 if (comparefunc
== GL_ALWAYS
) {
88 tgt
->SrcReg
[0].File
= PROGRAM_BUILTIN
;
89 tgt
->SrcReg
[0].Swizzle
= SWIZZLE_1111
;
91 tgt
->SrcReg
[0] = shadow_ambient(t
->Program
, inst
.TexSrcUnit
);
96 inst
.DstReg
.File
= PROGRAM_TEMPORARY
;
97 inst
.DstReg
.Index
= radeonFindFreeTemporary(t
);
98 inst
.DstReg
.WriteMask
= WRITEMASK_XYZW
;
99 } else if (inst
.Opcode
!= OPCODE_KIL
&& inst
.DstReg
.File
!= PROGRAM_TEMPORARY
) {
100 int tempreg
= radeonFindFreeTemporary(t
);
102 inst
.DstReg
.File
= PROGRAM_TEMPORARY
;
103 inst
.DstReg
.Index
= tempreg
;
104 inst
.DstReg
.WriteMask
= WRITEMASK_XYZW
;
105 destredirect
= GL_TRUE
;
108 if (inst
.SrcReg
[0].File
!= PROGRAM_TEMPORARY
&& inst
.SrcReg
[0].File
!= PROGRAM_INPUT
) {
109 int tmpreg
= radeonFindFreeTemporary(t
);
110 tgt
= radeonAppendInstructions(t
->Program
, 1);
111 tgt
->Opcode
= OPCODE_MOV
;
112 tgt
->DstReg
.File
= PROGRAM_TEMPORARY
;
113 tgt
->DstReg
.Index
= tmpreg
;
114 tgt
->SrcReg
[0] = inst
.SrcReg
[0];
116 reset_srcreg(&inst
.SrcReg
[0]);
117 inst
.SrcReg
[0].File
= PROGRAM_TEMPORARY
;
118 inst
.SrcReg
[0].Index
= tmpreg
;
121 tgt
= radeonAppendInstructions(t
->Program
, 1);
122 _mesa_copy_instructions(tgt
, &inst
, 1);
124 if (inst
.Opcode
!= OPCODE_KIL
&&
125 t
->Program
->ShadowSamplers
& (1 << inst
.TexSrcUnit
)) {
126 GLuint comparefunc
= GL_NEVER
+ compiler
->fp
->state
.unit
[inst
.TexSrcUnit
].texture_compare_func
;
127 GLuint depthmode
= compiler
->fp
->state
.unit
[inst
.TexSrcUnit
].depth_texture_mode
;
128 int rcptemp
= radeonFindFreeTemporary(t
);
131 tgt
= radeonAppendInstructions(t
->Program
, 3);
133 tgt
[0].Opcode
= OPCODE_RCP
;
134 tgt
[0].DstReg
.File
= PROGRAM_TEMPORARY
;
135 tgt
[0].DstReg
.Index
= rcptemp
;
136 tgt
[0].DstReg
.WriteMask
= WRITEMASK_W
;
137 tgt
[0].SrcReg
[0] = inst
.SrcReg
[0];
138 tgt
[0].SrcReg
[0].Swizzle
= SWIZZLE_WWWW
;
140 tgt
[1].Opcode
= OPCODE_MAD
;
141 tgt
[1].DstReg
= inst
.DstReg
;
142 tgt
[1].DstReg
.WriteMask
= orig_inst
->DstReg
.WriteMask
;
143 tgt
[1].SrcReg
[0] = inst
.SrcReg
[0];
144 tgt
[1].SrcReg
[0].Swizzle
= SWIZZLE_ZZZZ
;
145 tgt
[1].SrcReg
[1].File
= PROGRAM_TEMPORARY
;
146 tgt
[1].SrcReg
[1].Index
= rcptemp
;
147 tgt
[1].SrcReg
[1].Swizzle
= SWIZZLE_WWWW
;
148 tgt
[1].SrcReg
[2].File
= PROGRAM_TEMPORARY
;
149 tgt
[1].SrcReg
[2].Index
= inst
.DstReg
.Index
;
150 if (depthmode
== 0) /* GL_LUMINANCE */
151 tgt
[1].SrcReg
[2].Swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
);
152 else if (depthmode
== 2) /* GL_ALPHA */
153 tgt
[1].SrcReg
[2].Swizzle
= SWIZZLE_WWWW
;
155 /* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
156 * r < tex <=> -tex+r < 0
157 * r >= tex <=> not (-tex+r < 0 */
158 if (comparefunc
== GL_LESS
|| comparefunc
== GL_GEQUAL
)
159 tgt
[1].SrcReg
[2].NegateBase
= tgt
[0].SrcReg
[2].NegateBase
^ NEGATE_XYZW
;
161 tgt
[1].SrcReg
[0].NegateBase
= tgt
[0].SrcReg
[0].NegateBase
^ NEGATE_XYZW
;
163 tgt
[2].Opcode
= OPCODE_CMP
;
164 tgt
[2].DstReg
= orig_inst
->DstReg
;
165 tgt
[2].SrcReg
[0].File
= PROGRAM_TEMPORARY
;
166 tgt
[2].SrcReg
[0].Index
= tgt
[1].DstReg
.Index
;
168 if (comparefunc
== GL_LESS
|| comparefunc
== GL_GREATER
) {
176 tgt
[2].SrcReg
[pass
].File
= PROGRAM_BUILTIN
;
177 tgt
[2].SrcReg
[pass
].Swizzle
= SWIZZLE_1111
;
178 tgt
[2].SrcReg
[fail
] = shadow_ambient(t
->Program
, inst
.TexSrcUnit
);
179 } else if (destredirect
) {
180 tgt
= radeonAppendInstructions(t
->Program
, 1);
182 tgt
->Opcode
= OPCODE_MOV
;
183 tgt
->DstReg
= orig_inst
->DstReg
;
184 tgt
->SrcReg
[0].File
= PROGRAM_TEMPORARY
;
185 tgt
->SrcReg
[0].Index
= inst
.DstReg
.Index
;
192 static void update_params(GLcontext
*ctx
, struct gl_fragment_program
*fp
)
194 /* Ask Mesa nicely to fill in ParameterValues for us */
195 if (fp
->Base
.Parameters
)
196 _mesa_load_state_parameters(ctx
, fp
->Base
.Parameters
);
201 * Transform the program to support fragment.position.
203 * Introduce a small fragment at the start of the program that will be
204 * the only code that directly reads the FRAG_ATTRIB_WPOS input.
205 * All other code pieces that reference that input will be rewritten
206 * to read from a newly allocated temporary.
208 * \todo if/when r5xx supports the radeon_program architecture, this is a
209 * likely candidate for code sharing.
211 static void insert_WPOS_trailer(struct r500_fragment_program_compiler
*compiler
)
213 GLuint InputsRead
= compiler
->fp
->Base
.Base
.InputsRead
;
215 if (!(InputsRead
& FRAG_BIT_WPOS
))
218 static gl_state_index tokens
[STATE_LENGTH
] = {
219 STATE_INTERNAL
, STATE_R300_WINDOW_DIMENSION
, 0, 0, 0
221 struct prog_instruction
*fpi
;
224 GLuint tempregi
= _mesa_find_free_register(compiler
->program
, PROGRAM_TEMPORARY
);
226 _mesa_insert_instructions(compiler
->program
, 0, 3);
227 fpi
= compiler
->program
->Instructions
;
229 /* perspective divide */
230 fpi
[i
].Opcode
= OPCODE_RCP
;
232 fpi
[i
].DstReg
.File
= PROGRAM_TEMPORARY
;
233 fpi
[i
].DstReg
.Index
= tempregi
;
234 fpi
[i
].DstReg
.WriteMask
= WRITEMASK_W
;
235 fpi
[i
].DstReg
.CondMask
= COND_TR
;
237 fpi
[i
].SrcReg
[0].File
= PROGRAM_INPUT
;
238 fpi
[i
].SrcReg
[0].Index
= FRAG_ATTRIB_WPOS
;
239 fpi
[i
].SrcReg
[0].Swizzle
= SWIZZLE_WWWW
;
242 fpi
[i
].Opcode
= OPCODE_MUL
;
244 fpi
[i
].DstReg
.File
= PROGRAM_TEMPORARY
;
245 fpi
[i
].DstReg
.Index
= tempregi
;
246 fpi
[i
].DstReg
.WriteMask
= WRITEMASK_XYZ
;
247 fpi
[i
].DstReg
.CondMask
= COND_TR
;
249 fpi
[i
].SrcReg
[0].File
= PROGRAM_INPUT
;
250 fpi
[i
].SrcReg
[0].Index
= FRAG_ATTRIB_WPOS
;
251 fpi
[i
].SrcReg
[0].Swizzle
= SWIZZLE_XYZW
;
253 fpi
[i
].SrcReg
[1].File
= PROGRAM_TEMPORARY
;
254 fpi
[i
].SrcReg
[1].Index
= tempregi
;
255 fpi
[i
].SrcReg
[1].Swizzle
= SWIZZLE_WWWW
;
258 /* viewport transformation */
259 window_index
= _mesa_add_state_reference(compiler
->program
->Parameters
, tokens
);
261 fpi
[i
].Opcode
= OPCODE_MAD
;
263 fpi
[i
].DstReg
.File
= PROGRAM_TEMPORARY
;
264 fpi
[i
].DstReg
.Index
= tempregi
;
265 fpi
[i
].DstReg
.WriteMask
= WRITEMASK_XYZ
;
266 fpi
[i
].DstReg
.CondMask
= COND_TR
;
268 fpi
[i
].SrcReg
[0].File
= PROGRAM_TEMPORARY
;
269 fpi
[i
].SrcReg
[0].Index
= tempregi
;
270 fpi
[i
].SrcReg
[0].Swizzle
=
271 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ZERO
);
273 fpi
[i
].SrcReg
[1].File
= PROGRAM_STATE_VAR
;
274 fpi
[i
].SrcReg
[1].Index
= window_index
;
275 fpi
[i
].SrcReg
[1].Swizzle
=
276 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ZERO
);
278 fpi
[i
].SrcReg
[2].File
= PROGRAM_STATE_VAR
;
279 fpi
[i
].SrcReg
[2].Index
= window_index
;
280 fpi
[i
].SrcReg
[2].Swizzle
=
281 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ZERO
);
284 for (; i
< compiler
->program
->NumInstructions
; ++i
) {
286 for (reg
= 0; reg
< 3; reg
++) {
287 if (fpi
[i
].SrcReg
[reg
].File
== PROGRAM_INPUT
&&
288 fpi
[i
].SrcReg
[reg
].Index
== FRAG_ATTRIB_WPOS
) {
289 fpi
[i
].SrcReg
[reg
].File
= PROGRAM_TEMPORARY
;
290 fpi
[i
].SrcReg
[reg
].Index
= tempregi
;
297 static void nqssadce_init(struct nqssadce_state
* s
)
299 s
->Outputs
[FRAG_RESULT_COLOR
].Sourced
= WRITEMASK_XYZW
;
300 s
->Outputs
[FRAG_RESULT_DEPTH
].Sourced
= WRITEMASK_W
;
303 static GLboolean
is_native_swizzle(GLuint opcode
, struct prog_src_register reg
)
308 if (opcode
== OPCODE_TEX
||
309 opcode
== OPCODE_TXB
||
310 opcode
== OPCODE_TXP
||
311 opcode
== OPCODE_KIL
) {
316 reg
.NegateBase
^= 15;
318 if (opcode
== OPCODE_KIL
) {
319 if (reg
.Swizzle
!= SWIZZLE_NOOP
)
322 for(i
= 0; i
< 4; ++i
) {
323 GLuint swz
= GET_SWZ(reg
.Swizzle
, i
);
324 if (swz
== SWIZZLE_NIL
) {
325 reg
.NegateBase
&= ~(1 << i
);
337 } else if (opcode
== OPCODE_DDX
|| opcode
== OPCODE_DDY
) {
338 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
339 * if it doesn't fit perfectly into a .xyzw case... */
340 if (reg
.Swizzle
== SWIZZLE_NOOP
&& !reg
.Abs
341 && !reg
.NegateBase
&& !reg
.NegateAbs
)
346 /* ALU instructions support almost everything */
351 for(i
= 0; i
< 3; ++i
) {
352 GLuint swz
= GET_SWZ(reg
.Swizzle
, i
);
353 if (swz
!= SWIZZLE_NIL
&& swz
!= SWIZZLE_ZERO
)
356 if ((reg
.NegateBase
& relevant
) && ((reg
.NegateBase
& relevant
) != relevant
))
364 * Implement a MOV with a potentially non-native swizzle.
366 * The only thing we *cannot* do in an ALU instruction is per-component
367 * negation. Therefore, we split the MOV into two instructions when necessary.
369 static void nqssadce_build_swizzle(struct nqssadce_state
*s
,
370 struct prog_dst_register dst
, struct prog_src_register src
)
372 struct prog_instruction
*inst
;
373 GLuint negatebase
[2] = { 0, 0 };
376 for(i
= 0; i
< 4; ++i
) {
377 GLuint swz
= GET_SWZ(src
.Swizzle
, i
);
378 if (swz
== SWIZZLE_NIL
)
380 negatebase
[GET_BIT(src
.NegateBase
, i
)] |= 1 << i
;
383 _mesa_insert_instructions(s
->Program
, s
->IP
, (negatebase
[0] ? 1 : 0) + (negatebase
[1] ? 1 : 0));
384 inst
= s
->Program
->Instructions
+ s
->IP
;
386 for(i
= 0; i
<= 1; ++i
) {
390 inst
->Opcode
= OPCODE_MOV
;
392 inst
->DstReg
.WriteMask
= negatebase
[i
];
393 inst
->SrcReg
[0] = src
;
399 static GLuint
build_dtm(GLuint depthmode
)
403 case GL_LUMINANCE
: return 0;
404 case GL_INTENSITY
: return 1;
405 case GL_ALPHA
: return 2;
409 static GLuint
build_func(GLuint comparefunc
)
411 return comparefunc
- GL_NEVER
;
416 * Collect all external state that is relevant for compiling the given
419 static void build_state(
421 struct r300_fragment_program
*fp
,
422 struct r300_fragment_program_external_state
*state
)
426 _mesa_bzero(state
, sizeof(*state
));
428 for(unit
= 0; unit
< 16; ++unit
) {
429 if (fp
->Base
.Base
.ShadowSamplers
& (1 << unit
)) {
430 struct gl_texture_object
* tex
= r300
->radeon
.glCtx
->Texture
.Unit
[unit
]._Current
;
432 state
->unit
[unit
].depth_texture_mode
= build_dtm(tex
->DepthMode
);
433 state
->unit
[unit
].texture_compare_func
= build_func(tex
->CompareFunc
);
438 static void dump_program(struct r500_fragment_program_code
*code
);
440 void r500TranslateFragmentShader(GLcontext
*ctx
, struct gl_fragment_program
*fp
)
442 r300ContextPtr r300
= R300_CONTEXT(ctx
);
443 struct r300_fragment_program
*r300_fp
= (struct r300_fragment_program
*)fp
;
444 struct r300_fragment_program_external_state state
;
446 build_state(r300
, r300_fp
, &state
);
447 if (_mesa_memcmp(&r300_fp
->state
, &state
, sizeof(state
))) {
448 /* TODO: cache compiled programs */
449 r300_fp
->translated
= GL_FALSE
;
450 _mesa_memcpy(&r300_fp
->state
, &state
, sizeof(state
));
453 if (!r300_fp
->translated
) {
454 struct r500_fragment_program_compiler compiler
;
456 compiler
.r300
= r300
;
457 compiler
.fp
= r300_fp
;
458 compiler
.code
= &r300_fp
->code
.r500
;
459 compiler
.program
= _mesa_clone_program(ctx
, &fp
->Base
);
461 if (RADEON_DEBUG
& DEBUG_PIXEL
) {
462 _mesa_printf("Compiler: Initial program:\n");
463 _mesa_print_program(compiler
.program
);
466 insert_WPOS_trailer(&compiler
);
468 struct radeon_program_transformation transformations
[] = {
469 { &transform_TEX
, &compiler
},
470 { &radeonTransformALU
, 0 },
471 { &radeonTransformDeriv
, 0 },
472 { &radeonTransformTrigScale
, 0 }
474 radeonLocalTransform(ctx
, compiler
.program
, 4, transformations
);
476 if (RADEON_DEBUG
& DEBUG_PIXEL
) {
477 _mesa_printf("Compiler: after native rewrite:\n");
478 _mesa_print_program(compiler
.program
);
481 struct radeon_nqssadce_descr nqssadce
= {
482 .Init
= &nqssadce_init
,
483 .IsNativeSwizzle
= &is_native_swizzle
,
484 .BuildSwizzle
= &nqssadce_build_swizzle
,
485 .RewriteDepthOut
= GL_TRUE
487 radeonNqssaDce(ctx
, compiler
.program
, &nqssadce
);
489 if (RADEON_DEBUG
& DEBUG_PIXEL
) {
490 _mesa_printf("Compiler: after NqSSA-DCE:\n");
491 _mesa_print_program(compiler
.program
);
494 if (!r500FragmentProgramEmit(&compiler
))
495 r300_fp
->error
= GL_TRUE
;
497 r300_fp
->translated
= GL_TRUE
;
499 /* Subtle: Rescue any parameters that have been added during transformations */
500 _mesa_free_parameter_list(fp
->Base
.Parameters
);
501 fp
->Base
.Parameters
= compiler
.program
->Parameters
;
502 compiler
.program
->Parameters
= 0;
504 _mesa_reference_program(ctx
, &compiler
.program
, 0);
506 r300UpdateStateParameters(ctx
, _NEW_PROGRAM
);
508 if (RADEON_DEBUG
& DEBUG_PIXEL
) {
509 if (!r300_fp
->error
) {
510 _mesa_printf("Machine-readable code:\n");
511 dump_program(&r300_fp
->code
.r500
);
517 update_params(ctx
, fp
);
521 static char *toswiz(int swiz_val
) {
528 case 5: return "1/2";
535 static char *toop(int op_val
)
539 case 0: str
= "MAD"; break;
540 case 1: str
= "DP3"; break;
541 case 2: str
= "DP4"; break;
542 case 3: str
= "D2A"; break;
543 case 4: str
= "MIN"; break;
544 case 5: str
= "MAX"; break;
545 case 6: str
= "Reserved"; break;
546 case 7: str
= "CND"; break;
547 case 8: str
= "CMP"; break;
548 case 9: str
= "FRC"; break;
549 case 10: str
= "SOP"; break;
550 case 11: str
= "MDH"; break;
551 case 12: str
= "MDV"; break;
556 static char *to_alpha_op(int op_val
)
560 case 0: str
= "MAD"; break;
561 case 1: str
= "DP"; break;
562 case 2: str
= "MIN"; break;
563 case 3: str
= "MAX"; break;
564 case 4: str
= "Reserved"; break;
565 case 5: str
= "CND"; break;
566 case 6: str
= "CMP"; break;
567 case 7: str
= "FRC"; break;
568 case 8: str
= "EX2"; break;
569 case 9: str
= "LN2"; break;
570 case 10: str
= "RCP"; break;
571 case 11: str
= "RSQ"; break;
572 case 12: str
= "SIN"; break;
573 case 13: str
= "COS"; break;
574 case 14: str
= "MDH"; break;
575 case 15: str
= "MDV"; break;
580 static char *to_mask(int val
)
584 case 0: str
= "NONE"; break;
585 case 1: str
= "R"; break;
586 case 2: str
= "G"; break;
587 case 3: str
= "RG"; break;
588 case 4: str
= "B"; break;
589 case 5: str
= "RB"; break;
590 case 6: str
= "GB"; break;
591 case 7: str
= "RGB"; break;
592 case 8: str
= "A"; break;
593 case 9: str
= "AR"; break;
594 case 10: str
= "AG"; break;
595 case 11: str
= "ARG"; break;
596 case 12: str
= "AB"; break;
597 case 13: str
= "ARB"; break;
598 case 14: str
= "AGB"; break;
599 case 15: str
= "ARGB"; break;
604 static char *to_texop(int val
)
607 case 0: return "NOP";
609 case 2: return "TEXKILL";
610 case 3: return "PROJ";
611 case 4: return "LODBIAS";
612 case 5: return "LOD";
613 case 6: return "DXDY";
618 static void dump_program(struct r500_fragment_program_code
*code
)
621 fprintf(stderr
, "R500 Fragment Program:\n--------\n");
628 if (code
->const_nr
) {
629 fprintf(stderr
, "--------\nConstants:\n");
630 for (n
= 0; n
< code
->const_nr
; n
++) {
631 fprintf(stderr
, "Constant %d: %i[%i]\n", n
,
632 code
->constant
[n
].File
, code
->constant
[n
].Index
);
634 fprintf(stderr
, "--------\n");
637 for (n
= 0; n
< code
->inst_end
+1; n
++) {
638 inst0
= inst
= code
->inst
[n
].inst0
;
639 fprintf(stderr
,"%d\t0:CMN_INST 0x%08x:", n
, inst
);
641 case R500_INST_TYPE_ALU
: str
= "ALU"; break;
642 case R500_INST_TYPE_OUT
: str
= "OUT"; break;
643 case R500_INST_TYPE_FC
: str
= "FC"; break;
644 case R500_INST_TYPE_TEX
: str
= "TEX"; break;
646 fprintf(stderr
,"%s %s %s %s %s ", str
,
647 inst
& R500_INST_TEX_SEM_WAIT
? "TEX_WAIT" : "",
648 inst
& R500_INST_LAST
? "LAST" : "",
649 inst
& R500_INST_NOP
? "NOP" : "",
650 inst
& R500_INST_ALU_WAIT
? "ALU WAIT" : "");
651 fprintf(stderr
,"wmask: %s omask: %s\n", to_mask((inst
>> 11) & 0xf),
652 to_mask((inst
>> 15) & 0xf));
654 switch(inst0
& 0x3) {
657 fprintf(stderr
,"\t1:RGB_ADDR 0x%08x:", code
->inst
[n
].inst1
);
658 inst
= code
->inst
[n
].inst1
;
660 fprintf(stderr
,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
661 inst
& 0xff, (inst
& (1<<8)) ? 'c' : 't',
662 (inst
>> 10) & 0xff, (inst
& (1<<18)) ? 'c' : 't',
663 (inst
>> 20) & 0xff, (inst
& (1<<28)) ? 'c' : 't',
666 fprintf(stderr
,"\t2:ALPHA_ADDR 0x%08x:", code
->inst
[n
].inst2
);
667 inst
= code
->inst
[n
].inst2
;
668 fprintf(stderr
,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
669 inst
& 0xff, (inst
& (1<<8)) ? 'c' : 't',
670 (inst
>> 10) & 0xff, (inst
& (1<<18)) ? 'c' : 't',
671 (inst
>> 20) & 0xff, (inst
& (1<<28)) ? 'c' : 't',
673 fprintf(stderr
,"\t3 RGB_INST: 0x%08x:", code
->inst
[n
].inst3
);
674 inst
= code
->inst
[n
].inst3
;
675 fprintf(stderr
,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d\n",
676 (inst
) & 0x3, toswiz((inst
>> 2) & 0x7), toswiz((inst
>> 5) & 0x7), toswiz((inst
>> 8) & 0x7),
678 (inst
>> 13) & 0x3, toswiz((inst
>> 15) & 0x7), toswiz((inst
>> 18) & 0x7), toswiz((inst
>> 21) & 0x7),
682 fprintf(stderr
,"\t4 ALPHA_INST:0x%08x:", code
->inst
[n
].inst4
);
683 inst
= code
->inst
[n
].inst4
;
684 fprintf(stderr
,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d w:%d\n", to_alpha_op(inst
& 0xf),
685 (inst
>> 4) & 0x7f, inst
& (1<<11) ? "(rel)":"",
686 (inst
>> 12) & 0x3, toswiz((inst
>> 14) & 0x7), (inst
>> 17) & 0x3,
687 (inst
>> 19) & 0x3, toswiz((inst
>> 21) & 0x7), (inst
>> 24) & 0x3,
690 fprintf(stderr
,"\t5 RGBA_INST: 0x%08x:", code
->inst
[n
].inst5
);
691 inst
= code
->inst
[n
].inst5
;
692 fprintf(stderr
,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst
& 0xf),
693 (inst
>> 4) & 0x7f, inst
& (1<<11) ? "(rel)":"",
694 (inst
>> 12) & 0x3, toswiz((inst
>> 14) & 0x7), toswiz((inst
>> 17) & 0x7), toswiz((inst
>> 20) & 0x7),
696 (inst
>> 25) & 0x3, toswiz((inst
>> 27) & 0x7), (inst
>> 30) & 0x3);
701 inst
= code
->inst
[n
].inst1
;
702 fprintf(stderr
,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst
, (inst
>> 16) & 0xf,
703 to_texop((inst
>> 22) & 0x7), (inst
& (1<<25)) ? "ACQ" : "",
704 (inst
& (1<<26)) ? "IGNUNC" : "", (inst
& (1<<27)) ? "UNSCALED" : "SCALED");
705 inst
= code
->inst
[n
].inst2
;
706 fprintf(stderr
,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst
,
707 inst
& 127, inst
& (1<<7) ? "(rel)" : "",
708 toswiz((inst
>> 8) & 0x3), toswiz((inst
>> 10) & 0x3),
709 toswiz((inst
>> 12) & 0x3), toswiz((inst
>> 14) & 0x3),
710 (inst
>> 16) & 127, inst
& (1<<23) ? "(rel)" : "",
711 toswiz((inst
>> 24) & 0x3), toswiz((inst
>> 26) & 0x3),
712 toswiz((inst
>> 28) & 0x3), toswiz((inst
>> 30) & 0x3));
714 fprintf(stderr
,"\t3:TEX_DXDY: 0x%08x\n", code
->inst
[n
].inst3
);
717 fprintf(stderr
,"\n");