2 * Copyright (C) 2005 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * \author Ben Skeggs <darktama@iinet.net.au>
33 * \author Jerome Glisse <j.glisse@gmail.com>
35 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
37 * \todo Depth write, WPOS/FOGC inputs
41 * \todo Verify results of opcodes for accuracy, I've only checked them in
48 #include "shader/prog_instruction.h"
49 #include "shader/prog_parameter.h"
50 #include "shader/prog_print.h"
52 #include "r300_context.h"
53 #include "r500_fragprog.h"
55 #include "r300_state.h"
58 * Useful macros and values
60 #define ERROR(fmt, args...) do { \
61 fprintf(stderr, "%s::%s(): " fmt "\n", \
62 __FILE__, __FUNCTION__, ##args); \
63 fp->error = GL_TRUE; \
66 #define COMPILE_STATE struct r300_pfs_compile_state *cs = fp->cs
68 #define R500_US_NUM_TEMP_REGS 128
69 #define R500_US_NUM_CONST_REGS 256
71 /* "Register" flags */
72 #define REG_CONSTANT (1 << 8)
73 #define REG_SRC_REL (1 << 9)
74 #define REG_DEST_REL (1 << 7)
77 #define R500_SWIZZLE_ZERO 4
78 #define R500_SWIZZLE_HALF 5
79 #define R500_SWIZZLE_ONE 6
80 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
81 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
82 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
83 /* Swizzles for inst2 */
84 #define MAKE_SWIZ_TEX_STRQ(x) (x << 8)
85 #define MAKE_SWIZ_TEX_RGBA(x) (x << 24)
86 /* Swizzles for inst3 */
87 #define MAKE_SWIZ_RGB_A(x) (x << 2)
88 #define MAKE_SWIZ_RGB_B(x) (x << 15)
89 /* Swizzles for inst4 */
90 #define MAKE_SWIZ_ALPHA_A(x) (x << 14)
91 #define MAKE_SWIZ_ALPHA_B(x) (x << 21)
92 /* Swizzle for inst5 */
93 #define MAKE_SWIZ_RGBA_C(x) (x << 14)
94 #define MAKE_SWIZ_ALPHA_C(x) (x << 27)
96 static inline GLuint
make_rgb_swizzle(struct prog_src_register src
) {
99 /* This could be optimized, but it should be plenty fast already. */
101 for (i
= 0; i
< 3; i
++) {
102 temp
= (src
.Swizzle
>> i
*3) & 0x7;
103 /* Fix SWIZZLE_ONE */
104 if (temp
== 5) temp
++;
110 static inline GLuint
make_alpha_swizzle(struct prog_src_register src
) {
111 GLuint swiz
= (src
.Swizzle
>> 12) & 0x7;
112 if (swiz
== 5) swiz
++;
116 static inline GLuint
make_strq_swizzle(struct prog_src_register src
) {
118 GLuint temp
= src
.Swizzle
;
120 for (i
= 0; i
< 4; i
++) {
121 swiz
+= (temp
& 0x3) << i
*2;
127 static int get_temp(struct r500_fragment_program
*fp
, int slot
) {
133 while (cs
->inputs
[r
].refcount
!= 0) {
138 fp
->temp_reg_offset
= r
- slot
;
140 if (r
>= R500_US_NUM_TEMP_REGS
) {
141 ERROR("Out of hardware temps!\n");
145 if (r
> fp
->max_temp_idx
)
146 fp
->max_temp_idx
= r
;
151 /* Borrowed verbatim from r300_fragprog since it hasn't changed. */
152 static GLuint
emit_const4fv(struct r500_fragment_program
*fp
,
158 for (index
= 0; index
< fp
->const_nr
; ++index
) {
159 if (fp
->constant
[index
] == cp
)
163 if (index
>= fp
->const_nr
) {
164 if (index
>= R500_US_NUM_CONST_REGS
) {
165 ERROR("Out of hw constants!\n");
170 fp
->constant
[index
] = cp
;
173 reg
= index
| REG_CONSTANT
;
177 static GLuint
make_src(struct r500_fragment_program
*fp
, struct prog_src_register src
) {
181 case PROGRAM_TEMPORARY
:
182 reg
= src
.Index
+ fp
->temp_reg_offset
;
185 reg
= cs
->inputs
[src
.Index
].reg
;
187 case PROGRAM_STATE_VAR
:
188 case PROGRAM_NAMED_PARAM
:
189 case PROGRAM_CONSTANT
:
190 reg
= emit_const4fv(fp
, fp
->mesa_program
.Base
.Parameters
->
191 ParameterValues
[src
.Index
]);
194 ERROR("Can't handle src.File %x\n", src
.File
);
201 static GLuint
make_dest(struct r500_fragment_program
*fp
, struct prog_dst_register dest
) {
204 case PROGRAM_TEMPORARY
:
205 reg
= dest
.Index
+ fp
->temp_reg_offset
;
208 /* Eventually we may need to handle multiple
209 * rendering targets... */
213 ERROR("Can't handle dest.File %x\n", dest
.File
);
220 static void emit_tex(struct r500_fragment_program
*fp
,
221 struct prog_instruction
*fpi
, int opcode
, int dest
, int counter
)
226 mask
= fpi
->DstReg
.WriteMask
<< 11;
227 hwsrc
= make_src(fp
, fpi
->SrcReg
[0]);
229 fp
->inst
[counter
].inst0
= R500_INST_TYPE_TEX
| mask
230 | R500_INST_TEX_SEM_WAIT
;
232 fp
->inst
[counter
].inst1
= fpi
->TexSrcUnit
233 | R500_TEX_SEM_ACQUIRE
| R500_TEX_IGNORE_UNCOVERED
;
235 if (fpi
->TexSrcTarget
== TEXTURE_RECT_INDEX
)
236 fp
->inst
[counter
].inst1
|= R500_TEX_UNSCALED
;
240 fp
->inst
[counter
].inst1
|= R500_TEX_INST_LD
;
243 fp
->inst
[counter
].inst1
|= R500_TEX_INST_LODBIAS
;
246 fp
->inst
[counter
].inst1
|= R500_TEX_INST_PROJ
;
249 ERROR("emit_tex can't handle opcode %x\n", opcode
);
252 fp
->inst
[counter
].inst2
= R500_TEX_SRC_ADDR(hwsrc
)
253 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
254 | R500_TEX_SRC_S_SWIZ_R
| R500_TEX_SRC_T_SWIZ_G
255 | R500_TEX_SRC_R_SWIZ_B
| R500_TEX_SRC_Q_SWIZ_A
256 | R500_TEX_DST_ADDR(dest
)
257 | R500_TEX_DST_R_SWIZ_R
| R500_TEX_DST_G_SWIZ_G
258 | R500_TEX_DST_B_SWIZ_B
| R500_TEX_DST_A_SWIZ_A
;
262 fp
->inst
[counter
].inst3
= 0x0;
263 fp
->inst
[counter
].inst4
= 0x0;
264 fp
->inst
[counter
].inst5
= 0x0;
267 static void dumb_shader(struct r500_fragment_program
*fp
)
269 fp
->inst
[0].inst0
= R500_INST_TYPE_TEX
270 | R500_INST_TEX_SEM_WAIT
271 | R500_INST_RGB_WMASK_R
272 | R500_INST_RGB_WMASK_G
273 | R500_INST_RGB_WMASK_B
274 | R500_INST_ALPHA_WMASK
275 | R500_INST_RGB_CLAMP
276 | R500_INST_ALPHA_CLAMP
;
277 fp
->inst
[0].inst1
= R500_TEX_ID(0)
279 | R500_TEX_SEM_ACQUIRE
280 | R500_TEX_IGNORE_UNCOVERED
;
281 fp
->inst
[0].inst2
= R500_TEX_SRC_ADDR(0)
282 | R500_TEX_SRC_S_SWIZ_R
283 | R500_TEX_SRC_T_SWIZ_G
284 | R500_TEX_DST_ADDR(0)
285 | R500_TEX_DST_R_SWIZ_R
286 | R500_TEX_DST_G_SWIZ_G
287 | R500_TEX_DST_B_SWIZ_B
288 | R500_TEX_DST_A_SWIZ_A
;
289 fp
->inst
[0].inst3
= R500_DX_ADDR(0)
299 fp
->inst
[0].inst4
= 0x0;
300 fp
->inst
[0].inst5
= 0x0;
302 fp
->inst
[1].inst0
= R500_INST_TYPE_OUT
|
303 R500_INST_TEX_SEM_WAIT
|
305 R500_INST_RGB_OMASK_R
|
306 R500_INST_RGB_OMASK_G
|
307 R500_INST_RGB_OMASK_B
|
308 R500_INST_ALPHA_OMASK
;
309 fp
->inst
[1].inst1
= R500_RGB_ADDR0(0) |
311 R500_RGB_ADDR1_CONST
|
313 R500_RGB_ADDR2_CONST
|
314 R500_RGB_SRCP_OP_1_MINUS_2RGB0
;
315 fp
->inst
[1].inst2
= R500_ALPHA_ADDR0(0) |
316 R500_ALPHA_ADDR1(0) |
317 R500_ALPHA_ADDR1_CONST
|
318 R500_ALPHA_ADDR2(0) |
319 R500_ALPHA_ADDR2_CONST
|
320 R500_ALPHA_SRCP_OP_1_MINUS_2A0
;
321 fp
->inst
[1].inst3
= R500_ALU_RGB_SEL_A_SRC0
|
322 R500_ALU_RGB_R_SWIZ_A_R
|
323 R500_ALU_RGB_G_SWIZ_A_G
|
324 R500_ALU_RGB_B_SWIZ_A_B
|
325 R500_ALU_RGB_SEL_B_SRC0
|
326 R500_ALU_RGB_R_SWIZ_B_1
|
327 R500_ALU_RGB_B_SWIZ_B_1
|
328 R500_ALU_RGB_G_SWIZ_B_1
;
329 fp
->inst
[1].inst4
= R500_ALPHA_OP_MAD
|
330 R500_ALPHA_SWIZ_A_A
|
332 fp
->inst
[1].inst5
= R500_ALU_RGBA_OP_MAD
|
333 R500_ALU_RGBA_R_SWIZ_0
|
334 R500_ALU_RGBA_G_SWIZ_0
|
335 R500_ALU_RGBA_B_SWIZ_0
|
336 R500_ALU_RGBA_A_SWIZ_0
;
339 fp
->translated
= GL_TRUE
;
342 /* static void emit_alu(struct r500_fragment_program *fp) {
345 static void emit_mov(struct r500_fragment_program
*fp
, int counter
, struct prog_src_register src
, GLuint dest
) {
346 /* The r3xx shader uses MAD to implement MOV. We are using CMP, since
347 * it is technically more accurate and recommended by ATI/AMD. */
348 GLuint src_reg
= make_src(fp
, src
);
349 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| R500_INST_TEX_SEM_WAIT
;
350 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src_reg
);
351 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src_reg
);
352 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
353 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(src
))
354 | R500_ALU_RGB_SEL_B_SRC0
355 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(src
))
356 | R500_ALU_RGB_OMOD_DISABLE
;
357 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_CMP
358 | R500_ALPHA_ADDRD(dest
)
359 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(src
))
360 | R500_ALPHA_SEL_B_SRC0
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(src
))
361 | R500_ALPHA_OMOD_DISABLE
;
362 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_CMP
363 | R500_ALU_RGBA_ADDRD(dest
)
364 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
365 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
368 static GLboolean
parse_program(struct r500_fragment_program
*fp
)
370 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
371 const struct prog_instruction
*inst
= mp
->Base
.Instructions
;
372 struct prog_instruction
*fpi
;
373 GLuint src
[3], dest
, temp
[2];
374 int flags
, mask
, counter
= 0;
376 if (!inst
|| inst
[0].Opcode
== OPCODE_END
) {
377 ERROR("The program is empty!\n");
381 for (fpi
= mp
->Base
.Instructions
; fpi
->Opcode
!= OPCODE_END
; fpi
++) {
383 if (fpi
->Opcode
!= OPCODE_KIL
) {
384 dest
= make_dest(fp
, fpi
->DstReg
);
385 mask
= fpi
->DstReg
.WriteMask
<< 11;
388 switch (fpi
->Opcode
) {
390 emit_mov(fp
, counter
, fpi
->SrcReg
[0], dest
);
391 fp
->inst
[counter
].inst0
|= mask
;
392 fp
->inst
[counter
].inst3
|= R500_ALU_RGB_MOD_A_ABS
393 | R500_ALU_RGB_MOD_B_ABS
;
394 fp
->inst
[counter
].inst4
|= R500_ALPHA_MOD_A_ABS
395 | R500_ALPHA_MOD_B_ABS
;
398 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
399 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
400 /* Variation on MAD: 1*src0+src1 */
401 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
403 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
404 | R500_RGB_ADDR1(src
[1]) | R500_RGB_ADDR2(0);
405 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
406 | R500_ALPHA_ADDR1(src
[1]) | R500_ALPHA_ADDR2(0);
407 fp
->inst
[counter
].inst3
= /* 1 */
408 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE
)
409 | R500_ALU_RGB_SEL_B_SRC0
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[0]));
410 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
411 | R500_ALPHA_ADDRD(dest
)
412 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE
)
413 | R500_ALPHA_SEL_B_SRC0
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[0]));
414 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
415 | R500_ALU_RGBA_ADDRD(dest
)
416 | R500_ALU_RGBA_SEL_C_SRC1
417 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[1]))
418 | R500_ALU_RGBA_ALPHA_SEL_C_SRC1
419 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[1]));
422 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
423 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
424 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
425 | R500_INST_TEX_SEM_WAIT
| mask
;
426 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
427 | R500_RGB_ADDR1(src
[1]);
428 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
429 | R500_ALPHA_ADDR1(src
[1]);
430 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
431 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
432 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
433 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_DP
434 | R500_ALPHA_ADDRD(dest
)
435 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
436 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
437 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_DP3
438 | R500_ALU_RGBA_ADDRD(dest
);
441 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
442 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
444 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
445 | R500_INST_TEX_SEM_WAIT
| mask
;
446 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
447 | R500_RGB_ADDR1(src
[1]);
448 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
449 | R500_ALPHA_ADDR1(src
[1]);
450 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
451 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
452 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
453 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_DP
454 | R500_ALPHA_ADDRD(dest
)
455 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
456 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
457 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_DP4
458 | R500_ALU_RGBA_ADDRD(dest
);
461 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
462 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
463 src
[2] = make_src(fp
, fpi
->SrcReg
[2]);
464 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
466 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
467 | R500_RGB_ADDR1(src
[1]) | R500_RGB_ADDR2(src
[2]);
468 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
469 | R500_ALPHA_ADDR1(src
[1]) | R500_ALPHA_ADDR2(src
[2]);
470 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
471 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
472 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
473 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
474 | R500_ALPHA_ADDRD(dest
)
475 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
476 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
477 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
478 | R500_ALU_RGBA_ADDRD(dest
)
479 | R500_ALU_RGBA_SEL_C_SRC2
480 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[2]))
481 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
482 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[2]));
485 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
486 src
[1] = make_src(fp
, fpi
->SrcReg
[0]);
487 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| mask
;
488 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]) | R500_RGB_ADDR1(src
[1]);
489 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]) | R500_ALPHA_ADDR1(src
[1]);
490 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
491 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
492 | R500_ALU_RGB_SEL_B_SRC1
493 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
494 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAX
495 | R500_ALPHA_ADDRD(dest
)
496 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
497 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
498 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAX
499 | R500_ALU_RGBA_ADDRD(dest
);
502 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
503 src
[1] = make_src(fp
, fpi
->SrcReg
[0]);
504 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| mask
;
505 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]) | R500_RGB_ADDR1(src
[1]);
506 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]) | R500_ALPHA_ADDR1(src
[1]);
507 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
508 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
509 | R500_ALU_RGB_SEL_B_SRC1
510 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
511 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MIN
512 | R500_ALPHA_ADDRD(dest
)
513 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
514 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
515 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MIN
516 | R500_ALU_RGBA_ADDRD(dest
);
519 emit_mov(fp
, counter
, fpi
->SrcReg
[0], dest
);
520 fp
->inst
[counter
].inst0
|= mask
;
523 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
524 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
525 /* Variation on MAD: src0*src1+0 */
526 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
527 | R500_INST_TEX_SEM_WAIT
| mask
;
528 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
529 | R500_RGB_ADDR1(src
[1]);
530 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
531 | R500_ALPHA_ADDR1(src
[1]);
532 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
533 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
534 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
535 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
536 | R500_ALPHA_ADDRD(dest
)
537 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
538 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
539 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
540 | R500_ALU_RGBA_ADDRD(dest
)
541 // | R500_ALU_RGBA_SEL_C_SRC2
542 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
543 // | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
544 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
547 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
548 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
549 /* Variation on MAD: 1*src0-src1 */
550 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
552 fp
->inst
[counter
].inst1
= R500_RGB_ADDR1(src
[0])
553 | R500_RGB_ADDR2(src
[1]);
554 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR1(src
[0])
555 | R500_ALPHA_ADDR2(src
[1]);
556 fp
->inst
[counter
].inst3
= /* 1 */
557 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE
)
558 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[0]));
559 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
560 | R500_ALPHA_ADDRD(dest
)
561 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE
)
562 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[0]));
563 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
564 | R500_ALU_RGBA_ADDRD(dest
)
565 | R500_ALU_RGBA_SEL_C_SRC2
566 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[1]))
567 | R500_ALU_RGBA_MOD_C_NEG
568 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
569 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[1]))
570 | R500_ALU_RGBA_ALPHA_MOD_C_NEG
;
573 emit_tex(fp
, fpi
, OPCODE_TEX
, dest
, counter
);
576 emit_tex(fp
, fpi
, OPCODE_TXB
, dest
, counter
);
579 emit_tex(fp
, fpi
, OPCODE_TXP
, dest
, counter
);
582 ERROR("unknown fpi->Opcode %d\n", fpi
->Opcode
);
586 /* Finishing touches */
587 if (fpi
->SaturateMode
== SATURATE_ZERO_ONE
) {
588 fp
->inst
[counter
].inst0
|= R500_INST_RGB_CLAMP
| R500_INST_ALPHA_CLAMP
;
590 if (fpi
->DstReg
.File
== PROGRAM_OUTPUT
) {
591 fp
->inst
[counter
].inst0
|= R500_INST_TYPE_OUT
592 | R500_INST_RGB_OMASK_R
| R500_INST_RGB_OMASK_G
593 | R500_INST_RGB_OMASK_B
| R500_INST_ALPHA_OMASK
;
603 /* Finish him! (If it's an ALU/OUT instruction...) */
604 if ((fp
->inst
[counter
].inst0
& 0x3) ^ 0x2) {
605 fp
->inst
[counter
].inst0
|= R500_INST_TYPE_OUT
606 | R500_INST_TEX_SEM_WAIT
| R500_INST_LAST
;
608 /* We still need to put an output inst, right? */
610 fp
->inst
[counter
].inst0
= R500_INST_TYPE_OUT
611 | R500_INST_TEX_SEM_WAIT
| R500_INST_LAST
612 | R500_INST_RGB_OMASK_R
| R500_INST_RGB_OMASK_G
613 | R500_INST_RGB_OMASK_B
| R500_INST_ALPHA_OMASK
;
614 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(dest
);
615 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(dest
);
616 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
617 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB
)
618 | R500_ALU_RGB_SEL_B_SRC0
619 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE
);
620 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
621 | R500_ALPHA_ADDRD(0)
622 | R500_ALPHA_SEL_A_SRC0
| R500_ALPHA_SEL_B_SRC0
623 | R500_ALPHA_SWIZ_A_A
| R500_ALPHA_SWIZ_B_1
;
624 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
625 | R500_ALU_RGBA_ADDRD(0)
626 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
627 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
630 fp
->cs
->nrslots
= counter
;
637 static void init_program(r300ContextPtr r300
, struct r500_fragment_program
*fp
)
639 struct r300_pfs_compile_state
*cs
= NULL
;
640 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
641 struct prog_instruction
*fpi
;
642 GLuint InputsRead
= mp
->Base
.InputsRead
;
643 GLuint temps_used
= 0; /* for fp->temps[] */
646 /* New compile, reset tracking data */
648 driQueryOptioni(&r300
->radeon
.optionCache
, "fp_optimization");
649 fp
->translated
= GL_FALSE
;
650 fp
->error
= GL_FALSE
;
651 fp
->cs
= cs
= &(R300_CONTEXT(fp
->ctx
)->state
.pfs_compile
);
653 fp
->first_node_has_tex
= 0;
655 /* Size of pixel stack, plus 1. */
656 fp
->max_temp_idx
= 1;
657 /* Temp register offset. */
658 fp
->temp_reg_offset
= 0;
659 fp
->node
[0].alu_end
= -1;
660 fp
->node
[0].tex_end
= -1;
662 _mesa_memset(cs
, 0, sizeof(*fp
->cs
));
663 for (i
= 0; i
< PFS_MAX_ALU_INST
; i
++) {
664 for (j
= 0; j
< 3; j
++) {
665 cs
->slot
[i
].vsrc
[j
] = SRC_CONST
;
666 cs
->slot
[i
].ssrc
[j
] = SRC_CONST
;
670 /* Work out what temps the Mesa inputs correspond to, this must match
671 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
672 * configures itself based on the fragprog's InputsRead
674 * NOTE: this depends on get_hw_temp() allocating registers in order,
675 * starting from register 0, so we're just going to do that instead.
678 /* Texcoords come first */
679 for (i
= 0; i
< fp
->ctx
->Const
.MaxTextureUnits
; i
++) {
680 if (InputsRead
& (FRAG_BIT_TEX0
<< i
)) {
681 cs
->inputs
[FRAG_ATTRIB_TEX0
+ i
].refcount
= 0;
682 cs
->inputs
[FRAG_ATTRIB_TEX0
+ i
].reg
=
684 fp
->temp_reg_offset
++;
687 InputsRead
&= ~FRAG_BITS_TEX_ANY
;
689 /* fragment position treated as a texcoord */
690 if (InputsRead
& FRAG_BIT_WPOS
) {
691 cs
->inputs
[FRAG_ATTRIB_WPOS
].refcount
= 0;
692 cs
->inputs
[FRAG_ATTRIB_WPOS
].reg
=
694 fp
->temp_reg_offset
++;
696 InputsRead
&= ~FRAG_BIT_WPOS
;
698 /* Then primary colour */
699 if (InputsRead
& FRAG_BIT_COL0
) {
700 cs
->inputs
[FRAG_ATTRIB_COL0
].refcount
= 0;
701 cs
->inputs
[FRAG_ATTRIB_COL0
].reg
=
703 fp
->temp_reg_offset
++;
705 InputsRead
&= ~FRAG_BIT_COL0
;
707 /* Secondary color */
708 if (InputsRead
& FRAG_BIT_COL1
) {
709 cs
->inputs
[FRAG_ATTRIB_COL1
].refcount
= 0;
710 cs
->inputs
[FRAG_ATTRIB_COL1
].reg
=
712 fp
->temp_reg_offset
++;
714 InputsRead
&= ~FRAG_BIT_COL1
;
718 WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead
);
719 /* force read from hwreg 0 for now */
720 for (i
= 0; i
< 32; i
++)
721 if (InputsRead
& (1 << i
))
722 cs
->inputs
[i
].reg
= 0;
725 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
726 * That way, we can free up the reg when it's no longer needed
728 if (!mp
->Base
.Instructions
) {
729 ERROR("No instructions found in program, going to go die now.\n");
734 for (fpi
= mp
->Base
.Instructions
; fpi
->Opcode
!= OPCODE_END
; fpi
++) {
736 for (i
= 0; i
< 3; i
++) {
737 idx
= fpi
->SrcReg
[i
].Index
;
738 if (fpi
->SrcReg
[i
].File
== PROGRAM_INPUT
) {
739 cs
->inputs
[idx
].refcount
++;
740 if (fp
->max_temp_idx
< idx
)
741 fp
->max_temp_idx
= idx
;
747 fp
->max_temp_idx
= fp
->temp_reg_offset
+ 1;
749 cs
->temp_in_use
= temps_used
;
752 static void update_params(struct r500_fragment_program
*fp
)
754 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
756 /* Ask Mesa nicely to fill in ParameterValues for us */
757 if (mp
->Base
.Parameters
)
758 _mesa_load_state_parameters(fp
->ctx
, mp
->Base
.Parameters
);
761 void r500TranslateFragmentShader(r300ContextPtr r300
,
762 struct r500_fragment_program
*fp
)
765 struct r300_pfs_compile_state
*cs
= NULL
;
767 if (!fp
->translated
) {
769 /* I need to see what I'm working with! */
770 fprintf(stderr
, "Mesa program:\n");
771 fprintf(stderr
, "-------------\n");
772 _mesa_print_program(&fp
->mesa_program
.Base
);
775 init_program(r300
, fp
);
778 if (parse_program(fp
) == GL_FALSE
) {
779 ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n");
784 fp
->translated
= GL_TRUE
;
785 r300UpdateStateParameters(fp
->ctx
, _NEW_PROGRAM
);