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r5xx: Fix FP inputs. (For good?)
[mesa.git] / src / mesa / drivers / dri / r300 / r500_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * \file
30 *
31 * \author Ben Skeggs <darktama@iinet.net.au>
32 *
33 * \author Jerome Glisse <j.glisse@gmail.com>
34 *
35 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
36 *
37 * \todo Depth write, WPOS/FOGC inputs
38 *
39 * \todo FogOption
40 *
41 * \todo Verify results of opcodes for accuracy, I've only checked them in
42 * specific cases.
43 */
44
45 #include "glheader.h"
46 #include "macros.h"
47 #include "enums.h"
48 #include "shader/prog_instruction.h"
49 #include "shader/prog_parameter.h"
50 #include "shader/prog_print.h"
51
52 #include "r300_context.h"
53 #include "r500_fragprog.h"
54 #include "r300_reg.h"
55 #include "r300_state.h"
56
57 /*
58 * Useful macros and values
59 */
60 #define ERROR(fmt, args...) do { \
61 fprintf(stderr, "%s::%s(): " fmt "\n", \
62 __FILE__, __FUNCTION__, ##args); \
63 fp->error = GL_TRUE; \
64 } while(0)
65
66 #define COMPILE_STATE struct r300_pfs_compile_state *cs = fp->cs
67
68 #define R500_US_NUM_TEMP_REGS 128
69 #define R500_US_NUM_CONST_REGS 256
70
71 /* "Register" flags */
72 #define REG_CONSTANT (1 << 8)
73 #define REG_SRC_REL (1 << 9)
74 #define REG_DEST_REL (1 << 7)
75
76 /* Swizzle tools */
77 #define R500_SWIZZLE_ZERO 4
78 #define R500_SWIZZLE_HALF 5
79 #define R500_SWIZZLE_ONE 6
80 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
81 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
82 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
83 /* Swizzles for inst2 */
84 #define MAKE_SWIZ_TEX_STRQ(x) (x << 8)
85 #define MAKE_SWIZ_TEX_RGBA(x) (x << 24)
86 /* Swizzles for inst3 */
87 #define MAKE_SWIZ_RGB_A(x) (x << 2)
88 #define MAKE_SWIZ_RGB_B(x) (x << 15)
89 /* Swizzles for inst4 */
90 #define MAKE_SWIZ_ALPHA_A(x) (x << 14)
91 #define MAKE_SWIZ_ALPHA_B(x) (x << 21)
92 /* Swizzle for inst5 */
93 #define MAKE_SWIZ_RGBA_C(x) (x << 14)
94 #define MAKE_SWIZ_ALPHA_C(x) (x << 27)
95
96 static inline GLuint make_rgb_swizzle(struct prog_src_register src) {
97 GLuint swiz = 0x0;
98 GLuint temp;
99 /* This could be optimized, but it should be plenty fast already. */
100 int i;
101 for (i = 0; i < 3; i++) {
102 temp = (src.Swizzle >> i*3) & 0x7;
103 /* Fix SWIZZLE_ONE */
104 if (temp == 5) temp++;
105 swiz += temp << i*3;
106 }
107 return swiz;
108 }
109
110 static inline GLuint make_alpha_swizzle(struct prog_src_register src) {
111 GLuint swiz = (src.Swizzle >> 12) & 0x7;
112 if (swiz == 5) swiz++;
113 return swiz;
114 }
115
116 static inline GLuint make_strq_swizzle(struct prog_src_register src) {
117 GLuint swiz = 0x0;
118 GLuint temp = src.Swizzle;
119 int i;
120 for (i = 0; i < 4; i++) {
121 swiz += (temp & 0x3) << i*2;
122 temp >>= 3;
123 }
124 return swiz;
125 }
126
127 static int get_temp(struct r500_fragment_program *fp, int slot) {
128
129 COMPILE_STATE;
130
131 int r = slot;
132
133 while (cs->inputs[r].refcount != 0) {
134 /* Crap, taken. */
135 r++;
136 }
137
138 fp->temp_reg_offset = r - slot;
139
140 if (r >= R500_US_NUM_TEMP_REGS) {
141 ERROR("Out of hardware temps!\n");
142 return 0;
143 }
144
145 if (r > fp->max_temp_idx)
146 fp->max_temp_idx = r;
147
148 return r;
149 }
150
151 /* Borrowed verbatim from r300_fragprog since it hasn't changed. */
152 static GLuint emit_const4fv(struct r500_fragment_program *fp,
153 const GLfloat * cp)
154 {
155 GLuint reg = 0x0;
156 int index;
157
158 for (index = 0; index < fp->const_nr; ++index) {
159 if (fp->constant[index] == cp)
160 break;
161 }
162
163 if (index >= fp->const_nr) {
164 if (index >= R500_US_NUM_CONST_REGS) {
165 ERROR("Out of hw constants!\n");
166 return reg;
167 }
168
169 fp->const_nr++;
170 fp->constant[index] = cp;
171 }
172
173 reg = index | REG_CONSTANT;
174 return reg;
175 }
176
177 static GLuint make_src(struct r500_fragment_program *fp, struct prog_src_register src) {
178 COMPILE_STATE;
179 GLuint reg;
180 switch (src.File) {
181 case PROGRAM_TEMPORARY:
182 reg = src.Index + fp->temp_reg_offset;
183 break;
184 case PROGRAM_INPUT:
185 reg = cs->inputs[src.Index].reg;
186 break;
187 case PROGRAM_STATE_VAR:
188 case PROGRAM_NAMED_PARAM:
189 case PROGRAM_CONSTANT:
190 reg = emit_const4fv(fp, fp->mesa_program.Base.Parameters->
191 ParameterValues[src.Index]);
192 break;
193 default:
194 ERROR("Can't handle src.File %x\n", src.File);
195 reg = 0x0;
196 break;
197 }
198 return reg;
199 }
200
201 static GLuint make_dest(struct r500_fragment_program *fp, struct prog_dst_register dest) {
202 GLuint reg;
203 switch (dest.File) {
204 case PROGRAM_TEMPORARY:
205 reg = dest.Index + fp->temp_reg_offset;
206 break;
207 case PROGRAM_OUTPUT:
208 /* Eventually we may need to handle multiple
209 * rendering targets... */
210 reg = dest.Index;
211 break;
212 default:
213 ERROR("Can't handle dest.File %x\n", dest.File);
214 reg = 0x0;
215 break;
216 }
217 return reg;
218 }
219
220 static void emit_tex(struct r500_fragment_program *fp,
221 struct prog_instruction *fpi, int opcode, int dest, int counter)
222 {
223 int hwsrc, hwdest;
224 GLuint mask;
225
226 mask = fpi->DstReg.WriteMask << 11;
227 hwsrc = make_src(fp, fpi->SrcReg[0]);
228
229 fp->inst[counter].inst0 = R500_INST_TYPE_TEX | mask
230 | R500_INST_TEX_SEM_WAIT;
231
232 fp->inst[counter].inst1 = fpi->TexSrcUnit
233 | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
234 switch (opcode) {
235 case OPCODE_TEX:
236 fp->inst[counter].inst1 |= R500_TEX_INST_LD;
237 break;
238 case OPCODE_TXB:
239 fp->inst[counter].inst1 |= R500_TEX_INST_LODBIAS;
240 break;
241 case OPCODE_TXP:
242 fp->inst[counter].inst1 |= R500_TEX_INST_PROJ;
243 break;
244 default:
245 ERROR("emit_tex can't handle opcode %x\n", opcode);
246 }
247
248 fp->inst[counter].inst2 = R500_TEX_SRC_ADDR(hwsrc)
249 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
250 | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G
251 | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A
252 | R500_TEX_DST_ADDR(dest)
253 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
254 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
255
256
257
258 fp->inst[counter].inst3 = 0x0;
259 fp->inst[counter].inst4 = 0x0;
260 fp->inst[counter].inst5 = 0x0;
261 }
262
263 static void dumb_shader(struct r500_fragment_program *fp)
264 {
265 fp->inst[0].inst0 = R500_INST_TYPE_TEX
266 | R500_INST_TEX_SEM_WAIT
267 | R500_INST_RGB_WMASK_R
268 | R500_INST_RGB_WMASK_G
269 | R500_INST_RGB_WMASK_B
270 | R500_INST_ALPHA_WMASK
271 | R500_INST_RGB_CLAMP
272 | R500_INST_ALPHA_CLAMP;
273 fp->inst[0].inst1 = R500_TEX_ID(0)
274 | R500_TEX_INST_LD
275 | R500_TEX_SEM_ACQUIRE
276 | R500_TEX_IGNORE_UNCOVERED;
277 fp->inst[0].inst2 = R500_TEX_SRC_ADDR(0)
278 | R500_TEX_SRC_S_SWIZ_R
279 | R500_TEX_SRC_T_SWIZ_G
280 | R500_TEX_DST_ADDR(0)
281 | R500_TEX_DST_R_SWIZ_R
282 | R500_TEX_DST_G_SWIZ_G
283 | R500_TEX_DST_B_SWIZ_B
284 | R500_TEX_DST_A_SWIZ_A;
285 fp->inst[0].inst3 = R500_DX_ADDR(0)
286 | R500_DX_S_SWIZ_R
287 | R500_DX_T_SWIZ_R
288 | R500_DX_R_SWIZ_R
289 | R500_DX_Q_SWIZ_R
290 | R500_DY_ADDR(0)
291 | R500_DY_S_SWIZ_R
292 | R500_DY_T_SWIZ_R
293 | R500_DY_R_SWIZ_R
294 | R500_DY_Q_SWIZ_R;
295 fp->inst[0].inst4 = 0x0;
296 fp->inst[0].inst5 = 0x0;
297
298 fp->inst[1].inst0 = R500_INST_TYPE_OUT |
299 R500_INST_TEX_SEM_WAIT |
300 R500_INST_LAST |
301 R500_INST_RGB_OMASK_R |
302 R500_INST_RGB_OMASK_G |
303 R500_INST_RGB_OMASK_B |
304 R500_INST_ALPHA_OMASK;
305 fp->inst[1].inst1 = R500_RGB_ADDR0(0) |
306 R500_RGB_ADDR1(0) |
307 R500_RGB_ADDR1_CONST |
308 R500_RGB_ADDR2(0) |
309 R500_RGB_ADDR2_CONST |
310 R500_RGB_SRCP_OP_1_MINUS_2RGB0;
311 fp->inst[1].inst2 = R500_ALPHA_ADDR0(0) |
312 R500_ALPHA_ADDR1(0) |
313 R500_ALPHA_ADDR1_CONST |
314 R500_ALPHA_ADDR2(0) |
315 R500_ALPHA_ADDR2_CONST |
316 R500_ALPHA_SRCP_OP_1_MINUS_2A0;
317 fp->inst[1].inst3 = R500_ALU_RGB_SEL_A_SRC0 |
318 R500_ALU_RGB_R_SWIZ_A_R |
319 R500_ALU_RGB_G_SWIZ_A_G |
320 R500_ALU_RGB_B_SWIZ_A_B |
321 R500_ALU_RGB_SEL_B_SRC0 |
322 R500_ALU_RGB_R_SWIZ_B_1 |
323 R500_ALU_RGB_B_SWIZ_B_1 |
324 R500_ALU_RGB_G_SWIZ_B_1;
325 fp->inst[1].inst4 = R500_ALPHA_OP_MAD |
326 R500_ALPHA_SWIZ_A_A |
327 R500_ALPHA_SWIZ_B_1;
328 fp->inst[1].inst5 = R500_ALU_RGBA_OP_MAD |
329 R500_ALU_RGBA_R_SWIZ_0 |
330 R500_ALU_RGBA_G_SWIZ_0 |
331 R500_ALU_RGBA_B_SWIZ_0 |
332 R500_ALU_RGBA_A_SWIZ_0;
333
334 fp->cs->nrslots = 2;
335 fp->translated = GL_TRUE;
336 }
337
338 /* static void emit_alu(struct r500_fragment_program *fp) {
339 * } */
340
341 static void emit_mov(struct r500_fragment_program *fp, int counter, struct prog_src_register src, GLuint dest) {
342 /* The r3xx shader uses MAD to implement MOV. We are using CMP, since
343 * it is technically more accurate and recommended by ATI/AMD. */
344 GLuint src_reg = make_src(fp, src);
345 fp->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT;
346 fp->inst[counter].inst1 = R500_RGB_ADDR0(src_reg);
347 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src_reg);
348 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
349 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(src))
350 | R500_ALU_RGB_SEL_B_SRC0
351 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(src))
352 | R500_ALU_RGB_OMOD_DISABLE;
353 fp->inst[counter].inst4 = R500_ALPHA_OP_CMP
354 | R500_ALPHA_ADDRD(dest)
355 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(src))
356 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(src))
357 | R500_ALPHA_OMOD_DISABLE;
358 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP
359 | R500_ALU_RGBA_ADDRD(dest)
360 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
361 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
362 }
363
364 static GLboolean parse_program(struct r500_fragment_program *fp)
365 {
366 struct gl_fragment_program *mp = &fp->mesa_program;
367 const struct prog_instruction *inst = mp->Base.Instructions;
368 struct prog_instruction *fpi;
369 GLuint src[3], dest, temp[2];
370 int flags, mask, counter = 0;
371
372 if (!inst || inst[0].Opcode == OPCODE_END) {
373 ERROR("The program is empty!\n");
374 return GL_FALSE;
375 }
376
377 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
378
379 if (fpi->Opcode != OPCODE_KIL) {
380 dest = make_dest(fp, fpi->DstReg);
381 mask = fpi->DstReg.WriteMask << 11;
382 }
383
384 switch (fpi->Opcode) {
385 case OPCODE_ABS:
386 emit_mov(fp, counter, fpi->SrcReg[0], dest);
387 fp->inst[counter].inst0 |= mask;
388 fp->inst[counter].inst3 |= R500_ALU_RGB_MOD_A_ABS
389 | R500_ALU_RGB_MOD_B_ABS;
390 fp->inst[counter].inst4 |= R500_ALPHA_MOD_A_ABS
391 | R500_ALPHA_MOD_B_ABS;
392 break;
393 case OPCODE_ADD:
394 src[0] = make_src(fp, fpi->SrcReg[0]);
395 src[1] = make_src(fp, fpi->SrcReg[1]);
396 /* Variation on MAD: 1*src0+src1 */
397 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
398 | mask;
399 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
400 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(0);
401 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
402 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(0);
403 fp->inst[counter].inst3 = /* 1 */
404 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
405 | R500_ALU_RGB_SEL_B_SRC0 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
406 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
407 | R500_ALPHA_ADDRD(dest)
408 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
409 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
410 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
411 | R500_ALU_RGBA_ADDRD(dest)
412 | R500_ALU_RGBA_SEL_C_SRC1
413 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
414 | R500_ALU_RGBA_ALPHA_SEL_C_SRC1
415 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]));
416 break;
417 case OPCODE_DP3:
418 src[0] = make_src(fp, fpi->SrcReg[0]);
419 src[1] = make_src(fp, fpi->SrcReg[1]);
420 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
421 | R500_INST_TEX_SEM_WAIT | mask;
422 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
423 | R500_RGB_ADDR1(src[1]);
424 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
425 | R500_ALPHA_ADDR1(src[1]);
426 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
427 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
428 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
429 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
430 | R500_ALPHA_ADDRD(dest)
431 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
432 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
433 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP3
434 | R500_ALU_RGBA_ADDRD(dest);
435 break;
436 case OPCODE_DP4:
437 src[0] = make_src(fp, fpi->SrcReg[0]);
438 src[1] = make_src(fp, fpi->SrcReg[1]);
439 /* Based on DP3 */
440 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
441 | R500_INST_TEX_SEM_WAIT | mask;
442 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
443 | R500_RGB_ADDR1(src[1]);
444 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
445 | R500_ALPHA_ADDR1(src[1]);
446 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
447 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
448 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
449 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
450 | R500_ALPHA_ADDRD(dest)
451 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
452 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
453 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4
454 | R500_ALU_RGBA_ADDRD(dest);
455 break;
456 case OPCODE_MAD:
457 src[0] = make_src(fp, fpi->SrcReg[0]);
458 src[1] = make_src(fp, fpi->SrcReg[1]);
459 src[2] = make_src(fp, fpi->SrcReg[2]);
460 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
461 | mask;
462 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
463 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
464 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
465 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
466 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
467 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
468 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
469 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
470 | R500_ALPHA_ADDRD(dest)
471 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
472 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
473 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
474 | R500_ALU_RGBA_ADDRD(dest)
475 | R500_ALU_RGBA_SEL_C_SRC2
476 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
477 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
478 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
479 break;
480 case OPCODE_MAX:
481 src[0] = make_src(fp, fpi->SrcReg[0]);
482 src[1] = make_src(fp, fpi->SrcReg[0]);
483 fp->inst[counter].inst0 = R500_INST_TYPE_ALU | mask;
484 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
485 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
486 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
487 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
488 | R500_ALU_RGB_SEL_B_SRC1
489 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
490 fp->inst[counter].inst4 = R500_ALPHA_OP_MAX
491 | R500_ALPHA_ADDRD(dest)
492 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
493 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
494 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX
495 | R500_ALU_RGBA_ADDRD(dest);
496 break;
497 case OPCODE_MIN:
498 src[0] = make_src(fp, fpi->SrcReg[0]);
499 src[1] = make_src(fp, fpi->SrcReg[0]);
500 fp->inst[counter].inst0 = R500_INST_TYPE_ALU | mask;
501 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
502 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
503 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
504 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
505 | R500_ALU_RGB_SEL_B_SRC1
506 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
507 fp->inst[counter].inst4 = R500_ALPHA_OP_MIN
508 | R500_ALPHA_ADDRD(dest)
509 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
510 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
511 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MIN
512 | R500_ALU_RGBA_ADDRD(dest);
513 break;
514 case OPCODE_MOV:
515 emit_mov(fp, counter, fpi->SrcReg[0], dest);
516 fp->inst[counter].inst0 |= mask;
517 break;
518 case OPCODE_MUL:
519 src[0] = make_src(fp, fpi->SrcReg[0]);
520 src[1] = make_src(fp, fpi->SrcReg[1]);
521 /* Variation on MAD: src0*src1+0 */
522 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
523 | R500_INST_TEX_SEM_WAIT | mask;
524 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
525 | R500_RGB_ADDR1(src[1]);
526 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
527 | R500_ALPHA_ADDR1(src[1]);
528 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
529 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
530 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
531 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
532 | R500_ALPHA_ADDRD(dest)
533 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
534 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
535 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
536 | R500_ALU_RGBA_ADDRD(dest)
537 // | R500_ALU_RGBA_SEL_C_SRC2
538 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
539 // | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
540 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
541 break;
542 case OPCODE_SUB:
543 src[0] = make_src(fp, fpi->SrcReg[0]);
544 src[1] = make_src(fp, fpi->SrcReg[1]);
545 /* Variation on MAD: 1*src0-src1 */
546 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
547 | mask;
548 fp->inst[counter].inst1 = R500_RGB_ADDR1(src[0])
549 | R500_RGB_ADDR2(src[1]);
550 fp->inst[counter].inst2 = R500_ALPHA_ADDR1(src[0])
551 | R500_ALPHA_ADDR2(src[1]);
552 fp->inst[counter].inst3 = /* 1 */
553 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
554 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
555 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
556 | R500_ALPHA_ADDRD(dest)
557 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
558 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
559 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
560 | R500_ALU_RGBA_ADDRD(dest)
561 | R500_ALU_RGBA_SEL_C_SRC2
562 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
563 | R500_ALU_RGBA_MOD_C_NEG
564 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
565 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]))
566 | R500_ALU_RGBA_ALPHA_MOD_C_NEG;
567 break;
568 case OPCODE_TEX:
569 emit_tex(fp, fpi, OPCODE_TEX, dest, counter);
570 break;
571 case OPCODE_TXB:
572 emit_tex(fp, fpi, OPCODE_TXB, dest, counter);
573 break;
574 case OPCODE_TXP:
575 emit_tex(fp, fpi, OPCODE_TXP, dest, counter);
576 break;
577 default:
578 ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
579 break;
580 }
581
582 /* Finishing touches */
583 if (fpi->SaturateMode == SATURATE_ZERO_ONE) {
584 fp->inst[counter].inst0 |= R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP;
585 }
586 if (fpi->DstReg.File == PROGRAM_OUTPUT) {
587 fp->inst[counter].inst0 |= R500_INST_TYPE_OUT
588 | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G
589 | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK;
590 }
591
592 counter++;
593
594 if (fp->error)
595 return GL_FALSE;
596
597 }
598
599 /* Finish him! (If it's an ALU/OUT instruction...) */
600 if ((fp->inst[counter].inst0 & 0x3) ^ 0x2) {
601 fp->inst[counter].inst0 |= R500_INST_TYPE_OUT
602 | R500_INST_TEX_SEM_WAIT | R500_INST_LAST;
603 } else {
604 /* We still need to put an output inst, right? */
605 counter++;
606 fp->inst[counter].inst0 = R500_INST_TYPE_OUT
607 | R500_INST_TEX_SEM_WAIT | R500_INST_LAST
608 | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G
609 | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK;
610 fp->inst[counter].inst1 = R500_RGB_ADDR0(dest);
611 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(dest);
612 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
613 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB)
614 | R500_ALU_RGB_SEL_B_SRC0
615 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE);
616 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
617 | R500_ALPHA_ADDRD(0)
618 | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SEL_B_SRC0
619 | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1;
620 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
621 | R500_ALU_RGBA_ADDRD(0)
622 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
623 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
624 }
625
626 fp->cs->nrslots = counter;
627
628 fp->max_temp_idx++;
629
630 return GL_TRUE;
631 }
632
633 static void init_program(r300ContextPtr r300, struct r500_fragment_program *fp)
634 {
635 struct r300_pfs_compile_state *cs = NULL;
636 struct gl_fragment_program *mp = &fp->mesa_program;
637 struct prog_instruction *fpi;
638 GLuint InputsRead = mp->Base.InputsRead;
639 GLuint temps_used = 0; /* for fp->temps[] */
640 int i, j;
641
642 /* New compile, reset tracking data */
643 fp->optimization =
644 driQueryOptioni(&r300->radeon.optionCache, "fp_optimization");
645 fp->translated = GL_FALSE;
646 fp->error = GL_FALSE;
647 fp->cs = cs = &(R300_CONTEXT(fp->ctx)->state.pfs_compile);
648 fp->cur_node = 0;
649 fp->first_node_has_tex = 0;
650 fp->const_nr = 0;
651 /* Size of pixel stack, plus 1. */
652 fp->max_temp_idx = 1;
653 /* Temp register offset. */
654 fp->temp_reg_offset = 0;
655 fp->node[0].alu_end = -1;
656 fp->node[0].tex_end = -1;
657
658 _mesa_memset(cs, 0, sizeof(*fp->cs));
659 for (i = 0; i < PFS_MAX_ALU_INST; i++) {
660 for (j = 0; j < 3; j++) {
661 cs->slot[i].vsrc[j] = SRC_CONST;
662 cs->slot[i].ssrc[j] = SRC_CONST;
663 }
664 }
665
666 /* Work out what temps the Mesa inputs correspond to, this must match
667 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
668 * configures itself based on the fragprog's InputsRead
669 *
670 * NOTE: this depends on get_hw_temp() allocating registers in order,
671 * starting from register 0, so we're just going to do that instead.
672 */
673
674 /* Texcoords come first */
675 for (i = 0; i < fp->ctx->Const.MaxTextureUnits; i++) {
676 if (InputsRead & (FRAG_BIT_TEX0 << i)) {
677 cs->inputs[FRAG_ATTRIB_TEX0 + i].refcount = 0;
678 cs->inputs[FRAG_ATTRIB_TEX0 + i].reg =
679 fp->temp_reg_offset;
680 fp->temp_reg_offset++;
681 }
682 }
683 InputsRead &= ~FRAG_BITS_TEX_ANY;
684
685 /* fragment position treated as a texcoord */
686 if (InputsRead & FRAG_BIT_WPOS) {
687 cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0;
688 cs->inputs[FRAG_ATTRIB_WPOS].reg =
689 fp->temp_reg_offset;
690 fp->temp_reg_offset++;
691 }
692 InputsRead &= ~FRAG_BIT_WPOS;
693
694 /* Then primary colour */
695 if (InputsRead & FRAG_BIT_COL0) {
696 cs->inputs[FRAG_ATTRIB_COL0].refcount = 0;
697 cs->inputs[FRAG_ATTRIB_COL0].reg =
698 fp->temp_reg_offset;
699 fp->temp_reg_offset++;
700 }
701 InputsRead &= ~FRAG_BIT_COL0;
702
703 /* Secondary color */
704 if (InputsRead & FRAG_BIT_COL1) {
705 cs->inputs[FRAG_ATTRIB_COL1].refcount = 0;
706 cs->inputs[FRAG_ATTRIB_COL1].reg =
707 fp->temp_reg_offset;
708 fp->temp_reg_offset++;
709 }
710 InputsRead &= ~FRAG_BIT_COL1;
711
712 /* Anything else */
713 if (InputsRead) {
714 WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead);
715 /* force read from hwreg 0 for now */
716 for (i = 0; i < 32; i++)
717 if (InputsRead & (1 << i))
718 cs->inputs[i].reg = 0;
719 }
720
721 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
722 * That way, we can free up the reg when it's no longer needed
723 */
724 if (!mp->Base.Instructions) {
725 ERROR("No instructions found in program, going to go die now.\n");
726 return;
727 }
728
729 #if 0
730 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
731 int idx;
732 for (i = 0; i < 3; i++) {
733 idx = fpi->SrcReg[i].Index;
734 if (fpi->SrcReg[i].File == PROGRAM_INPUT) {
735 cs->inputs[idx].refcount++;
736 if (fp->max_temp_idx < idx)
737 fp->max_temp_idx = idx;
738 }
739 }
740 }
741 #endif
742
743 fp->max_temp_idx = fp->temp_reg_offset + 1;
744
745 cs->temp_in_use = temps_used;
746 }
747
748 static void update_params(struct r500_fragment_program *fp)
749 {
750 struct gl_fragment_program *mp = &fp->mesa_program;
751
752 /* Ask Mesa nicely to fill in ParameterValues for us */
753 if (mp->Base.Parameters)
754 _mesa_load_state_parameters(fp->ctx, mp->Base.Parameters);
755 }
756
757 void r500TranslateFragmentShader(r300ContextPtr r300,
758 struct r500_fragment_program *fp)
759 {
760
761 struct r300_pfs_compile_state *cs = NULL;
762
763 if (!fp->translated) {
764
765 /* I need to see what I'm working with! */
766 fprintf(stderr, "Mesa program:\n");
767 fprintf(stderr, "-------------\n");
768 _mesa_print_program(&fp->mesa_program.Base);
769 fflush(stdout);
770
771 init_program(r300, fp);
772 cs = fp->cs;
773
774 if (parse_program(fp) == GL_FALSE) {
775 ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n");
776 dumb_shader(fp);
777 return;
778 }
779
780 fp->translated = GL_TRUE;
781 r300UpdateStateParameters(fp->ctx, _NEW_PROGRAM);
782 }
783
784 update_params(fp);
785 }