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r500: mov cleanup macros
[mesa.git] / src / mesa / drivers / dri / r300 / r500_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * \file
30 *
31 * \author Ben Skeggs <darktama@iinet.net.au>
32 *
33 * \author Jerome Glisse <j.glisse@gmail.com>
34 *
35 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
36 *
37 * \todo Depth write, WPOS/FOGC inputs
38 *
39 * \todo FogOption
40 *
41 * \todo Verify results of opcodes for accuracy, I've only checked them in
42 * specific cases.
43 */
44
45 #include "glheader.h"
46 #include "macros.h"
47 #include "enums.h"
48 #include "shader/prog_instruction.h"
49 #include "shader/prog_parameter.h"
50 #include "shader/prog_print.h"
51
52 #include "r300_context.h"
53 #include "r500_fragprog.h"
54 #include "r300_reg.h"
55 #include "r300_state.h"
56
57 /*
58 * Useful macros and values
59 */
60 #define ERROR(fmt, args...) do { \
61 fprintf(stderr, "%s::%s(): " fmt "\n", \
62 __FILE__, __FUNCTION__, ##args); \
63 fp->error = GL_TRUE; \
64 } while(0)
65
66 #define COMPILE_STATE struct r300_pfs_compile_state *cs = fp->cs
67
68 /* "Register" flags */
69 #define REG_CONSTANT (1 << 8)
70 #define REG_SRC_REL (1 << 9)
71 #define REG_DEST_REL (1 << 7)
72
73 /* Swizzle tools */
74 #define R500_SWIZZLE_ZERO 4
75 #define R500_SWIZZLE_HALF 5
76 #define R500_SWIZZLE_ONE 6
77 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
78 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
79 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
80 /* Swizzles for inst2 */
81 #define MAKE_SWIZ_TEX_STRQ(x) (x << 8)
82 #define MAKE_SWIZ_TEX_RGBA(x) (x << 24)
83 /* Swizzles for inst3 */
84 #define MAKE_SWIZ_RGB_A(x) (x << 2)
85 #define MAKE_SWIZ_RGB_B(x) (x << 15)
86 /* Swizzles for inst4 */
87 #define MAKE_SWIZ_ALPHA_A(x) (x << 14)
88 #define MAKE_SWIZ_ALPHA_B(x) (x << 21)
89 /* Swizzle for inst5 */
90 #define MAKE_SWIZ_RGBA_C(x) (x << 14)
91 #define MAKE_SWIZ_ALPHA_C(x) (x << 27)
92
93 static inline GLuint make_rgb_swizzle(struct prog_src_register src) {
94 GLuint swiz = 0x0;
95 GLuint temp;
96 /* This could be optimized, but it should be plenty fast already. */
97 int i;
98 for (i = 0; i < 3; i++) {
99 temp = (src.Swizzle >> i*3) & 0x7;
100 /* Fix SWIZZLE_ONE */
101 if (temp == 5) temp++;
102 swiz += temp << i*3;
103 }
104 return swiz;
105 }
106
107 static inline GLuint make_alpha_swizzle(struct prog_src_register src) {
108 GLuint swiz = (src.Swizzle >> 12) & 0x7;
109 if (swiz == 5) swiz++;
110 return swiz;
111 }
112
113 static inline GLuint make_strq_swizzle(struct prog_src_register src) {
114 GLuint swiz = 0x0;
115 GLuint temp = src.Swizzle;
116 int i;
117 for (i = 0; i < 4; i++) {
118 swiz += (temp & 0x3) << i*2;
119 temp >>= 3;
120 }
121 return swiz;
122 }
123
124 /* Borrowed verbatim from r300_fragprog since it hasn't changed. */
125 static GLuint emit_const4fv(struct r500_fragment_program *fp,
126 const GLfloat * cp)
127 {
128 GLuint reg = 0x0;
129 int index;
130
131 for (index = 0; index < fp->const_nr; ++index) {
132 if (fp->constant[index] == cp)
133 break;
134 }
135
136 if (index >= fp->const_nr) {
137 /* TODO: This should be r5xx nums, not r300 */
138 if (index >= PFS_NUM_CONST_REGS) {
139 ERROR("Out of hw constants!\n");
140 return reg;
141 }
142
143 fp->const_nr++;
144 fp->constant[index] = cp;
145 }
146
147 reg = index | REG_CONSTANT;
148 return reg;
149 }
150
151 static GLuint make_src(struct r500_fragment_program *fp, struct prog_src_register src) {
152 GLuint reg;
153 switch (src.File) {
154 case PROGRAM_TEMPORARY:
155 reg = (src.Index << 0x1) | 0x1;
156 break;
157 case PROGRAM_INPUT:
158 /* Ugly hack needed to work around Mesa;
159 * fragments don't get loaded right otherwise! */
160 reg = 0x0;
161 break;
162 case PROGRAM_STATE_VAR:
163 case PROGRAM_NAMED_PARAM:
164 case PROGRAM_CONSTANT:
165 reg = emit_const4fv(fp, fp->mesa_program.Base.Parameters->
166 ParameterValues[src.Index]);
167 break;
168 default:
169 ERROR("Can't handle src.File %x\n", src.File);
170 reg = 0x0;
171 break;
172 }
173 return reg;
174 }
175
176 static GLuint make_dest(struct r500_fragment_program *fp, struct prog_dst_register dest) {
177 GLuint reg;
178 switch (dest.File) {
179 case PROGRAM_TEMPORARY:
180 reg = (dest.Index << 0x1) | 0x1;
181 break;
182 case PROGRAM_OUTPUT:
183 /* Eventually we may need to handle multiple
184 * rendering targets... */
185 reg = dest.Index;
186 break;
187 default:
188 ERROR("Can't handle dest.File %x\n", dest.File);
189 reg = 0x0;
190 break;
191 }
192 return reg;
193 }
194
195 static void dumb_shader(struct r500_fragment_program *fp)
196 {
197 fp->inst[0].inst0 = R500_INST_TYPE_TEX
198 | R500_INST_TEX_SEM_WAIT
199 | R500_INST_RGB_WMASK_R
200 | R500_INST_RGB_WMASK_G
201 | R500_INST_RGB_WMASK_B
202 | R500_INST_ALPHA_WMASK
203 | R500_INST_RGB_CLAMP
204 | R500_INST_ALPHA_CLAMP;
205 fp->inst[0].inst1 = R500_TEX_ID(0)
206 | R500_TEX_INST_LD
207 | R500_TEX_SEM_ACQUIRE
208 | R500_TEX_IGNORE_UNCOVERED;
209 fp->inst[0].inst2 = R500_TEX_SRC_ADDR(0)
210 | R500_TEX_SRC_S_SWIZ_R
211 | R500_TEX_SRC_T_SWIZ_G
212 | R500_TEX_DST_ADDR(0)
213 | R500_TEX_DST_R_SWIZ_R
214 | R500_TEX_DST_G_SWIZ_G
215 | R500_TEX_DST_B_SWIZ_B
216 | R500_TEX_DST_A_SWIZ_A;
217 fp->inst[0].inst3 = R500_DX_ADDR(0)
218 | R500_DX_S_SWIZ_R
219 | R500_DX_T_SWIZ_R
220 | R500_DX_R_SWIZ_R
221 | R500_DX_Q_SWIZ_R
222 | R500_DY_ADDR(0)
223 | R500_DY_S_SWIZ_R
224 | R500_DY_T_SWIZ_R
225 | R500_DY_R_SWIZ_R
226 | R500_DY_Q_SWIZ_R;
227 fp->inst[0].inst4 = 0x0;
228 fp->inst[0].inst5 = 0x0;
229
230 fp->inst[1].inst0 = R500_INST_TYPE_OUT |
231 R500_INST_TEX_SEM_WAIT |
232 R500_INST_LAST |
233 R500_INST_RGB_OMASK_R |
234 R500_INST_RGB_OMASK_G |
235 R500_INST_RGB_OMASK_B |
236 R500_INST_ALPHA_OMASK;
237 fp->inst[1].inst1 = R500_RGB_ADDR0(0) |
238 R500_RGB_ADDR1(0) |
239 R500_RGB_ADDR1_CONST |
240 R500_RGB_ADDR2(0) |
241 R500_RGB_ADDR2_CONST |
242 R500_RGB_SRCP_OP_1_MINUS_2RGB0;
243 fp->inst[1].inst2 = R500_ALPHA_ADDR0(0) |
244 R500_ALPHA_ADDR1(0) |
245 R500_ALPHA_ADDR1_CONST |
246 R500_ALPHA_ADDR2(0) |
247 R500_ALPHA_ADDR2_CONST |
248 R500_ALPHA_SRCP_OP_1_MINUS_2A0;
249 fp->inst[1].inst3 = R500_ALU_RGB_SEL_A_SRC0 |
250 R500_ALU_RGB_R_SWIZ_A_R |
251 R500_ALU_RGB_G_SWIZ_A_G |
252 R500_ALU_RGB_B_SWIZ_A_B |
253 R500_ALU_RGB_SEL_B_SRC0 |
254 R500_ALU_RGB_R_SWIZ_B_1 |
255 R500_ALU_RGB_B_SWIZ_B_1 |
256 R500_ALU_RGB_G_SWIZ_B_1;
257 fp->inst[1].inst4 = R500_ALPHA_OP_MAD |
258 R500_ALPHA_SWIZ_A_A |
259 R500_ALPHA_SWIZ_B_1;
260 fp->inst[1].inst5 = R500_ALU_RGBA_OP_MAD |
261 R500_ALU_RGBA_R_SWIZ_0 |
262 R500_ALU_RGBA_G_SWIZ_0 |
263 R500_ALU_RGBA_B_SWIZ_0 |
264 R500_ALU_RGBA_A_SWIZ_0;
265
266 fp->cs->nrslots = 2;
267 fp->translated = GL_TRUE;
268 }
269
270 static void emit_alu(struct r500_fragment_program *fp) {
271 }
272
273 static GLboolean parse_program(struct r500_fragment_program *fp)
274 {
275 struct gl_fragment_program *mp = &fp->mesa_program;
276 const struct prog_instruction *inst = mp->Base.Instructions;
277 struct prog_instruction *fpi;
278 GLuint src[3], dest, temp[2];
279 int flags, mask, counter = 0;
280
281 if (!inst || inst[0].Opcode == OPCODE_END) {
282 ERROR("The program is empty!\n");
283 return GL_FALSE;
284 }
285
286 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
287
288 if (fpi->Opcode != OPCODE_KIL) {
289 dest = make_dest(fp, fpi->DstReg);
290 mask = fpi->DstReg.WriteMask << 11;
291 }
292
293 switch (fpi->Opcode) {
294 case OPCODE_ABS:
295 src[0] = make_src(fp, fpi->SrcReg[0]);
296 /* Variation on MOV */
297 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
298 | mask;
299 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
300 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
301 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
302 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
303 | R500_ALU_RGB_MOD_A_ABS | R500_ALU_RGB_SEL_B_SRC0
304 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
305 fp->inst[counter].inst4 = R500_ALPHA_OP_MAX
306 | R500_ALPHA_ADDRD(dest)
307 | R500_ALPHA_SEL_A_SRC0
308 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) | R500_ALPHA_MOD_A_ABS
309 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
310 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX
311 | R500_ALU_RGBA_ADDRD(dest);
312 break;
313 case OPCODE_ADD:
314 src[0] = make_src(fp, fpi->SrcReg[0]);
315 src[1] = make_src(fp, fpi->SrcReg[1]);
316 /* Variation on MAD: 1*src0+src1 */
317 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
318 | mask;
319 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
320 | R500_RGB_ADDR1(src[1]);
321 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
322 | R500_ALPHA_ADDR1(src[1]);
323 fp->inst[counter].inst3 = /* 1 */
324 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
325 | R500_ALU_RGB_SEL_B_SRC0 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
326 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
327 | R500_ALPHA_ADDRD(dest)
328 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
329 | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
330 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
331 | R500_ALU_RGBA_ADDRD(dest)
332 | R500_ALU_RGBA_SEL_C_SRC1
333 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
334 | R500_ALU_RGBA_ALPHA_SEL_C_SRC1
335 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]));
336 break;
337 case OPCODE_DP3:
338 src[0] = make_src(fp, fpi->SrcReg[0]);
339 src[1] = make_src(fp, fpi->SrcReg[1]);
340 src[2] = make_src(fp, fpi->SrcReg[2]);
341 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
342 | mask;
343 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
344 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
345 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
346 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
347 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
348 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
349 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
350 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
351 | R500_ALPHA_ADDRD(dest)
352 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
353 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
354 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP3
355 | R500_ALU_RGBA_ADDRD(dest)
356 | R500_ALU_RGBA_SEL_C_SRC2
357 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
358 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
359 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
360 break;
361 case OPCODE_DP4:
362 src[0] = make_src(fp, fpi->SrcReg[0]);
363 src[1] = make_src(fp, fpi->SrcReg[1]);
364 src[2] = make_src(fp, fpi->SrcReg[2]);
365 /* Based on DP3 */
366 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
367 | mask;
368 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
369 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
370 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
371 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
372 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
373 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
374 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
375 fp->inst[counter].inst4 = R500_ALPHA_OP_DP
376 | R500_ALPHA_ADDRD(dest)
377 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
378 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
379 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4
380 | R500_ALU_RGBA_ADDRD(dest)
381 | R500_ALU_RGBA_SEL_C_SRC2
382 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
383 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
384 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
385 break;
386 case OPCODE_MAD:
387 src[0] = make_src(fp, fpi->SrcReg[0]);
388 src[1] = make_src(fp, fpi->SrcReg[1]);
389 src[2] = make_src(fp, fpi->SrcReg[2]);
390 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
391 | mask;
392 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
393 | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[2]);
394 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
395 | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[2]);
396 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
397 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
398 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
399 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
400 | R500_ALPHA_ADDRD(dest)
401 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
402 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
403 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
404 | R500_ALU_RGBA_ADDRD(dest)
405 | R500_ALU_RGBA_SEL_C_SRC2
406 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2]))
407 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
408 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2]));
409 break;
410 case OPCODE_MAX:
411 src[0] = make_src(fp, fpi->SrcReg[0]);
412 src[1] = make_src(fp, fpi->SrcReg[0]);
413 fp->inst[counter].inst0 = R500_INST_TYPE_ALU | mask;
414 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
415 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
416 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
417 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
418 | R500_ALU_RGB_SEL_B_SRC1
419 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
420 fp->inst[counter].inst4 = R500_ALPHA_OP_MAX
421 | R500_ALPHA_ADDRD(dest)
422 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
423 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
424 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX
425 | R500_ALU_RGBA_ADDRD(dest);
426 break;
427 case OPCODE_MIN:
428 src[0] = make_src(fp, fpi->SrcReg[0]);
429 src[1] = make_src(fp, fpi->SrcReg[0]);
430 fp->inst[counter].inst0 = R500_INST_TYPE_ALU | mask;
431 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]);
432 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]);
433 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
434 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
435 | R500_ALU_RGB_SEL_B_SRC1
436 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
437 fp->inst[counter].inst4 = R500_ALPHA_OP_MIN
438 | R500_ALPHA_ADDRD(dest)
439 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
440 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
441 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MIN
442 | R500_ALU_RGBA_ADDRD(dest);
443 break;
444 case OPCODE_MOV:
445 src[0] = make_src(fp, fpi->SrcReg[0]);
446
447 /* changed to use MAD - not sure if we
448 ever have negative things which max will fail on */
449 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
450 | mask;
451 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
452 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
453 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
454 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB)
455 | R500_ALU_RGB_SEL_B_SRC0
456 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE);
457 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
458 | R500_ALPHA_ADDRD(dest)
459 | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SEL_B_SRC0
460 | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1;
461
462 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
463 | R500_ALU_RGBA_ADDRD(dest)
464 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
465 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
466 break;
467 case OPCODE_MUL:
468 src[0] = make_src(fp, fpi->SrcReg[0]);
469 src[1] = make_src(fp, fpi->SrcReg[1]);
470 /* Variation on MAD: src0*src1+0 */
471 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
472 | mask;
473 fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0])
474 | R500_RGB_ADDR1(src[1]);
475 fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0])
476 | R500_ALPHA_ADDR1(src[1]);
477 fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
478 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]))
479 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1]));
480 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
481 | R500_ALPHA_ADDRD(dest)
482 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]))
483 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1]));
484 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
485 | R500_ALU_RGBA_ADDRD(dest)
486 // | R500_ALU_RGBA_SEL_C_SRC2
487 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO)
488 // | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
489 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
490 break;
491 case OPCODE_SUB:
492 src[0] = make_src(fp, fpi->SrcReg[0]);
493 src[1] = make_src(fp, fpi->SrcReg[1]);
494 /* Variation on MAD: 1*src0-src1 */
495 fp->inst[counter].inst0 = R500_INST_TYPE_ALU
496 | mask;
497 fp->inst[counter].inst1 = R500_RGB_ADDR1(src[0])
498 | R500_RGB_ADDR2(src[1]);
499 fp->inst[counter].inst2 = R500_ALPHA_ADDR1(src[0])
500 | R500_ALPHA_ADDR2(src[1]);
501 fp->inst[counter].inst3 = /* 1 */
502 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE)
503 | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0]));
504 fp->inst[counter].inst4 = R500_ALPHA_OP_MAD
505 | R500_ALPHA_ADDRD(dest)
506 | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE)
507 | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0]));
508 fp->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD
509 | R500_ALU_RGBA_ADDRD(dest)
510 | R500_ALU_RGBA_SEL_C_SRC2
511 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1]))
512 | R500_ALU_RGBA_MOD_C_NEG
513 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
514 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1]))
515 | R500_ALU_RGBA_ALPHA_MOD_C_NEG;
516 break;
517 case OPCODE_TEX:
518 src[0] = make_src(fp, fpi->SrcReg[0]);
519 fp->inst[counter].inst0 = R500_INST_TYPE_TEX | mask
520 | R500_INST_TEX_SEM_WAIT;
521 fp->inst[counter].inst1 = fpi->TexSrcUnit
522 | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
523 fp->inst[counter].inst2 = R500_TEX_SRC_ADDR(src[0])
524 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
525 | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G
526 | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A
527 | R500_TEX_DST_ADDR(dest)
528 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
529 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
530 fp->inst[counter].inst3 = 0x0;
531 fp->inst[counter].inst4 = 0x0;
532 fp->inst[counter].inst5 = 0x0;
533 break;
534 case OPCODE_TXP:
535 src[0] = make_src(fp, fpi->SrcReg[0]);
536 fp->inst[counter].inst0 = R500_INST_TYPE_TEX | mask;
537 fp->inst[counter].inst1 = fpi->TexSrcUnit
538 | R500_TEX_INST_PROJ | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
539 fp->inst[counter].inst2 = R500_TEX_SRC_ADDR(src[0])
540 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
541 | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G
542 | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A
543 | R500_TEX_DST_ADDR(dest)
544 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
545 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
546 fp->inst[counter].inst3 = 0x0;
547 fp->inst[counter].inst4 = 0x0;
548 fp->inst[counter].inst5 = 0x0;
549 break;
550 default:
551 ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
552 break;
553 }
554
555 /* Finishing touches */
556 if (fpi->SaturateMode == SATURATE_ZERO_ONE) {
557 fp->inst[counter].inst0 |= R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP;
558 }
559 if (fpi->DstReg.File == PROGRAM_OUTPUT) {
560 fp->inst[counter].inst0 |= R500_INST_TYPE_OUT
561 | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G
562 | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK;
563 }
564
565 counter++;
566
567 if (fp->error)
568 return GL_FALSE;
569
570 }
571
572 fp->cs->nrslots = counter;
573
574 /* Finish him! (If it's an output instruction...)
575 * Yes, I know it's ugly... */
576 if ((fp->inst[counter].inst0 & 0x3) ^ 0x2) {
577 fp->inst[counter].inst0 |= R500_INST_TYPE_OUT
578 | R500_INST_TEX_SEM_WAIT | R500_INST_LAST;
579 }
580
581 return GL_TRUE;
582 }
583
584 static void init_program(r300ContextPtr r300, struct r500_fragment_program *fp)
585 {
586 struct r300_pfs_compile_state *cs = NULL;
587 struct gl_fragment_program *mp = &fp->mesa_program;
588 struct prog_instruction *fpi;
589 GLuint InputsRead = mp->Base.InputsRead;
590 GLuint temps_used = 0; /* for fp->temps[] */
591 int i, j;
592
593 /* New compile, reset tracking data */
594 fp->optimization =
595 driQueryOptioni(&r300->radeon.optionCache, "fp_optimization");
596 fp->translated = GL_FALSE;
597 fp->error = GL_FALSE;
598 fp->cs = cs = &(R300_CONTEXT(fp->ctx)->state.pfs_compile);
599 fp->cur_node = 0;
600 fp->first_node_has_tex = 0;
601 fp->const_nr = 0;
602 fp->max_temp_idx = 64;
603 fp->node[0].alu_end = -1;
604 fp->node[0].tex_end = -1;
605
606 _mesa_memset(cs, 0, sizeof(*fp->cs));
607 for (i = 0; i < PFS_MAX_ALU_INST; i++) {
608 for (j = 0; j < 3; j++) {
609 cs->slot[i].vsrc[j] = SRC_CONST;
610 cs->slot[i].ssrc[j] = SRC_CONST;
611 }
612 }
613
614 /* Work out what temps the Mesa inputs correspond to, this must match
615 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
616 * configures itself based on the fragprog's InputsRead
617 *
618 * NOTE: this depends on get_hw_temp() allocating registers in order,
619 * starting from register 0.
620 */
621
622 #if 0
623 /* Texcoords come first */
624 for (i = 0; i < fp->ctx->Const.MaxTextureUnits; i++) {
625 if (InputsRead & (FRAG_BIT_TEX0 << i)) {
626 cs->inputs[FRAG_ATTRIB_TEX0 + i].refcount = 0;
627 cs->inputs[FRAG_ATTRIB_TEX0 + i].reg =
628 get_hw_temp(fp, 0);
629 }
630 }
631 InputsRead &= ~FRAG_BITS_TEX_ANY;
632
633 /* fragment position treated as a texcoord */
634 if (InputsRead & FRAG_BIT_WPOS) {
635 cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0;
636 cs->inputs[FRAG_ATTRIB_WPOS].reg = get_hw_temp(fp, 0);
637 insert_wpos(&mp->Base);
638 }
639 InputsRead &= ~FRAG_BIT_WPOS;
640
641 /* Then primary colour */
642 if (InputsRead & FRAG_BIT_COL0) {
643 cs->inputs[FRAG_ATTRIB_COL0].refcount = 0;
644 cs->inputs[FRAG_ATTRIB_COL0].reg = get_hw_temp(fp, 0);
645 }
646 InputsRead &= ~FRAG_BIT_COL0;
647
648 /* Secondary color */
649 if (InputsRead & FRAG_BIT_COL1) {
650 cs->inputs[FRAG_ATTRIB_COL1].refcount = 0;
651 cs->inputs[FRAG_ATTRIB_COL1].reg = get_hw_temp(fp, 0);
652 }
653 InputsRead &= ~FRAG_BIT_COL1;
654
655 /* Anything else */
656 if (InputsRead) {
657 WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead);
658 /* force read from hwreg 0 for now */
659 for (i = 0; i < 32; i++)
660 if (InputsRead & (1 << i))
661 cs->inputs[i].reg = 0;
662 }
663 #endif
664
665 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
666 * That way, we can free up the reg when it's no longer needed
667 */
668 if (!mp->Base.Instructions) {
669 ERROR("No instructions found in program\n");
670 return;
671 }
672
673 for (fpi = mp->Base.Instructions; fpi->Opcode != OPCODE_END; fpi++) {
674 int idx;
675
676 for (i = 0; i < 3; i++) {
677 idx = fpi->SrcReg[i].Index;
678 switch (fpi->SrcReg[i].File) {
679 case PROGRAM_TEMPORARY:
680 if (!(temps_used & (1 << idx))) {
681 cs->temps[idx].reg = -1;
682 cs->temps[idx].refcount = 1;
683 temps_used |= (1 << idx);
684 } else
685 cs->temps[idx].refcount++;
686 break;
687 case PROGRAM_INPUT:
688 cs->inputs[idx].refcount++;
689 break;
690 default:
691 break;
692 }
693 }
694
695 idx = fpi->DstReg.Index;
696 if (fpi->DstReg.File == PROGRAM_TEMPORARY) {
697 if (!(temps_used & (1 << idx))) {
698 cs->temps[idx].reg = -1;
699 cs->temps[idx].refcount = 1;
700 temps_used |= (1 << idx);
701 } else
702 cs->temps[idx].refcount++;
703 }
704 }
705 cs->temp_in_use = temps_used;
706 }
707
708 static void update_params(struct r500_fragment_program *fp)
709 {
710 struct gl_fragment_program *mp = &fp->mesa_program;
711
712 /* Ask Mesa nicely to fill in ParameterValues for us */
713 if (mp->Base.Parameters)
714 _mesa_load_state_parameters(fp->ctx, mp->Base.Parameters);
715 }
716
717 void r500TranslateFragmentShader(r300ContextPtr r300,
718 struct r500_fragment_program *fp)
719 {
720
721 struct r300_pfs_compile_state *cs = NULL;
722
723 if (!fp->translated) {
724
725 /* I need to see what I'm working with! */
726 fprintf(stderr, "Mesa program:\n");
727 fprintf(stderr, "-------------\n");
728 _mesa_print_program(&fp->mesa_program.Base);
729 fflush(stdout);
730
731 init_program(r300, fp);
732 cs = fp->cs;
733
734 if (parse_program(fp) == GL_FALSE) {
735 ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n");
736 dumb_shader(fp);
737 return;
738 }
739
740 /* Finish off */
741 fp->node[fp->cur_node].alu_end =
742 cs->nrslots - fp->node[fp->cur_node].alu_offset - 1;
743 if (fp->node[fp->cur_node].tex_end < 0)
744 fp->node[fp->cur_node].tex_end = 0;
745 fp->alu_offset = 0;
746 fp->alu_end = cs->nrslots - 1;
747 //assert(fp->node[fp->cur_node].alu_end >= 0);
748 //assert(fp->alu_end >= 0);
749
750 fp->translated = GL_TRUE;
751 r300UpdateStateParameters(fp->ctx, _NEW_PROGRAM);
752 }
753
754 update_params(fp);
755 }