2 * Copyright (C) 2005 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * \author Ben Skeggs <darktama@iinet.net.au>
33 * \author Jerome Glisse <j.glisse@gmail.com>
35 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
37 * \todo Depth write, WPOS/FOGC inputs
41 * \todo Verify results of opcodes for accuracy, I've only checked them in
48 #include "shader/prog_instruction.h"
49 #include "shader/prog_parameter.h"
50 #include "shader/prog_print.h"
52 #include "r300_context.h"
53 #include "r500_fragprog.h"
55 #include "r300_state.h"
58 * Useful macros and values
60 #define ERROR(fmt, args...) do { \
61 fprintf(stderr, "%s::%s(): " fmt "\n", \
62 __FILE__, __FUNCTION__, ##args); \
63 fp->error = GL_TRUE; \
66 #define COMPILE_STATE struct r300_pfs_compile_state *cs = fp->cs
68 #define R500_US_NUM_TEMP_REGS 128
69 #define R500_US_NUM_CONST_REGS 256
71 /* "Register" flags */
72 #define REG_CONSTANT (1 << 8)
73 #define REG_SRC_REL (1 << 9)
74 #define REG_DEST_REL (1 << 7)
77 #define R500_SWIZZLE_ZERO 4
78 #define R500_SWIZZLE_HALF 5
79 #define R500_SWIZZLE_ONE 6
80 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
81 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
82 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
83 /* Swizzles for inst2 */
84 #define MAKE_SWIZ_TEX_STRQ(x) (x << 8)
85 #define MAKE_SWIZ_TEX_RGBA(x) (x << 24)
86 /* Swizzles for inst3 */
87 #define MAKE_SWIZ_RGB_A(x) (x << 2)
88 #define MAKE_SWIZ_RGB_B(x) (x << 15)
89 /* Swizzles for inst4 */
90 #define MAKE_SWIZ_ALPHA_A(x) (x << 14)
91 #define MAKE_SWIZ_ALPHA_B(x) (x << 21)
92 /* Swizzle for inst5 */
93 #define MAKE_SWIZ_RGBA_C(x) (x << 14)
94 #define MAKE_SWIZ_ALPHA_C(x) (x << 27)
96 static inline GLuint
make_rgb_swizzle(struct prog_src_register src
) {
99 /* This could be optimized, but it should be plenty fast already. */
101 for (i
= 0; i
< 3; i
++) {
102 temp
= (src
.Swizzle
>> i
*3) & 0x7;
103 /* Fix SWIZZLE_ONE */
104 if (temp
== 5) temp
++;
110 static inline GLuint
make_alpha_swizzle(struct prog_src_register src
) {
111 GLuint swiz
= (src
.Swizzle
>> 12) & 0x7;
112 if (swiz
== 5) swiz
++;
116 static inline GLuint
make_strq_swizzle(struct prog_src_register src
) {
118 GLuint temp
= src
.Swizzle
;
120 for (i
= 0; i
< 4; i
++) {
121 swiz
+= (temp
& 0x3) << i
*2;
127 static int get_temp(struct r500_fragment_program
*fp
, int slot
) {
133 while (cs
->inputs
[r
].refcount
!= 0) {
138 fp
->temp_reg_offset
= r
- slot
;
140 if (r
>= R500_US_NUM_TEMP_REGS
) {
141 ERROR("Out of hardware temps!\n");
145 if (r
> fp
->max_temp_idx
)
146 fp
->max_temp_idx
= r
;
151 /* Borrowed verbatim from r300_fragprog since it hasn't changed. */
152 static GLuint
emit_const4fv(struct r500_fragment_program
*fp
,
158 for (index
= 0; index
< fp
->const_nr
; ++index
) {
159 if (fp
->constant
[index
] == cp
)
163 if (index
>= fp
->const_nr
) {
164 if (index
>= R500_US_NUM_CONST_REGS
) {
165 ERROR("Out of hw constants!\n");
170 fp
->constant
[index
] = cp
;
173 reg
= index
| REG_CONSTANT
;
177 static GLuint
make_src(struct r500_fragment_program
*fp
, struct prog_src_register src
) {
181 case PROGRAM_TEMPORARY
:
182 reg
= src
.Index
+ fp
->temp_reg_offset
;
185 reg
= cs
->inputs
[src
.Index
].reg
;
187 case PROGRAM_STATE_VAR
:
188 case PROGRAM_NAMED_PARAM
:
189 case PROGRAM_CONSTANT
:
190 reg
= emit_const4fv(fp
, fp
->mesa_program
.Base
.Parameters
->
191 ParameterValues
[src
.Index
]);
194 ERROR("Can't handle src.File %x\n", src
.File
);
201 static GLuint
make_dest(struct r500_fragment_program
*fp
, struct prog_dst_register dest
) {
204 case PROGRAM_TEMPORARY
:
205 reg
= dest
.Index
+ fp
->temp_reg_offset
;
208 /* Eventually we may need to handle multiple
209 * rendering targets... */
213 ERROR("Can't handle dest.File %x\n", dest
.File
);
220 static void emit_tex(struct r500_fragment_program
*fp
,
221 struct prog_instruction
*fpi
, int opcode
, int dest
, int counter
)
226 mask
= fpi
->DstReg
.WriteMask
<< 11;
227 hwsrc
= make_src(fp
, fpi
->SrcReg
[0]);
229 fp
->inst
[counter
].inst0
= R500_INST_TYPE_TEX
| mask
230 | R500_INST_TEX_SEM_WAIT
;
232 fp
->inst
[counter
].inst1
= R500_TEX_ID(fpi
->TexSrcUnit
)
233 | R500_TEX_SEM_ACQUIRE
| R500_TEX_IGNORE_UNCOVERED
;
235 if (fpi
->TexSrcTarget
== TEXTURE_RECT_INDEX
)
236 fp
->inst
[counter
].inst1
|= R500_TEX_UNSCALED
;
240 fp
->inst
[counter
].inst1
|= R500_TEX_INST_LD
;
243 fp
->inst
[counter
].inst1
|= R500_TEX_INST_LODBIAS
;
246 fp
->inst
[counter
].inst1
|= R500_TEX_INST_PROJ
;
249 ERROR("emit_tex can't handle opcode %x\n", opcode
);
252 fp
->inst
[counter
].inst2
= R500_TEX_SRC_ADDR(hwsrc
)
253 /* | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) */
254 | R500_TEX_SRC_S_SWIZ_R
| R500_TEX_SRC_T_SWIZ_G
255 | R500_TEX_SRC_R_SWIZ_B
| R500_TEX_SRC_Q_SWIZ_A
256 | R500_TEX_DST_ADDR(dest
)
257 | R500_TEX_DST_R_SWIZ_R
| R500_TEX_DST_G_SWIZ_G
258 | R500_TEX_DST_B_SWIZ_B
| R500_TEX_DST_A_SWIZ_A
;
262 fp
->inst
[counter
].inst3
= 0x0;
263 fp
->inst
[counter
].inst4
= 0x0;
264 fp
->inst
[counter
].inst5
= 0x0;
267 static void dumb_shader(struct r500_fragment_program
*fp
)
269 fp
->inst
[0].inst0
= R500_INST_TYPE_TEX
270 | R500_INST_TEX_SEM_WAIT
271 | R500_INST_RGB_WMASK_R
272 | R500_INST_RGB_WMASK_G
273 | R500_INST_RGB_WMASK_B
274 | R500_INST_ALPHA_WMASK
275 | R500_INST_RGB_CLAMP
276 | R500_INST_ALPHA_CLAMP
;
277 fp
->inst
[0].inst1
= R500_TEX_ID(0)
279 | R500_TEX_SEM_ACQUIRE
280 | R500_TEX_IGNORE_UNCOVERED
;
281 fp
->inst
[0].inst2
= R500_TEX_SRC_ADDR(0)
282 | R500_TEX_SRC_S_SWIZ_R
283 | R500_TEX_SRC_T_SWIZ_G
284 | R500_TEX_DST_ADDR(0)
285 | R500_TEX_DST_R_SWIZ_R
286 | R500_TEX_DST_G_SWIZ_G
287 | R500_TEX_DST_B_SWIZ_B
288 | R500_TEX_DST_A_SWIZ_A
;
289 fp
->inst
[0].inst3
= R500_DX_ADDR(0)
299 fp
->inst
[0].inst4
= 0x0;
300 fp
->inst
[0].inst5
= 0x0;
302 fp
->inst
[1].inst0
= R500_INST_TYPE_OUT
|
303 R500_INST_TEX_SEM_WAIT
|
305 R500_INST_RGB_OMASK_R
|
306 R500_INST_RGB_OMASK_G
|
307 R500_INST_RGB_OMASK_B
|
308 R500_INST_ALPHA_OMASK
;
309 fp
->inst
[1].inst1
= R500_RGB_ADDR0(0) |
311 R500_RGB_ADDR1_CONST
|
313 R500_RGB_ADDR2_CONST
|
314 R500_RGB_SRCP_OP_1_MINUS_2RGB0
;
315 fp
->inst
[1].inst2
= R500_ALPHA_ADDR0(0) |
316 R500_ALPHA_ADDR1(0) |
317 R500_ALPHA_ADDR1_CONST
|
318 R500_ALPHA_ADDR2(0) |
319 R500_ALPHA_ADDR2_CONST
|
320 R500_ALPHA_SRCP_OP_1_MINUS_2A0
;
321 fp
->inst
[1].inst3
= R500_ALU_RGB_SEL_A_SRC0
|
322 R500_ALU_RGB_R_SWIZ_A_R
|
323 R500_ALU_RGB_G_SWIZ_A_G
|
324 R500_ALU_RGB_B_SWIZ_A_B
|
325 R500_ALU_RGB_SEL_B_SRC0
|
326 R500_ALU_RGB_R_SWIZ_B_1
|
327 R500_ALU_RGB_B_SWIZ_B_1
|
328 R500_ALU_RGB_G_SWIZ_B_1
;
329 fp
->inst
[1].inst4
= R500_ALPHA_OP_MAD
|
330 R500_ALPHA_SWIZ_A_A
|
332 fp
->inst
[1].inst5
= R500_ALU_RGBA_OP_MAD
|
333 R500_ALU_RGBA_R_SWIZ_0
|
334 R500_ALU_RGBA_G_SWIZ_0
|
335 R500_ALU_RGBA_B_SWIZ_0
|
336 R500_ALU_RGBA_A_SWIZ_0
;
339 fp
->translated
= GL_TRUE
;
342 /* static void emit_alu(struct r500_fragment_program *fp) {
345 static void emit_mov(struct r500_fragment_program
*fp
, int counter
, struct prog_src_register src
, GLuint dest
) {
346 /* The r3xx shader uses MAD to implement MOV. We are using CMP, since
347 * it is technically more accurate and recommended by ATI/AMD. */
348 GLuint src_reg
= make_src(fp
, src
);
349 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| R500_INST_TEX_SEM_WAIT
;
350 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src_reg
);
351 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src_reg
);
352 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
353 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(src
))
354 | R500_ALU_RGB_SEL_B_SRC0
355 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(src
))
356 | R500_ALU_RGB_OMOD_DISABLE
;
357 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_CMP
358 | R500_ALPHA_ADDRD(dest
)
359 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(src
))
360 | R500_ALPHA_SEL_B_SRC0
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(src
))
361 | R500_ALPHA_OMOD_DISABLE
;
362 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_CMP
363 | R500_ALU_RGBA_ADDRD(dest
)
364 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
365 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
368 static GLboolean
parse_program(struct r500_fragment_program
*fp
)
370 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
371 const struct prog_instruction
*inst
= mp
->Base
.Instructions
;
372 struct prog_instruction
*fpi
;
373 GLuint src
[3], dest
, temp
[2];
374 int flags
, pixel_mask
= 0, output_mask
= 0, counter
= 0, temp_pixel_mask
= 0;
376 if (!inst
|| inst
[0].Opcode
== OPCODE_END
) {
377 ERROR("The program is empty!\n");
381 for (fpi
= mp
->Base
.Instructions
; fpi
->Opcode
!= OPCODE_END
; fpi
++) {
383 if (fpi
->Opcode
!= OPCODE_KIL
) {
384 dest
= make_dest(fp
, fpi
->DstReg
);
386 pixel_mask
= fpi
->DstReg
.WriteMask
<< 11;
387 output_mask
= fpi
->DstReg
.WriteMask
<< 14;
390 switch (fpi
->Opcode
) {
392 emit_mov(fp
, counter
, fpi
->SrcReg
[0], dest
);
393 fp
->inst
[counter
].inst0
|= pixel_mask
;
394 fp
->inst
[counter
].inst3
|= R500_ALU_RGB_MOD_A_ABS
395 | R500_ALU_RGB_MOD_B_ABS
;
396 fp
->inst
[counter
].inst4
|= R500_ALPHA_MOD_A_ABS
397 | R500_ALPHA_MOD_B_ABS
;
400 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
401 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
402 /* Variation on MAD: 1*src0+src1 */
403 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
405 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
406 | R500_RGB_ADDR1(src
[1]) | R500_RGB_ADDR2(0);
407 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
408 | R500_ALPHA_ADDR1(src
[1]) | R500_ALPHA_ADDR2(0);
409 fp
->inst
[counter
].inst3
= /* 1 */
410 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE
)
411 | R500_ALU_RGB_SEL_B_SRC0
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[0]));
412 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
413 | R500_ALPHA_ADDRD(dest
)
414 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE
)
415 | R500_ALPHA_SEL_B_SRC0
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[0]));
416 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
417 | R500_ALU_RGBA_ADDRD(dest
)
418 | R500_ALU_RGBA_SEL_C_SRC1
419 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[1]))
420 | R500_ALU_RGBA_ALPHA_SEL_C_SRC1
421 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[1]));
424 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
425 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
426 src
[2] = make_src(fp
, fpi
->SrcReg
[2]);
427 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
429 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
430 | R500_RGB_ADDR1(src
[1]) | R500_RGB_ADDR2(src
[2]);
431 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
432 | R500_ALPHA_ADDR1(src
[1]) | R500_ALPHA_ADDR2(src
[2]);
433 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
434 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
435 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
436 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_CMP
437 | R500_ALPHA_ADDRD(dest
)
438 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
439 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
440 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_CMP
441 | R500_ALU_RGBA_ADDRD(dest
)
442 | R500_ALU_RGBA_SEL_C_SRC2
443 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[2]))
444 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
445 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[2]));
448 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
449 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
450 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
451 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
452 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
453 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
454 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
455 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_COS
456 | R500_ALPHA_ADDRD(dest
)
457 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
458 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
459 | R500_ALU_RGBA_ADDRD(dest
);
462 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
463 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
464 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
465 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
466 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
467 | R500_RGB_ADDR1(src
[1]);
468 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
469 | R500_ALPHA_ADDR1(src
[1]);
470 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
471 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
472 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
473 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_DP
474 | R500_ALPHA_ADDRD(dest
)
475 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
476 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
477 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_DP3
478 | R500_ALU_RGBA_ADDRD(dest
);
481 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
482 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
484 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
485 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
486 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
487 | R500_RGB_ADDR1(src
[1]);
488 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
489 | R500_ALPHA_ADDR1(src
[1]);
490 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
491 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
492 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
493 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_DP
494 | R500_ALPHA_ADDRD(dest
)
495 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
496 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
497 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_DP4
498 | R500_ALU_RGBA_ADDRD(dest
);
501 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
502 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
503 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
504 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
505 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
506 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
507 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
508 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_EX2
509 | R500_ALPHA_ADDRD(dest
)
510 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
511 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
512 | R500_ALU_RGBA_ADDRD(dest
);
515 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
516 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
517 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
518 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
519 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
520 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
521 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
522 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_FRC
523 | R500_ALPHA_ADDRD(dest
)
524 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
525 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_FRC
526 | R500_ALU_RGBA_ADDRD(dest
);
528 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
529 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
530 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
531 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
532 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
533 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
534 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
535 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_LN2
536 | R500_ALPHA_ADDRD(dest
)
537 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
538 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
539 | R500_ALU_RGBA_ADDRD(dest
);
542 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
543 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
544 src
[2] = make_src(fp
, fpi
->SrcReg
[2]);
545 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
547 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
548 | R500_RGB_ADDR1(src
[1]) | R500_RGB_ADDR2(src
[2]);
549 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
550 | R500_ALPHA_ADDR1(src
[1]) | R500_ALPHA_ADDR2(src
[2]);
551 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
552 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
553 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
554 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
555 | R500_ALPHA_ADDRD(dest
)
556 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
557 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
558 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
559 | R500_ALU_RGBA_ADDRD(dest
)
560 | R500_ALU_RGBA_SEL_C_SRC2
561 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[2]))
562 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
563 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[2]));
566 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
567 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
568 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| pixel_mask
;
569 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]) | R500_RGB_ADDR1(src
[1]);
570 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]) | R500_ALPHA_ADDR1(src
[1]);
571 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
572 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
573 | R500_ALU_RGB_SEL_B_SRC1
574 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
575 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAX
576 | R500_ALPHA_ADDRD(dest
)
577 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
578 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
579 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAX
580 | R500_ALU_RGBA_ADDRD(dest
);
583 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
584 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
585 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| pixel_mask
;
586 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]) | R500_RGB_ADDR1(src
[1]);
587 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]) | R500_ALPHA_ADDR1(src
[1]);
588 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
589 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
590 | R500_ALU_RGB_SEL_B_SRC1
591 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
592 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MIN
593 | R500_ALPHA_ADDRD(dest
)
594 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
595 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
596 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MIN
597 | R500_ALU_RGBA_ADDRD(dest
);
600 emit_mov(fp
, counter
, fpi
->SrcReg
[0], dest
);
601 fp
->inst
[counter
].inst0
|= pixel_mask
;
604 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
605 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
606 /* Variation on MAD: src0*src1+0 */
607 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
608 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
609 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0])
610 | R500_RGB_ADDR1(src
[1]);
611 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0])
612 | R500_ALPHA_ADDR1(src
[1]);
613 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
614 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]))
615 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[1]));
616 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
617 | R500_ALPHA_ADDRD(dest
)
618 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]))
619 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[1]));
620 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
621 | R500_ALU_RGBA_ADDRD(dest
)
622 // | R500_ALU_RGBA_SEL_C_SRC2
623 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
624 // | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
625 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
628 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
629 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
630 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
631 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
632 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
633 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
634 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
635 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_RCP
636 | R500_ALPHA_ADDRD(dest
)
637 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
638 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
639 | R500_ALU_RGBA_ADDRD(dest
);
642 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
643 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
644 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
645 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
646 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
647 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
648 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
649 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_RSQ
650 | R500_ALPHA_ADDRD(dest
)
651 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
652 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
653 | R500_ALU_RGBA_ADDRD(dest
);
657 /* Do a cosine, then a sine, masking out the channels we want to protect. */
658 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
659 /* Cosine only goes in R (x) channel. */
660 temp_pixel_mask
= 0x1 << 11;
661 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
662 | R500_INST_TEX_SEM_WAIT
| temp_pixel_mask
;
663 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
664 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
665 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
666 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
667 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_COS
668 | R500_ALPHA_ADDRD(dest
)
669 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
670 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
671 | R500_ALU_RGBA_ADDRD(dest
);
673 /* Sine only goes in G (y) channel. */
674 temp_pixel_mask
= 0x2 << 11;
675 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| temp_pixel_mask
;
676 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
677 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
678 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
679 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
680 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_SIN
681 | R500_ALPHA_ADDRD(dest
)
682 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
683 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
684 | R500_ALU_RGBA_ADDRD(dest
);
686 /* Put 0 into B,A (z,w) channels. */
687 temp_pixel_mask
= 0xC << 11;
688 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
| temp_pixel_mask
;
689 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
690 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
691 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
692 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ZERO
)
693 | R500_ALU_RGB_SEL_B_SRC0
694 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ZERO
);
695 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_CMP
696 | R500_ALPHA_ADDRD(dest
)
697 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(R500_SWIZ_ZERO
)
698 | R500_ALPHA_SEL_B_SRC0
| MAKE_SWIZ_ALPHA_B(R500_SWIZ_ZERO
);
699 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_CMP
700 | R500_ALU_RGBA_ADDRD(dest
)
701 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
702 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
706 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
707 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
708 | R500_INST_TEX_SEM_WAIT
| pixel_mask
;
709 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(src
[0]);
710 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(src
[0]);
711 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
712 | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi
->SrcReg
[0]));
713 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_SIN
714 | R500_ALPHA_ADDRD(dest
)
715 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi
->SrcReg
[0]));
716 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_SOP
717 | R500_ALU_RGBA_ADDRD(dest
);
719 src
[0] = make_src(fp
, fpi
->SrcReg
[0]);
720 src
[1] = make_src(fp
, fpi
->SrcReg
[1]);
721 /* Variation on MAD: 1*src0-src1 */
722 fp
->inst
[counter
].inst0
= R500_INST_TYPE_ALU
724 fp
->inst
[counter
].inst1
= R500_RGB_ADDR1(src
[0])
725 | R500_RGB_ADDR2(src
[1]);
726 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR1(src
[0])
727 | R500_ALPHA_ADDR2(src
[1]);
728 fp
->inst
[counter
].inst3
= /* 1 */
729 MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE
)
730 | R500_ALU_RGB_SEL_B_SRC1
| MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi
->SrcReg
[0]));
731 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
732 | R500_ALPHA_ADDRD(dest
)
733 | R500_ALPHA_SEL_A_SRC0
| MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE
)
734 | R500_ALPHA_SEL_B_SRC1
| MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi
->SrcReg
[0]));
735 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
736 | R500_ALU_RGBA_ADDRD(dest
)
737 | R500_ALU_RGBA_SEL_C_SRC2
738 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi
->SrcReg
[1]))
739 | R500_ALU_RGBA_MOD_C_NEG
740 | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
741 | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi
->SrcReg
[1]))
742 | R500_ALU_RGBA_ALPHA_MOD_C_NEG
;
745 emit_tex(fp
, fpi
, OPCODE_TEX
, dest
, counter
);
748 emit_tex(fp
, fpi
, OPCODE_TXB
, dest
, counter
);
751 emit_tex(fp
, fpi
, OPCODE_TXP
, dest
, counter
);
754 ERROR("unknown fpi->Opcode %d\n", fpi
->Opcode
);
758 /* Finishing touches */
759 if (fpi
->SaturateMode
== SATURATE_ZERO_ONE
) {
760 fp
->inst
[counter
].inst0
|= R500_INST_RGB_CLAMP
| R500_INST_ALPHA_CLAMP
;
762 if (fpi
->DstReg
.File
== PROGRAM_OUTPUT
) {
763 fp
->inst
[counter
].inst0
|= R500_INST_TYPE_OUT
| output_mask
;
773 /* Finish him! (If it's an ALU/OUT instruction...) */
774 if ((fp
->inst
[counter
-1].inst0
& 0x3) <= 1) {
775 fp
->inst
[counter
-1].inst0
|= R500_INST_TYPE_OUT
776 | R500_INST_TEX_SEM_WAIT
| R500_INST_LAST
;
778 /* We still need to put an output inst, right? */
779 fp
->inst
[counter
].inst0
= R500_INST_TYPE_OUT
780 | R500_INST_TEX_SEM_WAIT
| R500_INST_LAST
|
782 fp
->inst
[counter
].inst1
= R500_RGB_ADDR0(dest
);
783 fp
->inst
[counter
].inst2
= R500_ALPHA_ADDR0(dest
);
784 fp
->inst
[counter
].inst3
= R500_ALU_RGB_SEL_A_SRC0
785 | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB
)
786 | R500_ALU_RGB_SEL_B_SRC0
787 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE
);
788 fp
->inst
[counter
].inst4
= R500_ALPHA_OP_MAD
789 | R500_ALPHA_ADDRD(0)
790 | R500_ALPHA_SEL_A_SRC0
| R500_ALPHA_SEL_B_SRC0
791 | R500_ALPHA_SWIZ_A_A
| R500_ALPHA_SWIZ_B_1
;
792 fp
->inst
[counter
].inst5
= R500_ALU_RGBA_OP_MAD
793 | R500_ALU_RGBA_ADDRD(0)
794 | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO
)
795 | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO
);
799 fp
->cs
->nrslots
= counter
;
806 static void init_program(r300ContextPtr r300
, struct r500_fragment_program
*fp
)
808 struct r300_pfs_compile_state
*cs
= NULL
;
809 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
810 struct prog_instruction
*fpi
;
811 GLuint InputsRead
= mp
->Base
.InputsRead
;
812 GLuint temps_used
= 0; /* for fp->temps[] */
815 /* New compile, reset tracking data */
817 driQueryOptioni(&r300
->radeon
.optionCache
, "fp_optimization");
818 fp
->translated
= GL_FALSE
;
819 fp
->error
= GL_FALSE
;
820 fp
->cs
= cs
= &(R300_CONTEXT(fp
->ctx
)->state
.pfs_compile
);
822 fp
->first_node_has_tex
= 0;
824 /* Size of pixel stack, plus 1. */
825 fp
->max_temp_idx
= 1;
826 /* Temp register offset. */
827 fp
->temp_reg_offset
= 0;
828 fp
->node
[0].alu_end
= -1;
829 fp
->node
[0].tex_end
= -1;
831 _mesa_memset(cs
, 0, sizeof(*fp
->cs
));
832 for (i
= 0; i
< PFS_MAX_ALU_INST
; i
++) {
833 for (j
= 0; j
< 3; j
++) {
834 cs
->slot
[i
].vsrc
[j
] = SRC_CONST
;
835 cs
->slot
[i
].ssrc
[j
] = SRC_CONST
;
839 /* Work out what temps the Mesa inputs correspond to, this must match
840 * what setup_rs_unit does, which shouldn't be a problem as rs_unit
841 * configures itself based on the fragprog's InputsRead
843 * NOTE: this depends on get_hw_temp() allocating registers in order,
844 * starting from register 0, so we're just going to do that instead.
847 /* Texcoords come first */
848 for (i
= 0; i
< fp
->ctx
->Const
.MaxTextureUnits
; i
++) {
849 if (InputsRead
& (FRAG_BIT_TEX0
<< i
)) {
850 cs
->inputs
[FRAG_ATTRIB_TEX0
+ i
].refcount
= 0;
851 cs
->inputs
[FRAG_ATTRIB_TEX0
+ i
].reg
=
853 fp
->temp_reg_offset
++;
856 InputsRead
&= ~FRAG_BITS_TEX_ANY
;
858 /* fragment position treated as a texcoord */
859 if (InputsRead
& FRAG_BIT_WPOS
) {
860 cs
->inputs
[FRAG_ATTRIB_WPOS
].refcount
= 0;
861 cs
->inputs
[FRAG_ATTRIB_WPOS
].reg
=
863 fp
->temp_reg_offset
++;
865 InputsRead
&= ~FRAG_BIT_WPOS
;
867 /* Then primary colour */
868 if (InputsRead
& FRAG_BIT_COL0
) {
869 cs
->inputs
[FRAG_ATTRIB_COL0
].refcount
= 0;
870 cs
->inputs
[FRAG_ATTRIB_COL0
].reg
=
872 fp
->temp_reg_offset
++;
874 InputsRead
&= ~FRAG_BIT_COL0
;
876 /* Secondary color */
877 if (InputsRead
& FRAG_BIT_COL1
) {
878 cs
->inputs
[FRAG_ATTRIB_COL1
].refcount
= 0;
879 cs
->inputs
[FRAG_ATTRIB_COL1
].reg
=
881 fp
->temp_reg_offset
++;
883 InputsRead
&= ~FRAG_BIT_COL1
;
887 WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead
);
888 /* force read from hwreg 0 for now */
889 for (i
= 0; i
< 32; i
++)
890 if (InputsRead
& (1 << i
))
891 cs
->inputs
[i
].reg
= 0;
894 /* Pre-parse the mesa program, grabbing refcounts on input/temp regs.
895 * That way, we can free up the reg when it's no longer needed
897 if (!mp
->Base
.Instructions
) {
898 ERROR("No instructions found in program, going to go die now.\n");
903 for (fpi
= mp
->Base
.Instructions
; fpi
->Opcode
!= OPCODE_END
; fpi
++) {
905 for (i
= 0; i
< 3; i
++) {
906 idx
= fpi
->SrcReg
[i
].Index
;
907 if (fpi
->SrcReg
[i
].File
== PROGRAM_INPUT
) {
908 cs
->inputs
[idx
].refcount
++;
909 if (fp
->max_temp_idx
< idx
)
910 fp
->max_temp_idx
= idx
;
916 fp
->max_temp_idx
= fp
->temp_reg_offset
+ 1;
918 cs
->temp_in_use
= temps_used
;
921 static void update_params(struct r500_fragment_program
*fp
)
923 struct gl_fragment_program
*mp
= &fp
->mesa_program
;
925 /* Ask Mesa nicely to fill in ParameterValues for us */
926 if (mp
->Base
.Parameters
)
927 _mesa_load_state_parameters(fp
->ctx
, mp
->Base
.Parameters
);
930 void r500TranslateFragmentShader(r300ContextPtr r300
,
931 struct r500_fragment_program
*fp
)
934 struct r300_pfs_compile_state
*cs
= NULL
;
936 if (!fp
->translated
) {
938 /* I need to see what I'm working with! */
939 fprintf(stderr
, "Mesa program:\n");
940 fprintf(stderr
, "-------------\n");
941 _mesa_print_program(&fp
->mesa_program
.Base
);
944 init_program(r300
, fp
);
947 if (parse_program(fp
) == GL_FALSE
) {
948 ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n");
951 fp
->inst_end
= cs
->nrslots
- 1;
955 fp
->inst_end
= cs
->nrslots
- 1;
957 fp
->translated
= GL_TRUE
;
958 r300UpdateStateParameters(fp
->ctx
, _NEW_PROGRAM
);