src/mesa/drivers/dri/r300/radeon_ioctl.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include <sched.h>
  36 #include <errno.h>
  37
  38 #include "glheader.h"
  39 #include "imports.h"
  40 #include "macros.h"
  41 #include "context.h"
  42 #include "swrast/swrast.h"
  43 #include "r200_context.h"
  44 #include "r300_context.h"
  45 #include "r200_state.h"
  46 #include "radeon_ioctl.h"
  47 #include "r200_ioctl.h"
  48 #include "r300_ioctl.h"
  49 #if R200_MERGED
  50 #include "r200_tcl.h"
  51 #include "r200_sanity.h"
  52 #endif
  53 #include "r300_state.h"
  54 #include "radeon_reg.h"
  55
  56 #include "drirenderbuffer.h"
  57 #include "vblank.h"
  58
  59 static void radeonWaitForIdle(radeonContextPtr radeon);
  60
  61 /* ================================================================
  62  * SwapBuffers with client-side throttling
  63  */
  64
  65 static uint32_t radeonGetLastFrame(radeonContextPtr radeon)
  66 {
  67         drm_radeon_getparam_t gp;
  68         int ret;
  69         uint32_t frame;
  70
  71         gp.param = RADEON_PARAM_LAST_FRAME;
  72         gp.value = (int *)&frame;
  73         ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM,
  74                                   &gp, sizeof(gp));
  75         if (ret) {
  76                 fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__,
  77                         ret);
  78                 exit(1);
  79         }
  80
  81         return frame;
  82 }
  83
  84 uint32_t radeonGetAge(radeonContextPtr radeon)
  85 {
  86         drm_radeon_getparam_t gp;
  87         int ret;
  88         uint32_t age;
  89
  90         gp.param = RADEON_PARAM_LAST_CLEAR;
  91         gp.value = (int *)&age;
  92         ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM,
  93                                   &gp, sizeof(gp));
  94         if (ret) {
  95                 fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__,
  96                         ret);
  97                 exit(1);
  98         }
  99
 100         return age;
 101 }
 102
 103 static void radeonEmitIrqLocked(radeonContextPtr radeon)
 104 {
 105         drm_radeon_irq_emit_t ie;
 106         int ret;
 107
 108         ie.irq_seq = &radeon->iw.irq_seq;
 109         ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT,
 110                                   &ie, sizeof(ie));
 111         if (ret) {
 112                 fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__,
 113                         ret);
 114                 exit(1);
 115         }
 116 }
 117
 118 static void radeonWaitIrq(radeonContextPtr radeon)
 119 {
 120         int ret;
 121
 122         do {
 123                 ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT,
 124                                       &radeon->iw, sizeof(radeon->iw));
 125         } while (ret && (errno == EINTR || errno == EBUSY));
 126
 127         if (ret) {
 128                 fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__,
 129                         ret);
 130                 exit(1);
 131         }
 132 }
 133
 134 static void radeonWaitForFrameCompletion(radeonContextPtr radeon)
 135 {
 136         drm_radeon_sarea_t *sarea = radeon->sarea;
 137
 138         if (radeon->do_irqs) {
 139                 if (radeonGetLastFrame(radeon) < sarea->last_frame) {
 140                         if (!radeon->irqsEmitted) {
 141                                 while (radeonGetLastFrame(radeon) <
 142                                        sarea->last_frame) ;
 143                         } else {
 144                                 UNLOCK_HARDWARE(radeon);
 145                                 radeonWaitIrq(radeon);
 146                                 LOCK_HARDWARE(radeon);
 147                         }
 148                         radeon->irqsEmitted = 10;
 149                 }
 150
 151                 if (radeon->irqsEmitted) {
 152                         radeonEmitIrqLocked(radeon);
 153                         radeon->irqsEmitted--;
 154                 }
 155         } else {
 156                 while (radeonGetLastFrame(radeon) < sarea->last_frame) {
 157                         UNLOCK_HARDWARE(radeon);
 158                         if (radeon->do_usleeps)
 159                                 DO_USLEEP(1);
 160                         LOCK_HARDWARE(radeon);
 161                 }
 162         }
 163 }
 164
 165 /* Copy the back color buffer to the front color buffer.
 166  */
 167 void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv,
 168                       const drm_clip_rect_t      * rect)
 169 {
 170         radeonContextPtr radeon;
 171         GLint nbox, i, ret;
 172         GLboolean missed_target;
 173         int64_t ust;
 174
 175         assert(dPriv);
 176         assert(dPriv->driContextPriv);
 177         assert(dPriv->driContextPriv->driverPrivate);
 178
 179         radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 180
 181         if (RADEON_DEBUG & DEBUG_IOCTL) {
 182                 fprintf(stderr, "\n%s( %p )\n\n", __FUNCTION__,
 183                         (void *)radeon->glCtx);
 184         }
 185
 186         if (IS_R200_CLASS(radeon->radeonScreen))
 187                 R200_FIREVERTICES((r200ContextPtr)radeon);
 188         else
 189                 r300Flush(radeon->glCtx);
 190
 191         LOCK_HARDWARE(radeon);
 192
 193         /* Throttle the frame rate -- only allow one pending swap buffers
 194          * request at a time.
 195          */
 196         radeonWaitForFrameCompletion(radeon);
 197         if (!rect)
 198         {
 199             UNLOCK_HARDWARE(radeon);
 200             driWaitForVBlank(dPriv, &radeon->vbl_seq, radeon->vblank_flags,
 201                              &missed_target);
 202             LOCK_HARDWARE(radeon);
 203         }
 204
 205         nbox = dPriv->numClipRects;     /* must be in locked region */
 206
 207         for (i = 0; i < nbox;) {
 208                 GLint nr = MIN2(i + RADEON_NR_SAREA_CLIPRECTS, nbox);
 209                 drm_clip_rect_t *box = dPriv->pClipRects;
 210                 drm_clip_rect_t *b = radeon->sarea->boxes;
 211                 GLint n = 0;
 212
 213                 for ( ; i < nr ; i++ ) {
 214
 215                     *b = box[i];
 216
 217                     if (rect)
 218                     {
 219                         if (rect->x1 > b->x1)
 220                             b->x1 = rect->x1;
 221                         if (rect->y1 > b->y1)
 222                             b->y1 = rect->y1;
 223                         if (rect->x2 < b->x2)
 224                             b->x2 = rect->x2;
 225                         if (rect->y2 < b->y2)
 226                             b->y2 = rect->y2;
 227
 228                         if (b->x1 < b->x2 && b->y1 < b->y2)
 229                             b++;
 230                     }
 231                     else
 232                         b++;
 233
 234                     n++;
 235                 }
 236                 radeon->sarea->nbox = n;
 237
 238                 ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_SWAP);
 239
 240                 if (ret) {
 241                         fprintf(stderr, "DRM_RADEON_SWAP: return = %d\n",
 242                                 ret);
 243                         UNLOCK_HARDWARE(radeon);
 244                         exit(1);
 245                 }
 246         }
 247
 248         UNLOCK_HARDWARE(radeon);
 249         if (!rect)
 250         {
 251             if (IS_R200_CLASS(radeon->radeonScreen))
 252                 ((r200ContextPtr)radeon)->hw.all_dirty = GL_TRUE;
 253             else
 254                 ((r300ContextPtr)radeon)->hw.all_dirty = GL_TRUE;
 255
 256             radeon->swap_count++;
 257             (*dri_interface->getUST) (&ust);
 258             if (missed_target) {
 259                 radeon->swap_missed_count++;
 260                 radeon->swap_missed_ust = ust - radeon->swap_ust;
 261             }
 262
 263             radeon->swap_ust = ust;
 264
 265             sched_yield();
 266         }
 267 }
 268
 269 void radeonPageFlip(const __DRIdrawablePrivate * dPriv)
 270 {
 271         radeonContextPtr radeon;
 272         GLint ret;
 273         GLboolean missed_target;
 274
 275         assert(dPriv);
 276         assert(dPriv->driContextPriv);
 277         assert(dPriv->driContextPriv->driverPrivate);
 278
 279         radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 280
 281         if (RADEON_DEBUG & DEBUG_IOCTL) {
 282                 fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
 283                         radeon->sarea->pfCurrentPage);
 284         }
 285
 286         if (IS_R200_CLASS(radeon->radeonScreen))
 287                 R200_FIREVERTICES((r200ContextPtr)radeon);
 288         else
 289                 r300Flush(radeon->glCtx);
 290         LOCK_HARDWARE(radeon);
 291
 292         if (!dPriv->numClipRects) {
 293                 UNLOCK_HARDWARE(radeon);
 294                 usleep(10000);  /* throttle invisible client 10ms */
 295                 return;
 296         }
 297
 298         /* Need to do this for the perf box placement:
 299          */
 300         {
 301                 drm_clip_rect_t *box = dPriv->pClipRects;
 302                 drm_clip_rect_t *b = radeon->sarea->boxes;
 303                 b[0] = box[0];
 304                 radeon->sarea->nbox = 1;
 305         }
 306
 307         /* Throttle the frame rate -- only allow a few pending swap buffers
 308          * request at a time.
 309          */
 310         radeonWaitForFrameCompletion(radeon);
 311         UNLOCK_HARDWARE(radeon);
 312         driWaitForVBlank(dPriv, &radeon->vbl_seq, radeon->vblank_flags,
 313                          &missed_target);
 314         if (missed_target) {
 315                 radeon->swap_missed_count++;
 316                 (void)(*dri_interface->getUST) (&radeon->swap_missed_ust);
 317         }
 318         LOCK_HARDWARE(radeon);
 319
 320         ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_FLIP);
 321
 322         UNLOCK_HARDWARE(radeon);
 323
 324         if (ret) {
 325                 fprintf(stderr, "DRM_RADEON_FLIP: return = %d\n", ret);
 326                 exit(1);
 327         }
 328
 329         radeon->swap_count++;
 330         (void)(*dri_interface->getUST) (&radeon->swap_ust);
 331
 332         driFlipRenderbuffers(radeon->glCtx->WinSysDrawBuffer,
 333                              radeon->sarea->pfCurrentPage);
 334
 335         if (radeon->sarea->pfCurrentPage == 1) {
 336                 radeon->state.color.drawOffset = radeon->radeonScreen->frontOffset;
 337                 radeon->state.color.drawPitch = radeon->radeonScreen->frontPitch;
 338         } else {
 339                 radeon->state.color.drawOffset = radeon->radeonScreen->backOffset;
 340                 radeon->state.color.drawPitch = radeon->radeonScreen->backPitch;
 341         }
 342
 343         if (IS_R200_CLASS(radeon->radeonScreen)) {
 344                 r200ContextPtr r200 = (r200ContextPtr)radeon;
 345
 346                 R200_STATECHANGE(r200, ctx);
 347                 r200->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = radeon->state.color.drawOffset
 348                         + radeon->radeonScreen->fbLocation;
 349                 r200->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = radeon->state.color.drawPitch;
 350         }
 351         if (IS_R300_CLASS(radeon->radeonScreen)) {
 352                 r300ContextPtr r300 = (r300ContextPtr)radeon;
 353                 R300_STATECHANGE(r300, cb);
 354                 r300->hw.cb.cmd[R300_CB_OFFSET] = r300->radeon.state.color.drawOffset +
 355                                                 r300->radeon.radeonScreen->fbLocation;
 356                 r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.state.color.drawPitch;
 357
 358                 if (r300->radeon.radeonScreen->cpp == 4)
 359                         r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_ARGB8888;
 360                 else
 361                         r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_RGB565;
 362
 363                 if (r300->radeon.sarea->tiling_enabled)
 364                         r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE;
 365         }
 366 }
 367
 368 void radeonWaitForIdleLocked(radeonContextPtr radeon)
 369 {
 370         int ret;
 371         int i = 0;
 372
 373         do {
 374                 ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE);
 375                 if (ret)
 376                         DO_USLEEP(1);
 377         } while (ret && ++i < 100);
 378
 379         if (ret < 0) {
 380                 UNLOCK_HARDWARE(radeon);
 381                 fprintf(stderr, "Error: R200 timed out... exiting\n");
 382                 exit(-1);
 383         }
 384 }
 385
 386 static void radeonWaitForIdle(radeonContextPtr radeon)
 387 {
 388         LOCK_HARDWARE(radeon);
 389         radeonWaitForIdleLocked(radeon);
 390         UNLOCK_HARDWARE(radeon);
 391 }
 392
 393 void radeonFlush(GLcontext * ctx)
 394 {
 395         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 396
 397         if (IS_R300_CLASS(radeon->radeonScreen))
 398                 r300Flush(ctx);
 399 #if R200_MERGED
 400         else
 401                 r200Flush(ctx);
 402 #endif
 403 }
 404
 405
 406 /* Make sure all commands have been sent to the hardware and have
 407  * completed processing.
 408  */
 409 void radeonFinish(GLcontext * ctx)
 410 {
 411         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 412
 413         radeonFlush(ctx);
 414
 415         if (radeon->do_irqs) {
 416                 LOCK_HARDWARE(radeon);
 417                 radeonEmitIrqLocked(radeon);
 418                 UNLOCK_HARDWARE(radeon);
 419                 radeonWaitIrq(radeon);
 420         } else
 421                 radeonWaitForIdle(radeon);
 422 }