2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
42 #include "swrast/swrast.h"
44 #include "r200_context.h"
45 #include "r300_context.h"
46 #include "r200_state.h"
47 #include "radeon_ioctl.h"
48 #include "r200_ioctl.h"
49 #include "r300_ioctl.h"
51 #include "r200_sanity.h"
52 #include "radeon_reg.h"
56 static void radeonWaitForIdle(radeonContextPtr radeon
);
58 /* ================================================================
59 * SwapBuffers with client-side throttling
62 static uint32_t radeonGetLastFrame(radeonContextPtr radeon
)
64 drm_radeon_getparam_t gp
;
68 gp
.param
= RADEON_PARAM_LAST_FRAME
;
69 gp
.value
= (int *)&frame
;
70 ret
= drmCommandWriteRead(radeon
->dri
.fd
, DRM_RADEON_GETPARAM
,
73 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
,
81 static void radeonEmitIrqLocked(radeonContextPtr radeon
)
83 drm_radeon_irq_emit_t ie
;
86 ie
.irq_seq
= &radeon
->iw
.irq_seq
;
87 ret
= drmCommandWriteRead(radeon
->dri
.fd
, DRM_RADEON_IRQ_EMIT
,
90 fprintf(stderr
, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__
,
96 static void radeonWaitIrq(radeonContextPtr radeon
)
101 ret
= drmCommandWrite(radeon
->dri
.fd
, DRM_RADEON_IRQ_WAIT
,
102 &radeon
->iw
, sizeof(radeon
->iw
));
103 } while (ret
&& (errno
== EINTR
|| errno
== EAGAIN
));
106 fprintf(stderr
, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__
,
112 static void radeonWaitForFrameCompletion(radeonContextPtr radeon
)
114 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
116 if (radeon
->do_irqs
) {
117 if (radeonGetLastFrame(radeon
) < sarea
->last_frame
) {
118 if (!radeon
->irqsEmitted
) {
119 while (radeonGetLastFrame(radeon
) <
122 UNLOCK_HARDWARE(radeon
);
123 radeonWaitIrq(radeon
);
124 LOCK_HARDWARE(radeon
);
126 radeon
->irqsEmitted
= 10;
129 if (radeon
->irqsEmitted
) {
130 radeonEmitIrqLocked(radeon
);
131 radeon
->irqsEmitted
--;
134 while (radeonGetLastFrame(radeon
) < sarea
->last_frame
) {
135 UNLOCK_HARDWARE(radeon
);
136 if (radeon
->do_usleeps
)
138 LOCK_HARDWARE(radeon
);
143 /* Copy the back color buffer to the front color buffer.
145 void radeonCopyBuffer(const __DRIdrawablePrivate
* dPriv
)
147 radeonContextPtr radeon
;
149 GLboolean missed_target
;
153 assert(dPriv
->driContextPriv
);
154 assert(dPriv
->driContextPriv
->driverPrivate
);
156 radeon
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
158 if (RADEON_DEBUG
& DEBUG_IOCTL
) {
159 fprintf(stderr
, "\n%s( %p )\n\n", __FUNCTION__
,
160 (void *)radeon
->glCtx
);
163 if (IS_FAMILY_R200(radeon
))
164 R200_FIREVERTICES((r200ContextPtr
)radeon
);
166 r300Flush(radeon
->glCtx
);
168 LOCK_HARDWARE(radeon
);
170 /* Throttle the frame rate -- only allow one pending swap buffers
173 radeonWaitForFrameCompletion(radeon
);
174 UNLOCK_HARDWARE(radeon
);
175 driWaitForVBlank(dPriv
, &radeon
->vbl_seq
, radeon
->vblank_flags
,
177 LOCK_HARDWARE(radeon
);
179 nbox
= dPriv
->numClipRects
; /* must be in locked region */
181 for (i
= 0; i
< nbox
;) {
182 GLint nr
= MIN2(i
+ RADEON_NR_SAREA_CLIPRECTS
, nbox
);
183 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
184 drm_clip_rect_t
*b
= radeon
->sarea
->boxes
;
187 for (; i
< nr
; i
++) {
191 radeon
->sarea
->nbox
= n
;
193 ret
= drmCommandNone(radeon
->dri
.fd
, DRM_RADEON_SWAP
);
196 fprintf(stderr
, "DRM_RADEON_SWAP: return = %d\n",
198 UNLOCK_HARDWARE(radeon
);
203 UNLOCK_HARDWARE(radeon
);
205 if (IS_FAMILY_R200(radeon
))
206 ((r200ContextPtr
)radeon
)->hw
.all_dirty
= GL_TRUE
;
208 ((r300ContextPtr
)radeon
)->hw
.all_dirty
= GL_TRUE
;
210 radeon
->swap_count
++;
211 (*radeon
->get_ust
) (&ust
);
213 radeon
->swap_missed_count
++;
214 radeon
->swap_missed_ust
= ust
- radeon
->swap_ust
;
217 radeon
->swap_ust
= ust
;
222 void radeonPageFlip(const __DRIdrawablePrivate
* dPriv
)
224 radeonContextPtr radeon
;
226 GLboolean missed_target
;
229 assert(dPriv
->driContextPriv
);
230 assert(dPriv
->driContextPriv
->driverPrivate
);
232 radeon
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
234 if (RADEON_DEBUG
& DEBUG_IOCTL
) {
235 fprintf(stderr
, "%s: pfCurrentPage: %d\n", __FUNCTION__
,
236 radeon
->sarea
->pfCurrentPage
);
239 if (IS_FAMILY_R200(radeon
))
240 R200_FIREVERTICES((r200ContextPtr
)radeon
);
241 LOCK_HARDWARE(radeon
);
243 if (!dPriv
->numClipRects
) {
244 UNLOCK_HARDWARE(radeon
);
245 usleep(10000); /* throttle invisible client 10ms */
249 /* Need to do this for the perf box placement:
252 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
253 drm_clip_rect_t
*b
= radeon
->sarea
->boxes
;
255 radeon
->sarea
->nbox
= 1;
258 /* Throttle the frame rate -- only allow a few pending swap buffers
261 radeonWaitForFrameCompletion(radeon
);
262 UNLOCK_HARDWARE(radeon
);
263 driWaitForVBlank(dPriv
, &radeon
->vbl_seq
, radeon
->vblank_flags
,
266 radeon
->swap_missed_count
++;
267 (void)(*radeon
->get_ust
) (&radeon
->swap_missed_ust
);
269 LOCK_HARDWARE(radeon
);
271 ret
= drmCommandNone(radeon
->dri
.fd
, DRM_RADEON_FLIP
);
273 UNLOCK_HARDWARE(radeon
);
276 fprintf(stderr
, "DRM_RADEON_FLIP: return = %d\n", ret
);
280 radeon
->swap_count
++;
281 (void)(*radeon
->get_ust
) (&radeon
->swap_ust
);
283 if (radeon
->sarea
->pfCurrentPage
== 1) {
284 radeon
->state
.color
.drawOffset
= radeon
->radeonScreen
->frontOffset
;
285 radeon
->state
.color
.drawPitch
= radeon
->radeonScreen
->frontPitch
;
287 radeon
->state
.color
.drawOffset
= radeon
->radeonScreen
->backOffset
;
288 radeon
->state
.color
.drawPitch
= radeon
->radeonScreen
->backPitch
;
291 if (IS_FAMILY_R200(radeon
)) {
292 r200ContextPtr r200
= (r200ContextPtr
)radeon
;
294 R200_STATECHANGE(r200
, ctx
);
295 r200
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = radeon
->state
.color
.drawOffset
296 + radeon
->radeonScreen
->fbLocation
;
297 r200
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = radeon
->state
.color
.drawPitch
;
301 void radeonWaitForIdleLocked(radeonContextPtr radeon
)
307 ret
= drmCommandNone(radeon
->dri
.fd
, DRM_RADEON_CP_IDLE
);
310 } while (ret
&& ++i
< 100);
313 UNLOCK_HARDWARE(radeon
);
314 fprintf(stderr
, "Error: R200 timed out... exiting\n");
319 static void radeonWaitForIdle(radeonContextPtr radeon
)
321 LOCK_HARDWARE(radeon
);
322 radeonWaitForIdleLocked(radeon
);
323 UNLOCK_HARDWARE(radeon
);
326 void radeonFlush(GLcontext
* ctx
)
328 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
330 if (IS_FAMILY_R300(radeon
))
337 /* Make sure all commands have been sent to the hardware and have
338 * completed processing.
340 void radeonFinish(GLcontext
* ctx
)
342 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
346 if (radeon
->do_irqs
) {
347 LOCK_HARDWARE(radeon
);
348 radeonEmitIrqLocked(radeon
);
349 UNLOCK_HARDWARE(radeon
);
350 radeonWaitIrq(radeon
);
352 radeonWaitForIdle(radeon
);