src/mesa/drivers/dri/r300/radeon_nqssadce.h

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef __RADEON_PROGRAM_NQSSADCE_H_
  29 #define __RADEON_PROGRAM_NQSSADCE_H_
  30
  31 #include "radeon_program.h"
  32
  33
  34 struct register_state {
  35         /**
  36          * Bitmask indicating which components of the register are sourced
  37          * by later instructions.
  38          */
  39         GLuint Sourced : 4;
  40 };
  41
  42 /**
  43  * Maintain state such as which registers are used, which registers are
  44  * read from, etc.
  45  */
  46 struct nqssadce_state {
  47         GLcontext *Ctx;
  48         struct gl_program *Program;
  49         struct radeon_nqssadce_descr *Descr;
  50
  51         /**
  52          * All instructions after this instruction pointer have been dealt with.
  53          */
  54         int IP;
  55
  56         /**
  57          * Which registers are read by subsequent instructions?
  58          */
  59         struct register_state Temps[MAX_PROGRAM_TEMPS];
  60         struct register_state Outputs[VERT_RESULT_MAX];
  61 };
  62
  63
  64 /**
  65  * This structure contains a description of the hardware in-so-far as
  66  * it is required for the NqSSA-DCE pass.
  67  */
  68 struct radeon_nqssadce_descr {
  69         /**
  70          * Fill in which outputs
  71          */
  72         void (*Init)(struct nqssadce_state *);
  73
  74         /**
  75          * Check whether the given swizzle, absolute and negate combination
  76          * can be implemented natively by the hardware for this opcode.
  77          */
  78         GLboolean (*IsNativeSwizzle)(GLuint opcode, struct prog_src_register reg);
  79
  80         /**
  81          * Emit (at the current IP) the instruction MOV dst, src;
  82          * The transformation will work recursively on the emitted instruction(s).
  83          */
  84         void (*BuildSwizzle)(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
  85
  86         /**
  87          * Rewrite instructions that write to DEPR.z to write to DEPR.w
  88          * instead (rewriting is done *before* the WriteMask test).
  89          */
  90         GLboolean RewriteDepthOut;
  91         void *Data;
  92 };
  93
  94 void radeonNqssaDce(GLcontext *ctx, struct gl_program *p, struct radeon_nqssadce_descr* descr);
  95
  96 #endif /* __RADEON_PROGRAM_NQSSADCE_H_ */