src/mesa/drivers/dri/r300/radeon_program_alu.c

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * @file
  30  *
  31  * Shareable transformations that transform "special" ALU instructions
  32  * into ALU instructions that are supported by hardware.
  33  *
  34  */
  35
  36 #include "radeon_program_alu.h"
  37
  38 #include "shader/prog_parameter.h"
  39
  40
  41 static struct prog_instruction *emit1(struct gl_program* p,
  42         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  43         struct prog_src_register SrcReg)
  44 {
  45         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  46
  47         fpi->Opcode = Opcode;
  48         fpi->DstReg = DstReg;
  49         fpi->SrcReg[0] = SrcReg;
  50         return fpi;
  51 }
  52
  53 static struct prog_instruction *emit2(struct gl_program* p,
  54         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  55         struct prog_src_register SrcReg0, struct prog_src_register SrcReg1)
  56 {
  57         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  58
  59         fpi->Opcode = Opcode;
  60         fpi->DstReg = DstReg;
  61         fpi->SrcReg[0] = SrcReg0;
  62         fpi->SrcReg[1] = SrcReg1;
  63         return fpi;
  64 }
  65
  66 static struct prog_instruction *emit3(struct gl_program* p,
  67         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  68         struct prog_src_register SrcReg0, struct prog_src_register SrcReg1,
  69         struct prog_src_register SrcReg2)
  70 {
  71         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  72
  73         fpi->Opcode = Opcode;
  74         fpi->DstReg = DstReg;
  75         fpi->SrcReg[0] = SrcReg0;
  76         fpi->SrcReg[1] = SrcReg1;
  77         fpi->SrcReg[2] = SrcReg2;
  78         return fpi;
  79 }
  80
  81 static void set_swizzle(struct prog_src_register *SrcReg, int coordinate, int swz)
  82 {
  83         SrcReg->Swizzle &= ~(7 << (3*coordinate));
  84         SrcReg->Swizzle |= swz << (3*coordinate);
  85 }
  86
  87 static void set_negate_base(struct prog_src_register *SrcReg, int coordinate, int negate)
  88 {
  89         SrcReg->NegateBase &= ~(1 << coordinate);
  90         SrcReg->NegateBase |= (negate << coordinate);
  91 }
  92
  93 static struct prog_dst_register dstreg(int file, int index)
  94 {
  95         struct prog_dst_register dst;
  96         dst.File = file;
  97         dst.Index = index;
  98         dst.WriteMask = WRITEMASK_XYZW;
  99         dst.CondMask = COND_TR;
 100         dst.CondSwizzle = SWIZZLE_NOOP;
 101         dst.CondSrc = 0;
 102         dst.pad = 0;
 103         return dst;
 104 }
 105
 106 static struct prog_dst_register dstregtmpmask(int index, int mask)
 107 {
 108         struct prog_dst_register dst;
 109         dst.File = PROGRAM_TEMPORARY;
 110         dst.Index = index;
 111         dst.WriteMask = mask;
 112         dst.CondMask = COND_TR;
 113         dst.CondSwizzle = SWIZZLE_NOOP;
 114         dst.CondSrc = 0;
 115         dst.pad = 0;
 116         return dst;
 117 }
 118
 119 static const struct prog_src_register builtin_zero = {
 120         .File = PROGRAM_BUILTIN,
 121         .Index = 0,
 122         .Swizzle = SWIZZLE_0000
 123 };
 124 static const struct prog_src_register builtin_one = {
 125         .File = PROGRAM_BUILTIN,
 126         .Index = 0,
 127         .Swizzle = SWIZZLE_1111
 128 };
 129 static const struct prog_src_register srcreg_undefined = {
 130         .File = PROGRAM_UNDEFINED,
 131         .Index = 0,
 132         .Swizzle = SWIZZLE_NOOP
 133 };
 134
 135 static struct prog_src_register srcreg(int file, int index)
 136 {
 137         struct prog_src_register src = srcreg_undefined;
 138         src.File = file;
 139         src.Index = index;
 140         return src;
 141 }
 142
 143 static struct prog_src_register srcregswz(int file, int index, int swz)
 144 {
 145         struct prog_src_register src = srcreg_undefined;
 146         src.File = file;
 147         src.Index = index;
 148         src.Swizzle = swz;
 149         return src;
 150 }
 151
 152 static struct prog_src_register absolute(struct prog_src_register reg)
 153 {
 154         struct prog_src_register newreg = reg;
 155         newreg.Abs = 1;
 156         newreg.NegateBase = 0;
 157         newreg.NegateAbs = 0;
 158         return newreg;
 159 }
 160
 161 static struct prog_src_register negate(struct prog_src_register reg)
 162 {
 163         struct prog_src_register newreg = reg;
 164         newreg.NegateAbs = !newreg.NegateAbs;
 165         return newreg;
 166 }
 167
 168 static struct prog_src_register swizzle(struct prog_src_register reg, GLuint x, GLuint y, GLuint z, GLuint w)
 169 {
 170         struct prog_src_register swizzled = reg;
 171         swizzled.Swizzle = MAKE_SWIZZLE4(
 172                 x >= 4 ? x : GET_SWZ(reg.Swizzle, x),
 173                 y >= 4 ? y : GET_SWZ(reg.Swizzle, y),
 174                 z >= 4 ? z : GET_SWZ(reg.Swizzle, z),
 175                 w >= 4 ? w : GET_SWZ(reg.Swizzle, w));
 176         return swizzled;
 177 }
 178
 179 static struct prog_src_register scalar(struct prog_src_register reg)
 180 {
 181         return swizzle(reg, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X);
 182 }
 183
 184 static void transform_ABS(struct radeon_transform_context* t,
 185         struct prog_instruction* inst)
 186 {
 187         struct prog_src_register src = inst->SrcReg[0];
 188         src.Abs = 1;
 189         src.NegateBase = 0;
 190         src.NegateAbs = 0;
 191         emit1(t->Program, OPCODE_MOV, inst->DstReg, src);
 192 }
 193
 194 static void transform_DPH(struct radeon_transform_context* t,
 195         struct prog_instruction* inst)
 196 {
 197         struct prog_src_register src0 = inst->SrcReg[0];
 198         if (src0.NegateAbs) {
 199                 if (src0.Abs) {
 200                         int tempreg = radeonFindFreeTemporary(t);
 201                         emit1(t->Program, OPCODE_MOV, dstreg(PROGRAM_TEMPORARY, tempreg), src0);
 202                         src0 = srcreg(src0.File, src0.Index);
 203                 } else {
 204                         src0.NegateAbs = 0;
 205                         src0.NegateBase ^= NEGATE_XYZW;
 206                 }
 207         }
 208         set_swizzle(&src0, 3, SWIZZLE_ONE);
 209         set_negate_base(&src0, 3, 0);
 210         emit2(t->Program, OPCODE_DP4, inst->DstReg, src0, inst->SrcReg[1]);
 211 }
 212
 213 /**
 214  * [1, src0.y*src1.y, src0.z, src1.w]
 215  * So basically MUL with lotsa swizzling.
 216  */
 217 static void transform_DST(struct radeon_transform_context* t,
 218         struct prog_instruction* inst)
 219 {
 220         emit2(t->Program, OPCODE_MUL, inst->DstReg,
 221                 swizzle(inst->SrcReg[0], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE),
 222                 swizzle(inst->SrcReg[1], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_W));
 223 }
 224
 225 static void transform_FLR(struct radeon_transform_context* t,
 226         struct prog_instruction* inst)
 227 {
 228         int tempreg = radeonFindFreeTemporary(t);
 229         emit1(t->Program, OPCODE_FRC, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]);
 230         emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
 231 }
 232
 233 /**
 234  * Definition of LIT (from ARB_fragment_program):
 235  *
 236  *  tmp = VectorLoad(op0);
 237  *  if (tmp.x < 0) tmp.x = 0;
 238  *  if (tmp.y < 0) tmp.y = 0;
 239  *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 240  *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 241  *  result.x = 1.0;
 242  *  result.y = tmp.x;
 243  *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 244  *  result.w = 1.0;
 245  *
 246  * The longest path of computation is the one leading to result.z,
 247  * consisting of 5 operations. This implementation of LIT takes
 248  * 5 slots, if the subsequent optimization passes are clever enough
 249  * to pair instructions correctly.
 250  */
 251 static void transform_LIT(struct radeon_transform_context* t,
 252         struct prog_instruction* inst)
 253 {
 254         static const GLfloat LitConst[4] = { -127.999999 };
 255
 256         GLuint constant;
 257         GLuint constant_swizzle;
 258         GLuint temp;
 259         int needTemporary = 0;
 260         struct prog_src_register srctemp;
 261
 262         constant = _mesa_add_unnamed_constant(t->Program->Parameters, LitConst, 1, &constant_swizzle);
 263
 264         if (inst->DstReg.WriteMask != WRITEMASK_XYZW) {
 265                 needTemporary = 1;
 266         } else if (inst->DstReg.File != PROGRAM_TEMPORARY) {
 267                 // LIT is typically followed by DP3/DP4, so there's no point
 268                 // in creating special code for this case
 269                 needTemporary = 1;
 270         }
 271
 272         if (needTemporary) {
 273                 temp = radeonFindFreeTemporary(t);
 274         } else {
 275                 temp = inst->DstReg.Index;
 276         }
 277         srctemp = srcreg(PROGRAM_TEMPORARY, temp);
 278
 279         // tmp.x = max(0.0, Src.x);
 280         // tmp.y = max(0.0, Src.y);
 281         // tmp.w = clamp(Src.z, -128+eps, 128-eps);
 282         emit2(t->Program, OPCODE_MAX,
 283                 dstregtmpmask(temp, WRITEMASK_XYW),
 284                 inst->SrcReg[0],
 285                 swizzle(srcreg(PROGRAM_CONSTANT, constant),
 286                         SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, constant_swizzle&3));
 287         emit2(t->Program, OPCODE_MIN,
 288                 dstregtmpmask(temp, WRITEMASK_Z),
 289                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 290                 negate(srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle)));
 291
 292         // tmp.w = Pow(tmp.y, tmp.w)
 293         emit1(t->Program, OPCODE_LG2,
 294                 dstregtmpmask(temp, WRITEMASK_W),
 295                 swizzle(srctemp, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
 296         emit2(t->Program, OPCODE_MUL,
 297                 dstregtmpmask(temp, WRITEMASK_W),
 298                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 299                 swizzle(srctemp, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z));
 300         emit1(t->Program, OPCODE_EX2,
 301                 dstregtmpmask(temp, WRITEMASK_W),
 302                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 303
 304         // tmp.z = (tmp.x > 0) ? tmp.w : 0.0
 305         emit3(t->Program, OPCODE_CMP,
 306                 dstregtmpmask(temp, WRITEMASK_Z),
 307                 negate(swizzle(srctemp, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 308                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 309                 builtin_zero);
 310
 311         // tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0
 312         emit1(t->Program, OPCODE_MOV,
 313                 dstregtmpmask(temp, WRITEMASK_XYW),
 314                 swizzle(srctemp, SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE));
 315
 316         if (needTemporary)
 317                 emit1(t->Program, OPCODE_MOV, inst->DstReg, srctemp);
 318 }
 319
 320 static void transform_LRP(struct radeon_transform_context* t,
 321         struct prog_instruction* inst)
 322 {
 323         int tempreg = radeonFindFreeTemporary(t);
 324
 325         emit2(t->Program, OPCODE_ADD,
 326                 dstreg(PROGRAM_TEMPORARY, tempreg),
 327                 inst->SrcReg[1], negate(inst->SrcReg[2]));
 328         emit3(t->Program, OPCODE_MAD,
 329                 inst->DstReg,
 330                 inst->SrcReg[0], srcreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[2]);
 331 }
 332
 333 static void transform_POW(struct radeon_transform_context* t,
 334         struct prog_instruction* inst)
 335 {
 336         int tempreg = radeonFindFreeTemporary(t);
 337         struct prog_dst_register tempdst = dstreg(PROGRAM_TEMPORARY, tempreg);
 338         struct prog_src_register tempsrc = srcreg(PROGRAM_TEMPORARY, tempreg);
 339         tempdst.WriteMask = WRITEMASK_W;
 340         tempsrc.Swizzle = SWIZZLE_WWWW;
 341
 342         emit1(t->Program, OPCODE_LG2, tempdst, scalar(inst->SrcReg[0]));
 343         emit2(t->Program, OPCODE_MUL, tempdst, tempsrc, scalar(inst->SrcReg[1]));
 344         emit1(t->Program, OPCODE_EX2, inst->DstReg, tempsrc);
 345 }
 346
 347 static void transform_RSQ(struct radeon_transform_context* t,
 348         struct prog_instruction* inst)
 349 {
 350         emit1(t->Program, OPCODE_RSQ, inst->DstReg, absolute(inst->SrcReg[0]));
 351 }
 352
 353 static void transform_SGE(struct radeon_transform_context* t,
 354         struct prog_instruction* inst)
 355 {
 356         int tempreg = radeonFindFreeTemporary(t);
 357
 358         emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
 359         emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one);
 360 }
 361
 362 static void transform_SLT(struct radeon_transform_context* t,
 363         struct prog_instruction* inst)
 364 {
 365         int tempreg = radeonFindFreeTemporary(t);
 366
 367         emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
 368         emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero);
 369 }
 370
 371 static void transform_SUB(struct radeon_transform_context* t,
 372         struct prog_instruction* inst)
 373 {
 374         emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1]));
 375 }
 376
 377 static void transform_SWZ(struct radeon_transform_context* t,
 378         struct prog_instruction* inst)
 379 {
 380         emit1(t->Program, OPCODE_MOV, inst->DstReg, inst->SrcReg[0]);
 381 }
 382
 383 static void transform_XPD(struct radeon_transform_context* t,
 384         struct prog_instruction* inst)
 385 {
 386         int tempreg = radeonFindFreeTemporary(t);
 387
 388         emit2(t->Program, OPCODE_MUL, dstreg(PROGRAM_TEMPORARY, tempreg),
 389                 swizzle(inst->SrcReg[0], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
 390                 swizzle(inst->SrcReg[1], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W));
 391         emit3(t->Program, OPCODE_MAD, inst->DstReg,
 392                 swizzle(inst->SrcReg[0], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W),
 393                 swizzle(inst->SrcReg[1], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
 394                 negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
 395 }
 396
 397
 398 /**
 399  * Can be used as a transformation for @ref radeonClauseLocalTransform,
 400  * no userData necessary.
 401  *
 402  * Eliminates the following ALU instructions:
 403  *  ABS, DPH, DST, FLR, LIT, LRP, POW, SGE, SLT, SUB, SWZ, XPD
 404  * using:
 405  *  MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
 406  *
 407  * Transforms RSQ to Radeon's native RSQ by explicitly setting
 408  * absolute value.
 409  *
 410  * @note should be applicable to R300 and R500 fragment programs.
 411  */
 412 GLboolean radeonTransformALU(struct radeon_transform_context* t,
 413         struct prog_instruction* inst,
 414         void* unused)
 415 {
 416         switch(inst->Opcode) {
 417         case OPCODE_ABS: transform_ABS(t, inst); return GL_TRUE;
 418         case OPCODE_DPH: transform_DPH(t, inst); return GL_TRUE;
 419         case OPCODE_DST: transform_DST(t, inst); return GL_TRUE;
 420         case OPCODE_FLR: transform_FLR(t, inst); return GL_TRUE;
 421         case OPCODE_LIT: transform_LIT(t, inst); return GL_TRUE;
 422         case OPCODE_LRP: transform_LRP(t, inst); return GL_TRUE;
 423         case OPCODE_POW: transform_POW(t, inst); return GL_TRUE;
 424         case OPCODE_RSQ: transform_RSQ(t, inst); return GL_TRUE;
 425         case OPCODE_SGE: transform_SGE(t, inst); return GL_TRUE;
 426         case OPCODE_SLT: transform_SLT(t, inst); return GL_TRUE;
 427         case OPCODE_SUB: transform_SUB(t, inst); return GL_TRUE;
 428         case OPCODE_SWZ: transform_SWZ(t, inst); return GL_TRUE;
 429         case OPCODE_XPD: transform_XPD(t, inst); return GL_TRUE;
 430         default:
 431                 return GL_FALSE;
 432         }
 433 }
 434
 435
 436 static void sincos_constants(struct radeon_transform_context* t, GLuint *constants)
 437 {
 438         static const GLfloat SinCosConsts[2][4] = {
 439                 {
 440                         1.273239545,            // 4/PI
 441                         -0.405284735,           // -4/(PI*PI)
 442                         3.141592654,            // PI
 443                         0.2225                  // weight
 444                 },
 445                 {
 446                         0.75,
 447                         0.5,
 448                         0.159154943,            // 1/(2*PI)
 449                         6.283185307             // 2*PI
 450                 }
 451         };
 452         int i;
 453
 454         for(i = 0; i < 2; ++i) {
 455                 GLuint swz;
 456                 constants[i] = _mesa_add_unnamed_constant(t->Program->Parameters, SinCosConsts[i], 4, &swz);
 457                 ASSERT(swz == SWIZZLE_NOOP);
 458         }
 459 }
 460
 461 /**
 462  * Approximate sin(x), where x is clamped to (-pi/2, pi/2).
 463  *
 464  * MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
 465  * MAD tmp.x, tmp.y, |src|, tmp.x
 466  * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
 467  * MAD dest, tmp.y, weight, tmp.x
 468  */
 469 static void sin_approx(struct radeon_transform_context* t,
 470         struct prog_dst_register dst, struct prog_src_register src, const GLuint* constants)
 471 {
 472         GLuint tempreg = radeonFindFreeTemporary(t);
 473
 474         emit2(t->Program, OPCODE_MUL, dstregtmpmask(tempreg, WRITEMASK_XY),
 475                 swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 476                 srcreg(PROGRAM_CONSTANT, constants[0]));
 477         emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_X),
 478                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 479                 absolute(swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 480                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 481         emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_Y),
 482                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 483                 absolute(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 484                 negate(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)));
 485         emit3(t->Program, OPCODE_MAD, dst,
 486                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 487                 swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 488                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 489 }
 490
 491 /**
 492  * Translate the trigonometric functions COS, SIN, and SCS
 493  * using only the basic instructions
 494  *  MOV, ADD, MUL, MAD, FRC
 495  */
 496 GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t,
 497         struct prog_instruction* inst,
 498         void* unused)
 499 {
 500         if (inst->Opcode != OPCODE_COS &&
 501             inst->Opcode != OPCODE_SIN &&
 502             inst->Opcode != OPCODE_SCS)
 503                 return GL_FALSE;
 504
 505         GLuint constants[2];
 506         GLuint tempreg = radeonFindFreeTemporary(t);
 507
 508         sincos_constants(t, constants);
 509
 510         if (inst->Opcode == OPCODE_COS) {
 511                 // MAD tmp.x, src, 1/(2*PI), 0.75
 512                 // FRC tmp.x, tmp.x
 513                 // MAD tmp.z, tmp.x, 2*PI, -PI
 514                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 515                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 516                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 517                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 518                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
 519                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 520                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 521                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 522                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 523                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 524
 525                 sin_approx(t, inst->DstReg,
 526                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 527                         constants);
 528         } else if (inst->Opcode == OPCODE_SIN) {
 529                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 530                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 531                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 532                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
 533                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
 534                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 535                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 536                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 537                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 538                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 539
 540                 sin_approx(t, inst->DstReg,
 541                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 542                         constants);
 543         } else {
 544                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
 545                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 546                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 547                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W));
 548                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_XY),
 549                         srcreg(PROGRAM_TEMPORARY, tempreg));
 550                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
 551                         srcreg(PROGRAM_TEMPORARY, tempreg),
 552                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 553                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 554
 555                 struct prog_dst_register dst = inst->DstReg;
 556
 557                 dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_X;
 558                 sin_approx(t, dst,
 559                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 560                         constants);
 561
 562                 dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_Y;
 563                 sin_approx(t, dst,
 564                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 565                         constants);
 566         }
 567
 568         return GL_TRUE;
 569 }
 570
 571
 572 /**
 573  * Transform the trigonometric functions COS, SIN, and SCS
 574  * to include pre-scaling by 1/(2*PI) and taking the fractional
 575  * part, so that the input to COS and SIN is always in the range [0,1).
 576  * SCS is replaced by one COS and one SIN instruction.
 577  *
 578  * @warning This transformation implicitly changes the semantics of SIN and COS!
 579  */
 580 GLboolean radeonTransformTrigScale(struct radeon_transform_context* t,
 581         struct prog_instruction* inst,
 582         void* unused)
 583 {
 584         if (inst->Opcode != OPCODE_COS &&
 585             inst->Opcode != OPCODE_SIN &&
 586             inst->Opcode != OPCODE_SCS)
 587                 return GL_FALSE;
 588
 589         static const GLfloat RCP_2PI[] = { 0.15915494309189535 };
 590         GLuint temp;
 591         GLuint constant;
 592         GLuint constant_swizzle;
 593
 594         temp = radeonFindFreeTemporary(t);
 595         constant = _mesa_add_unnamed_constant(t->Program->Parameters, RCP_2PI, 1, &constant_swizzle);
 596
 597         emit2(t->Program, OPCODE_MUL, dstregtmpmask(temp, WRITEMASK_W),
 598                 swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 599                 srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle));
 600         emit1(t->Program, OPCODE_FRC, dstregtmpmask(temp, WRITEMASK_W),
 601                 srcreg(PROGRAM_TEMPORARY, temp));
 602
 603         if (inst->Opcode == OPCODE_COS) {
 604                 emit1(t->Program, OPCODE_COS, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 605         } else if (inst->Opcode == OPCODE_SIN) {
 606                 emit1(t->Program, OPCODE_SIN, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 607         } else if (inst->Opcode == OPCODE_SCS) {
 608                 struct prog_dst_register moddst = inst->DstReg;
 609
 610                 if (inst->DstReg.WriteMask & WRITEMASK_X) {
 611                         moddst.WriteMask = WRITEMASK_X;
 612                         emit1(t->Program, OPCODE_COS, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 613                 }
 614                 if (inst->DstReg.WriteMask & WRITEMASK_Y) {
 615                         moddst.WriteMask = WRITEMASK_Y;
 616                         emit1(t->Program, OPCODE_SIN, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 617                 }
 618         }
 619
 620         return GL_TRUE;
 621 }