src/mesa/drivers/dri/r300/radeon_program_alu.c

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * @file
  30  *
  31  * Shareable transformations that transform "special" ALU instructions
  32  * into ALU instructions that are supported by hardware.
  33  *
  34  */
  35
  36 #include "radeon_program_alu.h"
  37
  38 #include "shader/prog_parameter.h"
  39
  40
  41 static struct prog_instruction *emit1(struct gl_program* p,
  42         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  43         struct prog_src_register SrcReg)
  44 {
  45         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  46
  47         fpi->Opcode = Opcode;
  48         fpi->DstReg = DstReg;
  49         fpi->SrcReg[0] = SrcReg;
  50         return fpi;
  51 }
  52
  53 static struct prog_instruction *emit2(struct gl_program* p,
  54         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  55         struct prog_src_register SrcReg0, struct prog_src_register SrcReg1)
  56 {
  57         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  58
  59         fpi->Opcode = Opcode;
  60         fpi->DstReg = DstReg;
  61         fpi->SrcReg[0] = SrcReg0;
  62         fpi->SrcReg[1] = SrcReg1;
  63         return fpi;
  64 }
  65
  66 static struct prog_instruction *emit3(struct gl_program* p,
  67         gl_inst_opcode Opcode, struct prog_dst_register DstReg,
  68         struct prog_src_register SrcReg0, struct prog_src_register SrcReg1,
  69         struct prog_src_register SrcReg2)
  70 {
  71         struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
  72
  73         fpi->Opcode = Opcode;
  74         fpi->DstReg = DstReg;
  75         fpi->SrcReg[0] = SrcReg0;
  76         fpi->SrcReg[1] = SrcReg1;
  77         fpi->SrcReg[2] = SrcReg2;
  78         return fpi;
  79 }
  80
  81 static void set_swizzle(struct prog_src_register *SrcReg, int coordinate, int swz)
  82 {
  83         SrcReg->Swizzle &= ~(7 << (3*coordinate));
  84         SrcReg->Swizzle |= swz << (3*coordinate);
  85 }
  86
  87 static void set_negate_base(struct prog_src_register *SrcReg, int coordinate, int negate)
  88 {
  89         SrcReg->NegateBase &= ~(1 << coordinate);
  90         SrcReg->NegateBase |= (negate << coordinate);
  91 }
  92
  93 static struct prog_dst_register dstreg(int file, int index)
  94 {
  95         struct prog_dst_register dst;
  96         dst.File = file;
  97         dst.Index = index;
  98         dst.WriteMask = WRITEMASK_XYZW;
  99         dst.CondMask = COND_TR;
 100         dst.CondSwizzle = SWIZZLE_NOOP;
 101         dst.CondSrc = 0;
 102         dst.pad = 0;
 103         return dst;
 104 }
 105
 106 static struct prog_dst_register dstregtmpmask(int index, int mask)
 107 {
 108         struct prog_dst_register dst;
 109         dst.File = PROGRAM_TEMPORARY;
 110         dst.Index = index;
 111         dst.WriteMask = mask;
 112         dst.CondMask = COND_TR;
 113         dst.CondSwizzle = SWIZZLE_NOOP;
 114         dst.CondSrc = 0;
 115         dst.pad = 0;
 116         return dst;
 117 }
 118
 119 static const struct prog_src_register builtin_zero = {
 120         .File = PROGRAM_BUILTIN,
 121         .Index = 0,
 122         .Swizzle = SWIZZLE_0000
 123 };
 124 static const struct prog_src_register builtin_one = {
 125         .File = PROGRAM_BUILTIN,
 126         .Index = 0,
 127         .Swizzle = SWIZZLE_1111
 128 };
 129 static const struct prog_src_register srcreg_undefined = {
 130         .File = PROGRAM_UNDEFINED,
 131         .Index = 0,
 132         .Swizzle = SWIZZLE_NOOP
 133 };
 134
 135 static struct prog_src_register srcreg(int file, int index)
 136 {
 137         struct prog_src_register src = srcreg_undefined;
 138         src.File = file;
 139         src.Index = index;
 140         return src;
 141 }
 142
 143 static struct prog_src_register srcregswz(int file, int index, int swz)
 144 {
 145         struct prog_src_register src = srcreg_undefined;
 146         src.File = file;
 147         src.Index = index;
 148         src.Swizzle = swz;
 149         return src;
 150 }
 151
 152 static struct prog_src_register absolute(struct prog_src_register reg)
 153 {
 154         struct prog_src_register newreg = reg;
 155         newreg.Abs = 1;
 156         newreg.NegateAbs = 0;
 157         return newreg;
 158 }
 159
 160 static struct prog_src_register negate(struct prog_src_register reg)
 161 {
 162         struct prog_src_register newreg = reg;
 163         newreg.NegateAbs = !newreg.NegateAbs;
 164         return newreg;
 165 }
 166
 167 static struct prog_src_register swizzle(struct prog_src_register reg, GLuint x, GLuint y, GLuint z, GLuint w)
 168 {
 169         struct prog_src_register swizzled = reg;
 170         swizzled.Swizzle = MAKE_SWIZZLE4(
 171                 x >= 4 ? x : GET_SWZ(reg.Swizzle, x),
 172                 y >= 4 ? y : GET_SWZ(reg.Swizzle, y),
 173                 z >= 4 ? z : GET_SWZ(reg.Swizzle, z),
 174                 w >= 4 ? w : GET_SWZ(reg.Swizzle, w));
 175         return swizzled;
 176 }
 177
 178 static struct prog_src_register scalar(struct prog_src_register reg)
 179 {
 180         return swizzle(reg, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X);
 181 }
 182
 183 static void transform_ABS(struct radeon_transform_context* t,
 184         struct prog_instruction* inst)
 185 {
 186         struct prog_src_register src = inst->SrcReg[0];
 187         src.Abs = 1;
 188         src.NegateBase = 0;
 189         src.NegateAbs = 0;
 190         emit1(t->Program, OPCODE_MOV, inst->DstReg, src);
 191 }
 192
 193 static void transform_DPH(struct radeon_transform_context* t,
 194         struct prog_instruction* inst)
 195 {
 196         struct prog_src_register src0 = inst->SrcReg[0];
 197         if (src0.NegateAbs) {
 198                 if (src0.Abs) {
 199                         int tempreg = radeonFindFreeTemporary(t);
 200                         emit1(t->Program, OPCODE_MOV, dstreg(PROGRAM_TEMPORARY, tempreg), src0);
 201                         src0 = srcreg(src0.File, src0.Index);
 202                 } else {
 203                         src0.NegateAbs = 0;
 204                         src0.NegateBase ^= NEGATE_XYZW;
 205                 }
 206         }
 207         set_swizzle(&src0, 3, SWIZZLE_ONE);
 208         set_negate_base(&src0, 3, 0);
 209         emit2(t->Program, OPCODE_DP4, inst->DstReg, src0, inst->SrcReg[1]);
 210 }
 211
 212 /**
 213  * [1, src0.y*src1.y, src0.z, src1.w]
 214  * So basically MUL with lotsa swizzling.
 215  */
 216 static void transform_DST(struct radeon_transform_context* t,
 217         struct prog_instruction* inst)
 218 {
 219         emit2(t->Program, OPCODE_MUL, inst->DstReg,
 220                 swizzle(inst->SrcReg[0], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE),
 221                 swizzle(inst->SrcReg[1], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_W));
 222 }
 223
 224 static void transform_FLR(struct radeon_transform_context* t,
 225         struct prog_instruction* inst)
 226 {
 227         int tempreg = radeonFindFreeTemporary(t);
 228         emit1(t->Program, OPCODE_FRC, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]);
 229         emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
 230 }
 231
 232 /**
 233  * Definition of LIT (from ARB_fragment_program):
 234  *
 235  *  tmp = VectorLoad(op0);
 236  *  if (tmp.x < 0) tmp.x = 0;
 237  *  if (tmp.y < 0) tmp.y = 0;
 238  *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 239  *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 240  *  result.x = 1.0;
 241  *  result.y = tmp.x;
 242  *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 243  *  result.w = 1.0;
 244  *
 245  * The longest path of computation is the one leading to result.z,
 246  * consisting of 5 operations. This implementation of LIT takes
 247  * 5 slots, if the subsequent optimization passes are clever enough
 248  * to pair instructions correctly.
 249  */
 250 static void transform_LIT(struct radeon_transform_context* t,
 251         struct prog_instruction* inst)
 252 {
 253         static const GLfloat LitConst[4] = { -127.999999 };
 254
 255         GLuint constant;
 256         GLuint constant_swizzle;
 257         GLuint temp;
 258         int needTemporary = 0;
 259         struct prog_src_register srctemp;
 260
 261         constant = _mesa_add_unnamed_constant(t->Program->Parameters, LitConst, 1, &constant_swizzle);
 262
 263         if (inst->DstReg.WriteMask != WRITEMASK_XYZW) {
 264                 needTemporary = 1;
 265         } else if (inst->DstReg.File != PROGRAM_TEMPORARY) {
 266                 // LIT is typically followed by DP3/DP4, so there's no point
 267                 // in creating special code for this case
 268                 needTemporary = 1;
 269         }
 270
 271         if (needTemporary) {
 272                 temp = radeonFindFreeTemporary(t);
 273         } else {
 274                 temp = inst->DstReg.Index;
 275         }
 276         srctemp = srcreg(PROGRAM_TEMPORARY, temp);
 277
 278         // tmp.x = max(0.0, Src.x);
 279         // tmp.y = max(0.0, Src.y);
 280         // tmp.w = clamp(Src.z, -128+eps, 128-eps);
 281         emit2(t->Program, OPCODE_MAX,
 282                 dstregtmpmask(temp, WRITEMASK_XYW),
 283                 inst->SrcReg[0],
 284                 swizzle(srcreg(PROGRAM_CONSTANT, constant),
 285                         SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, constant_swizzle&3));
 286         emit2(t->Program, OPCODE_MIN,
 287                 dstregtmpmask(temp, WRITEMASK_Z),
 288                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 289                 negate(srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle)));
 290
 291         // tmp.w = Pow(tmp.y, tmp.w)
 292         emit1(t->Program, OPCODE_LG2,
 293                 dstregtmpmask(temp, WRITEMASK_W),
 294                 swizzle(srctemp, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
 295         emit2(t->Program, OPCODE_MUL,
 296                 dstregtmpmask(temp, WRITEMASK_W),
 297                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 298                 swizzle(srctemp, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z));
 299         emit1(t->Program, OPCODE_EX2,
 300                 dstregtmpmask(temp, WRITEMASK_W),
 301                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 302
 303         // tmp.z = (tmp.x > 0) ? tmp.w : 0.0
 304         emit3(t->Program, OPCODE_CMP,
 305                 dstregtmpmask(temp, WRITEMASK_Z),
 306                 negate(swizzle(srctemp, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 307                 swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 308                 builtin_zero);
 309
 310         // tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0
 311         emit1(t->Program, OPCODE_MOV,
 312                 dstregtmpmask(temp, WRITEMASK_XYW),
 313                 swizzle(srctemp, SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE));
 314
 315         if (needTemporary)
 316                 emit1(t->Program, OPCODE_MOV, inst->DstReg, srctemp);
 317 }
 318
 319 static void transform_LRP(struct radeon_transform_context* t,
 320         struct prog_instruction* inst)
 321 {
 322         int tempreg = radeonFindFreeTemporary(t);
 323
 324         emit2(t->Program, OPCODE_ADD,
 325                 dstreg(PROGRAM_TEMPORARY, tempreg),
 326                 inst->SrcReg[1], negate(inst->SrcReg[2]));
 327         emit3(t->Program, OPCODE_MAD,
 328                 inst->DstReg,
 329                 inst->SrcReg[0], srcreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[2]);
 330 }
 331
 332 static void transform_POW(struct radeon_transform_context* t,
 333         struct prog_instruction* inst)
 334 {
 335         int tempreg = radeonFindFreeTemporary(t);
 336         struct prog_dst_register tempdst = dstreg(PROGRAM_TEMPORARY, tempreg);
 337         struct prog_src_register tempsrc = srcreg(PROGRAM_TEMPORARY, tempreg);
 338         tempdst.WriteMask = WRITEMASK_W;
 339         tempsrc.Swizzle = SWIZZLE_WWWW;
 340
 341         emit1(t->Program, OPCODE_LG2, tempdst, scalar(inst->SrcReg[0]));
 342         emit2(t->Program, OPCODE_MUL, tempdst, tempsrc, scalar(inst->SrcReg[1]));
 343         emit1(t->Program, OPCODE_EX2, inst->DstReg, tempsrc);
 344 }
 345
 346 static void transform_SGE(struct radeon_transform_context* t,
 347         struct prog_instruction* inst)
 348 {
 349         int tempreg = radeonFindFreeTemporary(t);
 350
 351         emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
 352         emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one);
 353 }
 354
 355 static void transform_SLT(struct radeon_transform_context* t,
 356         struct prog_instruction* inst)
 357 {
 358         int tempreg = radeonFindFreeTemporary(t);
 359
 360         emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
 361         emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero);
 362 }
 363
 364 static void transform_SUB(struct radeon_transform_context* t,
 365         struct prog_instruction* inst)
 366 {
 367         emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1]));
 368 }
 369
 370 static void transform_SWZ(struct radeon_transform_context* t,
 371         struct prog_instruction* inst)
 372 {
 373         emit1(t->Program, OPCODE_MOV, inst->DstReg, inst->SrcReg[0]);
 374 }
 375
 376 static void transform_XPD(struct radeon_transform_context* t,
 377         struct prog_instruction* inst)
 378 {
 379         int tempreg = radeonFindFreeTemporary(t);
 380
 381         emit2(t->Program, OPCODE_MUL, dstreg(PROGRAM_TEMPORARY, tempreg),
 382                 swizzle(inst->SrcReg[0], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
 383                 swizzle(inst->SrcReg[1], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W));
 384         emit3(t->Program, OPCODE_MAD, inst->DstReg,
 385                 swizzle(inst->SrcReg[0], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W),
 386                 swizzle(inst->SrcReg[1], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
 387                 negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
 388 }
 389
 390
 391 /**
 392  * Can be used as a transformation for @ref radeonClauseLocalTransform,
 393  * no userData necessary.
 394  *
 395  * Eliminates the following ALU instructions:
 396  *  ABS, DPH, DST, FLR, LIT, LRP, POW, SGE, SLT, SUB, SWZ, XPD
 397  * using:
 398  *  MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
 399  *
 400  * @note should be applicable to R300 and R500 fragment programs.
 401  */
 402 GLboolean radeonTransformALU(struct radeon_transform_context* t,
 403         struct prog_instruction* inst,
 404         void* unused)
 405 {
 406         switch(inst->Opcode) {
 407         case OPCODE_ABS: transform_ABS(t, inst); return GL_TRUE;
 408         case OPCODE_DPH: transform_DPH(t, inst); return GL_TRUE;
 409         case OPCODE_DST: transform_DST(t, inst); return GL_TRUE;
 410         case OPCODE_FLR: transform_FLR(t, inst); return GL_TRUE;
 411         case OPCODE_LIT: transform_LIT(t, inst); return GL_TRUE;
 412         case OPCODE_LRP: transform_LRP(t, inst); return GL_TRUE;
 413         case OPCODE_POW: transform_POW(t, inst); return GL_TRUE;
 414         case OPCODE_SGE: transform_SGE(t, inst); return GL_TRUE;
 415         case OPCODE_SLT: transform_SLT(t, inst); return GL_TRUE;
 416         case OPCODE_SUB: transform_SUB(t, inst); return GL_TRUE;
 417         case OPCODE_SWZ: transform_SWZ(t, inst); return GL_TRUE;
 418         case OPCODE_XPD: transform_XPD(t, inst); return GL_TRUE;
 419         default:
 420                 return GL_FALSE;
 421         }
 422 }
 423
 424
 425 static void sincos_constants(struct radeon_transform_context* t, GLuint *constants)
 426 {
 427         static const GLfloat SinCosConsts[2][4] = {
 428                 {
 429                         1.273239545,            // 4/PI
 430                         -0.405284735,           // -4/(PI*PI)
 431                         3.141592654,            // PI
 432                         0.2225                  // weight
 433                 },
 434                 {
 435                         0.75,
 436                         0.5,
 437                         0.159154943,            // 1/(2*PI)
 438                         6.283185307             // 2*PI
 439                 }
 440         };
 441         int i;
 442
 443         for(i = 0; i < 2; ++i) {
 444                 GLuint swz;
 445                 constants[i] = _mesa_add_unnamed_constant(t->Program->Parameters, SinCosConsts[i], 4, &swz);
 446                 ASSERT(swz == SWIZZLE_NOOP);
 447         }
 448 }
 449
 450 /**
 451  * Approximate sin(x), where x is clamped to (-pi/2, pi/2).
 452  *
 453  * MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
 454  * MAD tmp.x, tmp.y, |src|, tmp.x
 455  * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
 456  * MAD dest, tmp.y, weight, tmp.x
 457  */
 458 static void sin_approx(struct radeon_transform_context* t,
 459         struct prog_dst_register dst, struct prog_src_register src, const GLuint* constants)
 460 {
 461         GLuint tempreg = radeonFindFreeTemporary(t);
 462
 463         emit2(t->Program, OPCODE_MUL, dstregtmpmask(tempreg, WRITEMASK_XY),
 464                 swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 465                 srcreg(PROGRAM_CONSTANT, constants[0]));
 466         emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_X),
 467                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 468                 absolute(swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 469                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 470         emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_Y),
 471                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 472                 absolute(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
 473                 negate(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)));
 474         emit3(t->Program, OPCODE_MAD, dst,
 475                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 476                 swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 477                 swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 478 }
 479
 480 /**
 481  * Translate the trigonometric functions COS, SIN, and SCS
 482  * using only the basic instructions
 483  *  MOV, ADD, MUL, MAD, FRC
 484  */
 485 GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t,
 486         struct prog_instruction* inst,
 487         void* unused)
 488 {
 489         if (inst->Opcode != OPCODE_COS &&
 490             inst->Opcode != OPCODE_SIN &&
 491             inst->Opcode != OPCODE_SCS)
 492                 return GL_FALSE;
 493
 494         GLuint constants[2];
 495         GLuint tempreg = radeonFindFreeTemporary(t);
 496
 497         sincos_constants(t, constants);
 498
 499         if (inst->Opcode == OPCODE_COS) {
 500                 // MAD tmp.x, src, 1/(2*PI), 0.75
 501                 // FRC tmp.x, tmp.x
 502                 // MAD tmp.z, tmp.x, 2*PI, -PI
 503                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 504                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 505                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 506                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
 507                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
 508                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 509                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 510                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 511                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 512                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 513
 514                 sin_approx(t, inst->DstReg,
 515                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 516                         constants);
 517         } else if (inst->Opcode == OPCODE_SIN) {
 518                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 519                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 520                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 521                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
 522                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
 523                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
 524                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
 525                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 526                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 527                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 528
 529                 sin_approx(t, inst->DstReg,
 530                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 531                         constants);
 532         } else {
 533                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
 534                         swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 535                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
 536                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W));
 537                 emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_XY),
 538                         srcreg(PROGRAM_TEMPORARY, tempreg));
 539                 emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
 540                         srcreg(PROGRAM_TEMPORARY, tempreg),
 541                         swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
 542                         negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
 543
 544                 struct prog_dst_register dst = inst->DstReg;
 545
 546                 dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_X;
 547                 sin_approx(t, dst,
 548                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 549                         constants);
 550
 551                 dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_Y;
 552                 sin_approx(t, dst,
 553                         swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
 554                         constants);
 555         }
 556
 557         return GL_TRUE;
 558 }
 559
 560
 561 /**
 562  * Transform the trigonometric functions COS, SIN, and SCS
 563  * to include pre-scaling by 1/(2*PI) and taking the fractional
 564  * part, so that the input to COS and SIN is always in the range [0,1).
 565  * SCS is replaced by one COS and one SIN instruction.
 566  *
 567  * @warning This transformation implicitly changes the semantics of SIN and COS!
 568  */
 569 GLboolean radeonTransformTrigScale(struct radeon_transform_context* t,
 570         struct prog_instruction* inst,
 571         void* unused)
 572 {
 573         if (inst->Opcode != OPCODE_COS &&
 574             inst->Opcode != OPCODE_SIN &&
 575             inst->Opcode != OPCODE_SCS)
 576                 return GL_FALSE;
 577
 578         static const GLfloat RCP_2PI[] = { 0.15915494309189535 };
 579         GLuint temp;
 580         GLuint constant;
 581         GLuint constant_swizzle;
 582
 583         temp = radeonFindFreeTemporary(t);
 584         constant = _mesa_add_unnamed_constant(t->Program->Parameters, RCP_2PI, 1, &constant_swizzle);
 585
 586         emit2(t->Program, OPCODE_MUL, dstregtmpmask(temp, WRITEMASK_W),
 587                 swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
 588                 srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle));
 589         emit1(t->Program, OPCODE_FRC, dstregtmpmask(temp, WRITEMASK_W),
 590                 srcreg(PROGRAM_TEMPORARY, temp));
 591
 592         if (inst->Opcode == OPCODE_COS) {
 593                 emit1(t->Program, OPCODE_COS, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 594         } else if (inst->Opcode == OPCODE_SIN) {
 595                 emit1(t->Program, OPCODE_SIN, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 596         } else if (inst->Opcode == OPCODE_SCS) {
 597                 struct prog_dst_register moddst = inst->DstReg;
 598
 599                 if (inst->DstReg.WriteMask & WRITEMASK_X) {
 600                         moddst.WriteMask = WRITEMASK_X;
 601                         emit1(t->Program, OPCODE_COS, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 602                 }
 603                 if (inst->DstReg.WriteMask & WRITEMASK_Y) {
 604                         moddst.WriteMask = WRITEMASK_Y;
 605                         emit1(t->Program, OPCODE_SIN, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
 606                 }
 607         }
 608
 609         return GL_TRUE;
 610 }