2 * Copyright (C) 2008 Nicolai Haehnle.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Perform temporary register allocation and attempt to pair off instructions
32 * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction
33 * vs. ALU instruction scheduling.
36 #include "radeon_program_pair.h"
38 #include "radeon_common.h"
40 #include "shader/prog_print.h"
42 #define error(fmt, args...) do { \
43 _mesa_problem(s->Ctx, "%s::%s(): " fmt "\n", \
44 __FILE__, __FUNCTION__, ##args); \
48 struct pair_state_instruction
{
49 GLuint IsTex
:1; /**< Is a texture instruction */
50 GLuint NeedRGB
:1; /**< Needs the RGB ALU */
51 GLuint NeedAlpha
:1; /**< Needs the Alpha ALU */
52 GLuint IsTranscendent
:1; /**< Is a special transcendent instruction */
55 * Number of (read and write) dependencies that must be resolved before
56 * this instruction can be scheduled.
58 GLuint NumDependencies
:5;
61 * Next instruction in the linked list of ready instructions.
63 struct pair_state_instruction
*NextReady
;
66 * Values that this instruction writes
68 struct reg_value
*Values
[4];
73 * Used to keep track of which instructions read a value.
75 struct reg_value_reader
{
76 GLuint IP
; /**< IP of the instruction that performs this access */
77 struct reg_value_reader
*Next
;
81 * Used to keep track which values are stored in each component of a
85 GLuint IP
; /**< IP of the instruction that writes this value */
86 struct reg_value
*Next
; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */
89 * Unordered linked list of instructions that read from this value.
91 struct reg_value_reader
*Readers
;
94 * Number of readers of this value. This is calculated during @ref scan_instructions
95 * and continually decremented during code emission.
96 * When this count reaches zero, the instruction that writes the @ref Next value
103 * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register
104 * to the proper hardware temporary.
106 struct pair_register_translation
{
109 GLuint RefCount
:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */
112 * Notes the value that is currently contained in each component
113 * (only used for PROGRAM_TEMPORARY registers).
115 struct reg_value
*Value
[4];
120 struct gl_program
*Program
;
121 const struct radeon_pair_handler
*Handler
;
128 * Translate Mesa registers to hardware registers
130 struct pair_register_translation Inputs
[FRAG_ATTRIB_MAX
];
131 struct pair_register_translation Temps
[MAX_PROGRAM_TEMPS
];
134 * Derived information about program instructions.
136 struct pair_state_instruction
*Instructions
;
139 GLuint RefCount
; /**< # of times this occurs in an unscheduled SrcReg or DstReg */
143 * Linked list of instructions that can be scheduled right now,
144 * based on which ALU/TEX resources they require.
146 struct pair_state_instruction
*ReadyFullALU
;
147 struct pair_state_instruction
*ReadyRGB
;
148 struct pair_state_instruction
*ReadyAlpha
;
149 struct pair_state_instruction
*ReadyTEX
;
152 * Pool of @ref reg_value structures for fast allocation.
154 struct reg_value
*ValuePool
;
155 GLuint ValuePoolUsed
;
156 struct reg_value_reader
*ReaderPool
;
157 GLuint ReaderPoolUsed
;
161 static struct pair_register_translation
*get_register(struct pair_state
*s
, GLuint file
, GLuint index
)
164 case PROGRAM_TEMPORARY
: return &s
->Temps
[index
];
165 case PROGRAM_INPUT
: return &s
->Inputs
[index
];
170 static void alloc_hw_reg(struct pair_state
*s
, GLuint file
, GLuint index
, GLuint hwindex
)
172 struct pair_register_translation
*t
= get_register(s
, file
, index
);
173 ASSERT(!s
->HwTemps
[hwindex
].RefCount
);
174 ASSERT(!t
->Allocated
);
175 s
->HwTemps
[hwindex
].RefCount
= t
->RefCount
;
177 t
->HwIndex
= hwindex
;
180 static GLuint
get_hw_reg(struct pair_state
*s
, GLuint file
, GLuint index
)
184 struct pair_register_translation
*t
= get_register(s
, file
, index
);
186 _mesa_problem(s
->Ctx
, "get_hw_reg: %i[%i]\n", file
, index
);
193 for(hwindex
= 0; hwindex
< s
->Handler
->MaxHwTemps
; ++hwindex
)
194 if (!s
->HwTemps
[hwindex
].RefCount
)
197 if (hwindex
>= s
->Handler
->MaxHwTemps
) {
198 error("Ran out of hardware temporaries");
202 alloc_hw_reg(s
, file
, index
, hwindex
);
207 static void deref_hw_reg(struct pair_state
*s
, GLuint hwindex
)
209 if (!s
->HwTemps
[hwindex
].RefCount
) {
210 error("Hwindex %i refcount error", hwindex
);
214 s
->HwTemps
[hwindex
].RefCount
--;
217 static void add_pairinst_to_list(struct pair_state_instruction
**list
, struct pair_state_instruction
*pairinst
)
219 pairinst
->NextReady
= *list
;
224 * The instruction at the given IP has become ready. Link it into the ready
227 static void instruction_ready(struct pair_state
*s
, int ip
)
229 struct pair_state_instruction
*pairinst
= s
->Instructions
+ ip
;
232 _mesa_printf("instruction_ready(%i)\n", ip
);
235 add_pairinst_to_list(&s
->ReadyTEX
, pairinst
);
236 else if (!pairinst
->NeedAlpha
)
237 add_pairinst_to_list(&s
->ReadyRGB
, pairinst
);
238 else if (!pairinst
->NeedRGB
)
239 add_pairinst_to_list(&s
->ReadyAlpha
, pairinst
);
241 add_pairinst_to_list(&s
->ReadyFullALU
, pairinst
);
246 * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
247 * and reverse the order of arguments for CMP.
249 static void final_rewrite(struct pair_state
*s
, struct prog_instruction
*inst
)
251 struct prog_src_register tmp
;
253 switch(inst
->Opcode
) {
255 inst
->SrcReg
[2] = inst
->SrcReg
[1];
256 inst
->SrcReg
[1].File
= PROGRAM_BUILTIN
;
257 inst
->SrcReg
[1].Swizzle
= SWIZZLE_1111
;
258 inst
->SrcReg
[1].Negate
= NEGATE_NONE
;
259 inst
->Opcode
= OPCODE_MAD
;
262 tmp
= inst
->SrcReg
[2];
263 inst
->SrcReg
[2] = inst
->SrcReg
[0];
264 inst
->SrcReg
[0] = tmp
;
267 /* AMD say we should use CMP.
268 * However, when we transform
271 * CMP tmp, -r0, -r0, 0;
273 * we get incorrect behaviour on R500 when r0 == 0.0.
274 * It appears that the R500 KIL hardware treats -0.0 as less
277 inst
->SrcReg
[1].File
= PROGRAM_BUILTIN
;
278 inst
->SrcReg
[1].Swizzle
= SWIZZLE_1111
;
279 inst
->SrcReg
[2].File
= PROGRAM_BUILTIN
;
280 inst
->SrcReg
[2].Swizzle
= SWIZZLE_0000
;
281 inst
->Opcode
= OPCODE_MAD
;
284 inst
->SrcReg
[2].File
= PROGRAM_BUILTIN
;
285 inst
->SrcReg
[2].Swizzle
= SWIZZLE_0000
;
286 inst
->Opcode
= OPCODE_MAD
;
296 * Classify an instruction according to which ALUs etc. it needs
298 static void classify_instruction(struct pair_state
*s
,
299 struct prog_instruction
*inst
, struct pair_state_instruction
*pairinst
)
301 pairinst
->NeedRGB
= (inst
->DstReg
.WriteMask
& WRITEMASK_XYZ
) ? 1 : 0;
302 pairinst
->NeedAlpha
= (inst
->DstReg
.WriteMask
& WRITEMASK_W
) ? 1 : 0;
304 switch(inst
->Opcode
) {
322 pairinst
->IsTranscendent
= 1;
323 pairinst
->NeedAlpha
= 1;
326 pairinst
->NeedAlpha
= 1;
329 pairinst
->NeedRGB
= 1;
339 error("Unknown opcode %d\n", inst
->Opcode
);
346 * Count which (input, temporary) register is read and written how often,
347 * and scan the instruction stream to find dependencies.
349 static void scan_instructions(struct pair_state
*s
)
351 struct prog_instruction
*inst
;
352 struct pair_state_instruction
*pairinst
;
355 for(inst
= s
->Program
->Instructions
, pairinst
= s
->Instructions
, ip
= 0;
356 inst
->Opcode
!= OPCODE_END
;
357 ++inst
, ++pairinst
, ++ip
) {
358 final_rewrite(s
, inst
);
359 classify_instruction(s
, inst
, pairinst
);
361 int nsrc
= _mesa_num_inst_src_regs(inst
->Opcode
);
363 for(j
= 0; j
< nsrc
; j
++) {
364 struct pair_register_translation
*t
=
365 get_register(s
, inst
->SrcReg
[j
].File
, inst
->SrcReg
[j
].Index
);
371 if (inst
->SrcReg
[j
].File
== PROGRAM_TEMPORARY
) {
373 for(i
= 0; i
< 4; ++i
) {
374 GLuint swz
= GET_SWZ(inst
->SrcReg
[j
].Swizzle
, i
);
376 continue; /* constant or NIL swizzle */
378 continue; /* this is an undefined read */
380 /* Do not add a dependency if this instruction
381 * also rewrites the value. The code below adds
382 * a dependency for the DstReg, which is a superset
383 * of the SrcReg dependency. */
384 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
&&
385 inst
->DstReg
.Index
== inst
->SrcReg
[j
].Index
&&
386 GET_BIT(inst
->DstReg
.WriteMask
, swz
))
389 struct reg_value_reader
* r
= &s
->ReaderPool
[s
->ReaderPoolUsed
++];
390 pairinst
->NumDependencies
++;
391 t
->Value
[swz
]->NumReaders
++;
393 r
->Next
= t
->Value
[swz
]->Readers
;
394 t
->Value
[swz
]->Readers
= r
;
399 int ndst
= _mesa_num_inst_dst_regs(inst
->Opcode
);
401 struct pair_register_translation
*t
=
402 get_register(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
406 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
) {
408 for(j
= 0; j
< 4; ++j
) {
409 if (!GET_BIT(inst
->DstReg
.WriteMask
, j
))
412 struct reg_value
* v
= &s
->ValuePool
[s
->ValuePoolUsed
++];
415 pairinst
->NumDependencies
++;
416 t
->Value
[j
]->Next
= v
;
419 pairinst
->Values
[j
] = v
;
426 _mesa_printf("scan(%i): NumDeps = %i\n", ip
, pairinst
->NumDependencies
);
428 if (!pairinst
->NumDependencies
)
429 instruction_ready(s
, ip
);
432 /* Clear the PROGRAM_TEMPORARY state */
434 for(i
= 0; i
< MAX_PROGRAM_TEMPS
; ++i
) {
435 for(j
= 0; j
< 4; ++j
)
436 s
->Temps
[i
].Value
[j
] = 0;
442 * Reserve hardware temporary registers for the program inputs.
444 * @note This allocation is performed explicitly, because the order of inputs
445 * is determined by the RS hardware.
447 static void allocate_input_registers(struct pair_state
*s
)
449 GLuint InputsRead
= s
->Program
->InputsRead
;
454 if (InputsRead
& FRAG_BIT_COL0
)
455 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_COL0
, hwindex
++);
456 InputsRead
&= ~FRAG_BIT_COL0
;
458 /* Secondary color */
459 if (InputsRead
& FRAG_BIT_COL1
)
460 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_COL1
, hwindex
++);
461 InputsRead
&= ~FRAG_BIT_COL1
;
464 for (i
= 0; i
< s
->Ctx
->Const
.MaxTextureUnits
; i
++) {
465 if (InputsRead
& (FRAG_BIT_TEX0
<< i
))
466 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_TEX0
+i
, hwindex
++);
468 InputsRead
&= ~FRAG_BITS_TEX_ANY
;
470 /* Fogcoords treated as a texcoord */
471 if (InputsRead
& FRAG_BIT_FOGC
)
472 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_FOGC
, hwindex
++);
473 InputsRead
&= ~FRAG_BIT_FOGC
;
475 /* fragment position treated as a texcoord */
476 if (InputsRead
& FRAG_BIT_WPOS
)
477 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_WPOS
, hwindex
++);
478 InputsRead
&= ~FRAG_BIT_WPOS
;
482 error("Don't know how to handle inputs 0x%x\n", InputsRead
);
486 static void decrement_dependencies(struct pair_state
*s
, int ip
)
488 struct pair_state_instruction
*pairinst
= s
->Instructions
+ ip
;
489 ASSERT(pairinst
->NumDependencies
> 0);
490 if (!--pairinst
->NumDependencies
)
491 instruction_ready(s
, ip
);
495 * Update the dependency tracking state based on what the instruction
496 * at the given IP does.
498 static void commit_instruction(struct pair_state
*s
, int ip
)
500 struct prog_instruction
*inst
= s
->Program
->Instructions
+ ip
;
501 struct pair_state_instruction
*pairinst
= s
->Instructions
+ ip
;
504 _mesa_printf("commit_instruction(%i)\n", ip
);
506 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
) {
507 struct pair_register_translation
*t
= &s
->Temps
[inst
->DstReg
.Index
];
508 deref_hw_reg(s
, t
->HwIndex
);
511 for(i
= 0; i
< 4; ++i
) {
512 if (!GET_BIT(inst
->DstReg
.WriteMask
, i
))
515 t
->Value
[i
] = pairinst
->Values
[i
];
516 if (t
->Value
[i
]->NumReaders
) {
517 struct reg_value_reader
*r
;
518 for(r
= pairinst
->Values
[i
]->Readers
; r
; r
= r
->Next
)
519 decrement_dependencies(s
, r
->IP
);
520 } else if (t
->Value
[i
]->Next
) {
521 /* This happens when the only reader writes
522 * the register at the same time */
523 decrement_dependencies(s
, t
->Value
[i
]->Next
->IP
);
528 int nsrc
= _mesa_num_inst_src_regs(inst
->Opcode
);
530 for(i
= 0; i
< nsrc
; i
++) {
531 struct pair_register_translation
*t
= get_register(s
, inst
->SrcReg
[i
].File
, inst
->SrcReg
[i
].Index
);
535 deref_hw_reg(s
, get_hw_reg(s
, inst
->SrcReg
[i
].File
, inst
->SrcReg
[i
].Index
));
537 if (inst
->SrcReg
[i
].File
!= PROGRAM_TEMPORARY
)
541 for(j
= 0; j
< 4; ++j
) {
542 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, j
);
548 /* Do not free a dependency if this instruction
549 * also rewrites the value. See scan_instructions. */
550 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
&&
551 inst
->DstReg
.Index
== inst
->SrcReg
[i
].Index
&&
552 GET_BIT(inst
->DstReg
.WriteMask
, swz
))
555 if (!--t
->Value
[swz
]->NumReaders
) {
556 if (t
->Value
[swz
]->Next
)
557 decrement_dependencies(s
, t
->Value
[swz
]->Next
->IP
);
565 * Emit all ready texture instructions in a single block.
567 * Emit as a single block to (hopefully) sample many textures in parallel,
568 * and to avoid hardware indirections on R300.
570 * In R500, we don't really know when the result of a texture instruction
571 * arrives. So allocate all destinations first, to make sure they do not
572 * arrive early and overwrite a texture coordinate we're going to use later
575 static void emit_all_tex(struct pair_state
*s
)
577 struct pair_state_instruction
*readytex
;
578 struct pair_state_instruction
*pairinst
;
582 // Don't let the ready list change under us!
583 readytex
= s
->ReadyTEX
;
586 // Allocate destination hardware registers in one block to avoid conflicts.
587 for(pairinst
= readytex
; pairinst
; pairinst
= pairinst
->NextReady
) {
588 int ip
= pairinst
- s
->Instructions
;
589 struct prog_instruction
*inst
= s
->Program
->Instructions
+ ip
;
590 if (inst
->Opcode
!= OPCODE_KIL
)
591 get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
595 _mesa_printf(" BEGIN_TEX\n");
597 if (s
->Handler
->BeginTexBlock
)
598 s
->Error
= s
->Error
|| !s
->Handler
->BeginTexBlock(s
->UserData
);
600 for(pairinst
= readytex
; pairinst
; pairinst
= pairinst
->NextReady
) {
601 int ip
= pairinst
- s
->Instructions
;
602 struct prog_instruction
*inst
= s
->Program
->Instructions
+ ip
;
603 commit_instruction(s
, ip
);
605 if (inst
->Opcode
!= OPCODE_KIL
)
606 inst
->DstReg
.Index
= get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
607 inst
->SrcReg
[0].Index
= get_hw_reg(s
, inst
->SrcReg
[0].File
, inst
->SrcReg
[0].Index
);
611 _mesa_print_instruction(inst
);
614 s
->Error
= s
->Error
|| !s
->Handler
->EmitTex(s
->UserData
, inst
);
618 _mesa_printf(" END_TEX\n");
622 static int alloc_pair_source(struct pair_state
*s
, struct radeon_pair_instruction
*pair
,
623 struct prog_src_register src
, GLboolean rgb
, GLboolean alpha
)
626 int candidate_quality
= -1;
635 if (src
.File
== PROGRAM_TEMPORARY
|| src
.File
== PROGRAM_INPUT
) {
637 index
= get_hw_reg(s
, src
.File
, src
.Index
);
640 s
->Error
|= !s
->Handler
->EmitConst(s
->UserData
, src
.File
, src
.Index
, &index
);
643 for(i
= 0; i
< 3; ++i
) {
646 if (pair
->RGB
.Src
[i
].Used
) {
647 if (pair
->RGB
.Src
[i
].Constant
!= constant
||
648 pair
->RGB
.Src
[i
].Index
!= index
)
654 if (pair
->Alpha
.Src
[i
].Used
) {
655 if (pair
->Alpha
.Src
[i
].Constant
!= constant
||
656 pair
->Alpha
.Src
[i
].Index
!= index
)
661 if (q
> candidate_quality
) {
662 candidate_quality
= q
;
667 if (candidate
>= 0) {
669 pair
->RGB
.Src
[candidate
].Used
= 1;
670 pair
->RGB
.Src
[candidate
].Constant
= constant
;
671 pair
->RGB
.Src
[candidate
].Index
= index
;
674 pair
->Alpha
.Src
[candidate
].Used
= 1;
675 pair
->Alpha
.Src
[candidate
].Constant
= constant
;
676 pair
->Alpha
.Src
[candidate
].Index
= index
;
684 * Fill the given ALU instruction's opcodes and source operands into the given pair,
687 static GLboolean
fill_instruction_into_pair(struct pair_state
*s
, struct radeon_pair_instruction
*pair
, int ip
)
689 struct pair_state_instruction
*pairinst
= s
->Instructions
+ ip
;
690 struct prog_instruction
*inst
= s
->Program
->Instructions
+ ip
;
692 ASSERT(!pairinst
->NeedRGB
|| pair
->RGB
.Opcode
== OPCODE_NOP
);
693 ASSERT(!pairinst
->NeedAlpha
|| pair
->Alpha
.Opcode
== OPCODE_NOP
);
695 if (pairinst
->NeedRGB
) {
696 if (pairinst
->IsTranscendent
)
697 pair
->RGB
.Opcode
= OPCODE_REPL_ALPHA
;
699 pair
->RGB
.Opcode
= inst
->Opcode
;
700 if (inst
->SaturateMode
== SATURATE_ZERO_ONE
)
701 pair
->RGB
.Saturate
= 1;
703 if (pairinst
->NeedAlpha
) {
704 pair
->Alpha
.Opcode
= inst
->Opcode
;
705 if (inst
->SaturateMode
== SATURATE_ZERO_ONE
)
706 pair
->Alpha
.Saturate
= 1;
709 int nargs
= _mesa_num_inst_src_regs(inst
->Opcode
);
712 /* Special case for DDX/DDY (MDH/MDV). */
713 if (inst
->Opcode
== OPCODE_DDX
|| inst
->Opcode
== OPCODE_DDY
) {
714 if (pair
->RGB
.Src
[0].Used
|| pair
->Alpha
.Src
[0].Used
)
720 for(i
= 0; i
< nargs
; ++i
) {
722 if (pairinst
->NeedRGB
&& !pairinst
->IsTranscendent
) {
723 GLboolean srcrgb
= GL_FALSE
;
724 GLboolean srcalpha
= GL_FALSE
;
726 for(j
= 0; j
< 3; ++j
) {
727 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, j
);
733 source
= alloc_pair_source(s
, pair
, inst
->SrcReg
[i
], srcrgb
, srcalpha
);
736 pair
->RGB
.Arg
[i
].Source
= source
;
737 pair
->RGB
.Arg
[i
].Swizzle
= inst
->SrcReg
[i
].Swizzle
& 0x1ff;
738 pair
->RGB
.Arg
[i
].Abs
= inst
->SrcReg
[i
].Abs
;
739 pair
->RGB
.Arg
[i
].Negate
= !!(inst
->SrcReg
[i
].Negate
& (NEGATE_X
| NEGATE_Y
| NEGATE_Z
));
741 if (pairinst
->NeedAlpha
) {
742 GLboolean srcrgb
= GL_FALSE
;
743 GLboolean srcalpha
= GL_FALSE
;
744 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, pairinst
->IsTranscendent
? 0 : 3);
749 source
= alloc_pair_source(s
, pair
, inst
->SrcReg
[i
], srcrgb
, srcalpha
);
752 pair
->Alpha
.Arg
[i
].Source
= source
;
753 pair
->Alpha
.Arg
[i
].Swizzle
= swz
;
754 pair
->Alpha
.Arg
[i
].Abs
= inst
->SrcReg
[i
].Abs
;
755 pair
->Alpha
.Arg
[i
].Negate
= !!(inst
->SrcReg
[i
].Negate
& NEGATE_W
);
764 * Fill in the destination register information.
766 * This is split from filling in source registers because we want
767 * to avoid allocating hardware temporaries for destinations until
768 * we are absolutely certain that we're going to emit a certain
769 * instruction pairing.
771 static void fill_dest_into_pair(struct pair_state
*s
, struct radeon_pair_instruction
*pair
, int ip
)
773 struct pair_state_instruction
*pairinst
= s
->Instructions
+ ip
;
774 struct prog_instruction
*inst
= s
->Program
->Instructions
+ ip
;
776 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
777 if (inst
->DstReg
.Index
== FRAG_RESULT_COLOR
) {
778 pair
->RGB
.OutputWriteMask
|= inst
->DstReg
.WriteMask
& WRITEMASK_XYZ
;
779 pair
->Alpha
.OutputWriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
780 } else if (inst
->DstReg
.Index
== FRAG_RESULT_DEPTH
) {
781 pair
->Alpha
.DepthWriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
784 GLuint hwindex
= get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
785 if (pairinst
->NeedRGB
) {
786 pair
->RGB
.DestIndex
= hwindex
;
787 pair
->RGB
.WriteMask
|= inst
->DstReg
.WriteMask
& WRITEMASK_XYZ
;
789 if (pairinst
->NeedAlpha
) {
790 pair
->Alpha
.DestIndex
= hwindex
;
791 pair
->Alpha
.WriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
798 * Find a good ALU instruction or pair of ALU instruction and emit it.
800 * Prefer emitting full ALU instructions, so that when we reach a point
801 * where no full ALU instruction can be emitted, we have more candidates
802 * for RGB/Alpha pairing.
804 static void emit_alu(struct pair_state
*s
)
806 struct radeon_pair_instruction pair
;
808 if (s
->ReadyFullALU
|| !(s
->ReadyRGB
&& s
->ReadyAlpha
)) {
810 if (s
->ReadyFullALU
) {
811 ip
= s
->ReadyFullALU
- s
->Instructions
;
812 s
->ReadyFullALU
= s
->ReadyFullALU
->NextReady
;
813 } else if (s
->ReadyRGB
) {
814 ip
= s
->ReadyRGB
- s
->Instructions
;
815 s
->ReadyRGB
= s
->ReadyRGB
->NextReady
;
817 ip
= s
->ReadyAlpha
- s
->Instructions
;
818 s
->ReadyAlpha
= s
->ReadyAlpha
->NextReady
;
821 _mesa_bzero(&pair
, sizeof(pair
));
822 fill_instruction_into_pair(s
, &pair
, ip
);
823 fill_dest_into_pair(s
, &pair
, ip
);
824 commit_instruction(s
, ip
);
826 struct pair_state_instruction
**prgb
;
827 struct pair_state_instruction
**palpha
;
829 /* Some pairings might fail because they require too
830 * many source slots; try all possible pairings if necessary */
831 for(prgb
= &s
->ReadyRGB
; *prgb
; prgb
= &(*prgb
)->NextReady
) {
832 for(palpha
= &s
->ReadyAlpha
; *palpha
; palpha
= &(*palpha
)->NextReady
) {
833 int rgbip
= *prgb
- s
->Instructions
;
834 int alphaip
= *palpha
- s
->Instructions
;
835 _mesa_bzero(&pair
, sizeof(pair
));
836 fill_instruction_into_pair(s
, &pair
, rgbip
);
837 if (!fill_instruction_into_pair(s
, &pair
, alphaip
))
839 *prgb
= (*prgb
)->NextReady
;
840 *palpha
= (*palpha
)->NextReady
;
841 fill_dest_into_pair(s
, &pair
, rgbip
);
842 fill_dest_into_pair(s
, &pair
, alphaip
);
843 commit_instruction(s
, rgbip
);
844 commit_instruction(s
, alphaip
);
849 /* No success in pairing; just take the first RGB instruction */
850 int ip
= s
->ReadyRGB
- s
->Instructions
;
851 s
->ReadyRGB
= s
->ReadyRGB
->NextReady
;
852 _mesa_bzero(&pair
, sizeof(pair
));
853 fill_instruction_into_pair(s
, &pair
, ip
);
854 fill_dest_into_pair(s
, &pair
, ip
);
855 commit_instruction(s
, ip
);
860 radeonPrintPairInstruction(&pair
);
862 s
->Error
= s
->Error
|| !s
->Handler
->EmitPaired(s
->UserData
, &pair
);
866 GLboolean
radeonPairProgram(GLcontext
*ctx
, struct gl_program
*program
,
867 const struct radeon_pair_handler
* handler
, void *userdata
)
871 _mesa_bzero(&s
, sizeof(s
));
875 s
.UserData
= userdata
;
876 s
.Debug
= (RADEON_DEBUG
& DEBUG_PIXEL
) ? GL_TRUE
: GL_FALSE
;
877 s
.Verbose
= GL_FALSE
&& s
.Debug
;
879 s
.Instructions
= (struct pair_state_instruction
*)_mesa_calloc(
880 sizeof(struct pair_state_instruction
)*s
.Program
->NumInstructions
);
881 s
.ValuePool
= (struct reg_value
*)_mesa_calloc(sizeof(struct reg_value
)*s
.Program
->NumInstructions
*4);
882 s
.ReaderPool
= (struct reg_value_reader
*)_mesa_calloc(
883 sizeof(struct reg_value_reader
)*s
.Program
->NumInstructions
*12);
886 _mesa_printf("Emit paired program\n");
888 scan_instructions(&s
);
889 allocate_input_registers(&s
);
892 (s
.ReadyTEX
|| s
.ReadyRGB
|| s
.ReadyAlpha
|| s
.ReadyFullALU
)) {
896 while(s
.ReadyFullALU
|| s
.ReadyRGB
|| s
.ReadyAlpha
)
901 _mesa_printf(" END\n");
903 _mesa_free(s
.Instructions
);
904 _mesa_free(s
.ValuePool
);
905 _mesa_free(s
.ReaderPool
);
911 static void print_pair_src(int i
, struct radeon_pair_instruction_source
* src
)
913 _mesa_printf(" Src%i = %s[%i]", i
, src
->Constant
? "CNST" : "TEMP", src
->Index
);
916 static const char* opcode_string(GLuint opcode
)
918 if (opcode
== OPCODE_REPL_ALPHA
)
921 return _mesa_opcode_string(opcode
);
924 static int num_pairinst_args(GLuint opcode
)
926 if (opcode
== OPCODE_REPL_ALPHA
)
929 return _mesa_num_inst_src_regs(opcode
);
932 static char swizzle_char(GLuint swz
)
935 case SWIZZLE_X
: return 'x';
936 case SWIZZLE_Y
: return 'y';
937 case SWIZZLE_Z
: return 'z';
938 case SWIZZLE_W
: return 'w';
939 case SWIZZLE_ZERO
: return '0';
940 case SWIZZLE_ONE
: return '1';
941 case SWIZZLE_NIL
: return '_';
946 void radeonPrintPairInstruction(struct radeon_pair_instruction
*inst
)
951 _mesa_printf(" RGB: ");
952 for(i
= 0; i
< 3; ++i
) {
953 if (inst
->RGB
.Src
[i
].Used
)
954 print_pair_src(i
, inst
->RGB
.Src
+ i
);
957 _mesa_printf(" Alpha:");
958 for(i
= 0; i
< 3; ++i
) {
959 if (inst
->Alpha
.Src
[i
].Used
)
960 print_pair_src(i
, inst
->Alpha
.Src
+ i
);
964 _mesa_printf(" %s%s", opcode_string(inst
->RGB
.Opcode
), inst
->RGB
.Saturate
? "_SAT" : "");
965 if (inst
->RGB
.WriteMask
)
966 _mesa_printf(" TEMP[%i].%s%s%s", inst
->RGB
.DestIndex
,
967 (inst
->RGB
.WriteMask
& 1) ? "x" : "",
968 (inst
->RGB
.WriteMask
& 2) ? "y" : "",
969 (inst
->RGB
.WriteMask
& 4) ? "z" : "");
970 if (inst
->RGB
.OutputWriteMask
)
971 _mesa_printf(" COLOR.%s%s%s",
972 (inst
->RGB
.OutputWriteMask
& 1) ? "x" : "",
973 (inst
->RGB
.OutputWriteMask
& 2) ? "y" : "",
974 (inst
->RGB
.OutputWriteMask
& 4) ? "z" : "");
975 nargs
= num_pairinst_args(inst
->RGB
.Opcode
);
976 for(i
= 0; i
< nargs
; ++i
) {
977 const char* abs
= inst
->RGB
.Arg
[i
].Abs
? "|" : "";
978 const char* neg
= inst
->RGB
.Arg
[i
].Negate
? "-" : "";
979 _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg
, abs
, inst
->RGB
.Arg
[i
].Source
,
980 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 0)),
981 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 1)),
982 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 2)),
987 _mesa_printf(" %s%s", opcode_string(inst
->Alpha
.Opcode
), inst
->Alpha
.Saturate
? "_SAT" : "");
988 if (inst
->Alpha
.WriteMask
)
989 _mesa_printf(" TEMP[%i].w", inst
->Alpha
.DestIndex
);
990 if (inst
->Alpha
.OutputWriteMask
)
991 _mesa_printf(" COLOR.w");
992 if (inst
->Alpha
.DepthWriteMask
)
993 _mesa_printf(" DEPTH.w");
994 nargs
= num_pairinst_args(inst
->Alpha
.Opcode
);
995 for(i
= 0; i
< nargs
; ++i
) {
996 const char* abs
= inst
->Alpha
.Arg
[i
].Abs
? "|" : "";
997 const char* neg
= inst
->Alpha
.Arg
[i
].Negate
? "-" : "";
998 _mesa_printf(", %s%sSrc%i.%c%s", neg
, abs
, inst
->Alpha
.Arg
[i
].Source
,
999 swizzle_char(inst
->Alpha
.Arg
[i
].Swizzle
), abs
);