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[mesa.git] / src / mesa / drivers / dri / r300 / radeon_program_pair.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * @file
30 *
31 * Perform temporary register allocation and attempt to pair off instructions
32 * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction
33 * vs. ALU instruction scheduling.
34 */
35
36 #include "radeon_program_pair.h"
37
38 #include "radeon_common.h"
39
40 #include "shader/prog_print.h"
41
42 #define error(fmt, args...) do { \
43 _mesa_problem(s->Ctx, "%s::%s(): " fmt "\n", \
44 __FILE__, __FUNCTION__, ##args); \
45 s->Error = GL_TRUE; \
46 } while(0)
47
48 struct pair_state_instruction {
49 GLuint IsTex:1; /**< Is a texture instruction */
50 GLuint NeedRGB:1; /**< Needs the RGB ALU */
51 GLuint NeedAlpha:1; /**< Needs the Alpha ALU */
52 GLuint IsTranscendent:1; /**< Is a special transcendent instruction */
53
54 /**
55 * Number of (read and write) dependencies that must be resolved before
56 * this instruction can be scheduled.
57 */
58 GLuint NumDependencies:5;
59
60 /**
61 * Next instruction in the linked list of ready instructions.
62 */
63 struct pair_state_instruction *NextReady;
64
65 /**
66 * Values that this instruction writes
67 */
68 struct reg_value *Values[4];
69 };
70
71
72 /**
73 * Used to keep track of which instructions read a value.
74 */
75 struct reg_value_reader {
76 GLuint IP; /**< IP of the instruction that performs this access */
77 struct reg_value_reader *Next;
78 };
79
80 /**
81 * Used to keep track which values are stored in each component of a
82 * PROGRAM_TEMPORARY.
83 */
84 struct reg_value {
85 GLuint IP; /**< IP of the instruction that writes this value */
86 struct reg_value *Next; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */
87
88 /**
89 * Unordered linked list of instructions that read from this value.
90 */
91 struct reg_value_reader *Readers;
92
93 /**
94 * Number of readers of this value. This is calculated during @ref scan_instructions
95 * and continually decremented during code emission.
96 * When this count reaches zero, the instruction that writes the @ref Next value
97 * can be scheduled.
98 */
99 GLuint NumReaders;
100 };
101
102 /**
103 * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register
104 * to the proper hardware temporary.
105 */
106 struct pair_register_translation {
107 GLuint Allocated:1;
108 GLuint HwIndex:8;
109 GLuint RefCount:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */
110
111 /**
112 * Notes the value that is currently contained in each component
113 * (only used for PROGRAM_TEMPORARY registers).
114 */
115 struct reg_value *Value[4];
116 };
117
118 struct pair_state {
119 GLcontext *Ctx;
120 struct gl_program *Program;
121 const struct radeon_pair_handler *Handler;
122 GLboolean Error;
123 GLboolean Debug;
124 GLboolean Verbose;
125 void *UserData;
126
127 /**
128 * Translate Mesa registers to hardware registers
129 */
130 struct pair_register_translation Inputs[FRAG_ATTRIB_MAX];
131 struct pair_register_translation Temps[MAX_PROGRAM_TEMPS];
132
133 /**
134 * Derived information about program instructions.
135 */
136 struct pair_state_instruction *Instructions;
137
138 struct {
139 GLuint RefCount; /**< # of times this occurs in an unscheduled SrcReg or DstReg */
140 } HwTemps[128];
141
142 /**
143 * Linked list of instructions that can be scheduled right now,
144 * based on which ALU/TEX resources they require.
145 */
146 struct pair_state_instruction *ReadyFullALU;
147 struct pair_state_instruction *ReadyRGB;
148 struct pair_state_instruction *ReadyAlpha;
149 struct pair_state_instruction *ReadyTEX;
150
151 /**
152 * Pool of @ref reg_value structures for fast allocation.
153 */
154 struct reg_value *ValuePool;
155 GLuint ValuePoolUsed;
156 struct reg_value_reader *ReaderPool;
157 GLuint ReaderPoolUsed;
158 };
159
160
161 static struct pair_register_translation *get_register(struct pair_state *s, GLuint file, GLuint index)
162 {
163 switch(file) {
164 case PROGRAM_TEMPORARY: return &s->Temps[index];
165 case PROGRAM_INPUT: return &s->Inputs[index];
166 default: return 0;
167 }
168 }
169
170 static void alloc_hw_reg(struct pair_state *s, GLuint file, GLuint index, GLuint hwindex)
171 {
172 struct pair_register_translation *t = get_register(s, file, index);
173 ASSERT(!s->HwTemps[hwindex].RefCount);
174 ASSERT(!t->Allocated);
175 s->HwTemps[hwindex].RefCount = t->RefCount;
176 t->Allocated = 1;
177 t->HwIndex = hwindex;
178 }
179
180 static GLuint get_hw_reg(struct pair_state *s, GLuint file, GLuint index)
181 {
182 GLuint hwindex;
183
184 struct pair_register_translation *t = get_register(s, file, index);
185 if (!t) {
186 _mesa_problem(s->Ctx, "get_hw_reg: %i[%i]\n", file, index);
187 return 0;
188 }
189
190 if (t->Allocated)
191 return t->HwIndex;
192
193 for(hwindex = 0; hwindex < s->Handler->MaxHwTemps; ++hwindex)
194 if (!s->HwTemps[hwindex].RefCount)
195 break;
196
197 if (hwindex >= s->Handler->MaxHwTemps) {
198 error("Ran out of hardware temporaries");
199 return 0;
200 }
201
202 alloc_hw_reg(s, file, index, hwindex);
203 return hwindex;
204 }
205
206
207 static void deref_hw_reg(struct pair_state *s, GLuint hwindex)
208 {
209 if (!s->HwTemps[hwindex].RefCount) {
210 error("Hwindex %i refcount error", hwindex);
211 return;
212 }
213
214 s->HwTemps[hwindex].RefCount--;
215 }
216
217 static void add_pairinst_to_list(struct pair_state_instruction **list, struct pair_state_instruction *pairinst)
218 {
219 pairinst->NextReady = *list;
220 *list = pairinst;
221 }
222
223 /**
224 * The instruction at the given IP has become ready. Link it into the ready
225 * instructions.
226 */
227 static void instruction_ready(struct pair_state *s, int ip)
228 {
229 struct pair_state_instruction *pairinst = s->Instructions + ip;
230
231 if (s->Verbose)
232 _mesa_printf("instruction_ready(%i)\n", ip);
233
234 if (pairinst->IsTex)
235 add_pairinst_to_list(&s->ReadyTEX, pairinst);
236 else if (!pairinst->NeedAlpha)
237 add_pairinst_to_list(&s->ReadyRGB, pairinst);
238 else if (!pairinst->NeedRGB)
239 add_pairinst_to_list(&s->ReadyAlpha, pairinst);
240 else
241 add_pairinst_to_list(&s->ReadyFullALU, pairinst);
242 }
243
244
245 /**
246 * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
247 * and reverse the order of arguments for CMP.
248 */
249 static void final_rewrite(struct pair_state *s, struct prog_instruction *inst)
250 {
251 struct prog_src_register tmp;
252
253 switch(inst->Opcode) {
254 case OPCODE_ADD:
255 inst->SrcReg[2] = inst->SrcReg[1];
256 inst->SrcReg[1].File = PROGRAM_BUILTIN;
257 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
258 inst->SrcReg[1].NegateBase = 0;
259 inst->SrcReg[1].NegateAbs = 0;
260 inst->Opcode = OPCODE_MAD;
261 break;
262 case OPCODE_CMP:
263 tmp = inst->SrcReg[2];
264 inst->SrcReg[2] = inst->SrcReg[0];
265 inst->SrcReg[0] = tmp;
266 break;
267 case OPCODE_MOV:
268 /* AMD say we should use CMP.
269 * However, when we transform
270 * KIL -r0;
271 * into
272 * CMP tmp, -r0, -r0, 0;
273 * KIL tmp;
274 * we get incorrect behaviour on R500 when r0 == 0.0.
275 * It appears that the R500 KIL hardware treats -0.0 as less
276 * than zero.
277 */
278 inst->SrcReg[1].File = PROGRAM_BUILTIN;
279 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
280 inst->SrcReg[2].File = PROGRAM_BUILTIN;
281 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
282 inst->Opcode = OPCODE_MAD;
283 break;
284 case OPCODE_MUL:
285 inst->SrcReg[2].File = PROGRAM_BUILTIN;
286 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
287 inst->Opcode = OPCODE_MAD;
288 break;
289 default:
290 /* nothing to do */
291 break;
292 }
293 }
294
295
296 /**
297 * Classify an instruction according to which ALUs etc. it needs
298 */
299 static void classify_instruction(struct pair_state *s,
300 struct prog_instruction *inst, struct pair_state_instruction *pairinst)
301 {
302 pairinst->NeedRGB = (inst->DstReg.WriteMask & WRITEMASK_XYZ) ? 1 : 0;
303 pairinst->NeedAlpha = (inst->DstReg.WriteMask & WRITEMASK_W) ? 1 : 0;
304
305 switch(inst->Opcode) {
306 case OPCODE_ADD:
307 case OPCODE_CMP:
308 case OPCODE_DDX:
309 case OPCODE_DDY:
310 case OPCODE_FRC:
311 case OPCODE_MAD:
312 case OPCODE_MAX:
313 case OPCODE_MIN:
314 case OPCODE_MOV:
315 case OPCODE_MUL:
316 break;
317 case OPCODE_COS:
318 case OPCODE_EX2:
319 case OPCODE_LG2:
320 case OPCODE_RCP:
321 case OPCODE_RSQ:
322 case OPCODE_SIN:
323 pairinst->IsTranscendent = 1;
324 pairinst->NeedAlpha = 1;
325 break;
326 case OPCODE_DP4:
327 pairinst->NeedAlpha = 1;
328 /* fall through */
329 case OPCODE_DP3:
330 pairinst->NeedRGB = 1;
331 break;
332 case OPCODE_KIL:
333 case OPCODE_TEX:
334 case OPCODE_TXB:
335 case OPCODE_TXP:
336 case OPCODE_END:
337 pairinst->IsTex = 1;
338 break;
339 default:
340 error("Unknown opcode %d\n", inst->Opcode);
341 break;
342 }
343 }
344
345
346 /**
347 * Count which (input, temporary) register is read and written how often,
348 * and scan the instruction stream to find dependencies.
349 */
350 static void scan_instructions(struct pair_state *s)
351 {
352 struct prog_instruction *inst;
353 struct pair_state_instruction *pairinst;
354 GLuint ip;
355
356 for(inst = s->Program->Instructions, pairinst = s->Instructions, ip = 0;
357 inst->Opcode != OPCODE_END;
358 ++inst, ++pairinst, ++ip) {
359 final_rewrite(s, inst);
360 classify_instruction(s, inst, pairinst);
361
362 int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
363 int j;
364 for(j = 0; j < nsrc; j++) {
365 struct pair_register_translation *t =
366 get_register(s, inst->SrcReg[j].File, inst->SrcReg[j].Index);
367 if (!t)
368 continue;
369
370 t->RefCount++;
371
372 if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) {
373 int i;
374 for(i = 0; i < 4; ++i) {
375 GLuint swz = GET_SWZ(inst->SrcReg[j].Swizzle, i);
376 if (swz >= 4)
377 continue; /* constant or NIL swizzle */
378 if (!t->Value[swz])
379 continue; /* this is an undefined read */
380
381 /* Do not add a dependency if this instruction
382 * also rewrites the value. The code below adds
383 * a dependency for the DstReg, which is a superset
384 * of the SrcReg dependency. */
385 if (inst->DstReg.File == PROGRAM_TEMPORARY &&
386 inst->DstReg.Index == inst->SrcReg[j].Index &&
387 GET_BIT(inst->DstReg.WriteMask, swz))
388 continue;
389
390 struct reg_value_reader* r = &s->ReaderPool[s->ReaderPoolUsed++];
391 pairinst->NumDependencies++;
392 t->Value[swz]->NumReaders++;
393 r->IP = ip;
394 r->Next = t->Value[swz]->Readers;
395 t->Value[swz]->Readers = r;
396 }
397 }
398 }
399
400 int ndst = _mesa_num_inst_dst_regs(inst->Opcode);
401 if (ndst) {
402 struct pair_register_translation *t =
403 get_register(s, inst->DstReg.File, inst->DstReg.Index);
404 if (t) {
405 t->RefCount++;
406
407 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
408 int j;
409 for(j = 0; j < 4; ++j) {
410 if (!GET_BIT(inst->DstReg.WriteMask, j))
411 continue;
412
413 struct reg_value* v = &s->ValuePool[s->ValuePoolUsed++];
414 v->IP = ip;
415 if (t->Value[j]) {
416 pairinst->NumDependencies++;
417 t->Value[j]->Next = v;
418 }
419 t->Value[j] = v;
420 pairinst->Values[j] = v;
421 }
422 }
423 }
424 }
425
426 if (s->Verbose)
427 _mesa_printf("scan(%i): NumDeps = %i\n", ip, pairinst->NumDependencies);
428
429 if (!pairinst->NumDependencies)
430 instruction_ready(s, ip);
431 }
432
433 /* Clear the PROGRAM_TEMPORARY state */
434 int i, j;
435 for(i = 0; i < MAX_PROGRAM_TEMPS; ++i) {
436 for(j = 0; j < 4; ++j)
437 s->Temps[i].Value[j] = 0;
438 }
439 }
440
441
442 /**
443 * Reserve hardware temporary registers for the program inputs.
444 *
445 * @note This allocation is performed explicitly, because the order of inputs
446 * is determined by the RS hardware.
447 */
448 static void allocate_input_registers(struct pair_state *s)
449 {
450 GLuint InputsRead = s->Program->InputsRead;
451 int i;
452 GLuint hwindex = 0;
453
454 /* Texcoords come first */
455 for (i = 0; i < s->Ctx->Const.MaxTextureUnits; i++) {
456 if (InputsRead & (FRAG_BIT_TEX0 << i))
457 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_TEX0+i, hwindex++);
458 }
459 InputsRead &= ~FRAG_BITS_TEX_ANY;
460
461 /* fragment position treated as a texcoord */
462 if (InputsRead & FRAG_BIT_WPOS)
463 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_WPOS, hwindex++);
464 InputsRead &= ~FRAG_BIT_WPOS;
465
466 /* Then primary colour */
467 if (InputsRead & FRAG_BIT_COL0)
468 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL0, hwindex++);
469 InputsRead &= ~FRAG_BIT_COL0;
470
471 /* Secondary color */
472 if (InputsRead & FRAG_BIT_COL1)
473 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL1, hwindex++);
474 InputsRead &= ~FRAG_BIT_COL1;
475
476 /* Anything else */
477 if (InputsRead)
478 error("Don't know how to handle inputs 0x%x\n", InputsRead);
479 }
480
481
482 static void decrement_dependencies(struct pair_state *s, int ip)
483 {
484 struct pair_state_instruction *pairinst = s->Instructions + ip;
485 ASSERT(pairinst->NumDependencies > 0);
486 if (!--pairinst->NumDependencies)
487 instruction_ready(s, ip);
488 }
489
490 /**
491 * Update the dependency tracking state based on what the instruction
492 * at the given IP does.
493 */
494 static void commit_instruction(struct pair_state *s, int ip)
495 {
496 struct prog_instruction *inst = s->Program->Instructions + ip;
497 struct pair_state_instruction *pairinst = s->Instructions + ip;
498
499 if (s->Verbose)
500 _mesa_printf("commit_instruction(%i)\n", ip);
501
502 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
503 struct pair_register_translation *t = &s->Temps[inst->DstReg.Index];
504 deref_hw_reg(s, t->HwIndex);
505
506 int i;
507 for(i = 0; i < 4; ++i) {
508 if (!GET_BIT(inst->DstReg.WriteMask, i))
509 continue;
510
511 t->Value[i] = pairinst->Values[i];
512 if (t->Value[i]->NumReaders) {
513 struct reg_value_reader *r;
514 for(r = pairinst->Values[i]->Readers; r; r = r->Next)
515 decrement_dependencies(s, r->IP);
516 } else if (t->Value[i]->Next) {
517 /* This happens when the only reader writes
518 * the register at the same time */
519 decrement_dependencies(s, t->Value[i]->Next->IP);
520 }
521 }
522 }
523
524 int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
525 int i;
526 for(i = 0; i < nsrc; i++) {
527 struct pair_register_translation *t = get_register(s, inst->SrcReg[i].File, inst->SrcReg[i].Index);
528 if (!t)
529 continue;
530
531 deref_hw_reg(s, get_hw_reg(s, inst->SrcReg[i].File, inst->SrcReg[i].Index));
532
533 if (inst->SrcReg[i].File != PROGRAM_TEMPORARY)
534 continue;
535
536 int j;
537 for(j = 0; j < 4; ++j) {
538 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
539 if (swz >= 4)
540 continue;
541 if (!t->Value[swz])
542 continue;
543
544 /* Do not free a dependency if this instruction
545 * also rewrites the value. See scan_instructions. */
546 if (inst->DstReg.File == PROGRAM_TEMPORARY &&
547 inst->DstReg.Index == inst->SrcReg[i].Index &&
548 GET_BIT(inst->DstReg.WriteMask, swz))
549 continue;
550
551 if (!--t->Value[swz]->NumReaders) {
552 if (t->Value[swz]->Next)
553 decrement_dependencies(s, t->Value[swz]->Next->IP);
554 }
555 }
556 }
557 }
558
559
560 /**
561 * Emit all ready texture instructions in a single block.
562 *
563 * Emit as a single block to (hopefully) sample many textures in parallel,
564 * and to avoid hardware indirections on R300.
565 *
566 * In R500, we don't really know when the result of a texture instruction
567 * arrives. So allocate all destinations first, to make sure they do not
568 * arrive early and overwrite a texture coordinate we're going to use later
569 * in the block.
570 */
571 static void emit_all_tex(struct pair_state *s)
572 {
573 struct pair_state_instruction *readytex;
574 struct pair_state_instruction *pairinst;
575
576 ASSERT(s->ReadyTEX);
577
578 // Don't let the ready list change under us!
579 readytex = s->ReadyTEX;
580 s->ReadyTEX = 0;
581
582 // Allocate destination hardware registers in one block to avoid conflicts.
583 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
584 int ip = pairinst - s->Instructions;
585 struct prog_instruction *inst = s->Program->Instructions + ip;
586 if (inst->Opcode != OPCODE_KIL)
587 get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
588 }
589
590 if (s->Debug)
591 _mesa_printf(" BEGIN_TEX\n");
592
593 if (s->Handler->BeginTexBlock)
594 s->Error = s->Error || !s->Handler->BeginTexBlock(s->UserData);
595
596 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
597 int ip = pairinst - s->Instructions;
598 struct prog_instruction *inst = s->Program->Instructions + ip;
599 commit_instruction(s, ip);
600
601 if (inst->Opcode != OPCODE_KIL)
602 inst->DstReg.Index = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
603 inst->SrcReg[0].Index = get_hw_reg(s, inst->SrcReg[0].File, inst->SrcReg[0].Index);
604
605 if (s->Debug) {
606 _mesa_printf(" ");
607 _mesa_print_instruction(inst);
608 }
609 s->Error = s->Error || !s->Handler->EmitTex(s->UserData, inst);
610 }
611
612 if (s->Debug)
613 _mesa_printf(" END_TEX\n");
614 }
615
616
617 static int alloc_pair_source(struct pair_state *s, struct radeon_pair_instruction *pair,
618 struct prog_src_register src, GLboolean rgb, GLboolean alpha)
619 {
620 int candidate = -1;
621 int candidate_quality = -1;
622 int i;
623
624 if (!rgb && !alpha)
625 return 0;
626
627 GLuint constant;
628 GLuint index;
629
630 if (src.File == PROGRAM_TEMPORARY || src.File == PROGRAM_INPUT) {
631 constant = 0;
632 index = get_hw_reg(s, src.File, src.Index);
633 } else {
634 constant = 1;
635 s->Error |= !s->Handler->EmitConst(s->UserData, src.File, src.Index, &index);
636 }
637
638 for(i = 0; i < 3; ++i) {
639 int q = 0;
640 if (rgb) {
641 if (pair->RGB.Src[i].Used) {
642 if (pair->RGB.Src[i].Constant != constant ||
643 pair->RGB.Src[i].Index != index)
644 continue;
645 q++;
646 }
647 }
648 if (alpha) {
649 if (pair->Alpha.Src[i].Used) {
650 if (pair->Alpha.Src[i].Constant != constant ||
651 pair->Alpha.Src[i].Index != index)
652 continue;
653 q++;
654 }
655 }
656 if (q > candidate_quality) {
657 candidate_quality = q;
658 candidate = i;
659 }
660 }
661
662 if (candidate >= 0) {
663 if (rgb) {
664 pair->RGB.Src[candidate].Used = 1;
665 pair->RGB.Src[candidate].Constant = constant;
666 pair->RGB.Src[candidate].Index = index;
667 }
668 if (alpha) {
669 pair->Alpha.Src[candidate].Used = 1;
670 pair->Alpha.Src[candidate].Constant = constant;
671 pair->Alpha.Src[candidate].Index = index;
672 }
673 }
674
675 return candidate;
676 }
677
678 /**
679 * Fill the given ALU instruction's opcodes and source operands into the given pair,
680 * if possible.
681 */
682 static GLboolean fill_instruction_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip)
683 {
684 struct pair_state_instruction *pairinst = s->Instructions + ip;
685 struct prog_instruction *inst = s->Program->Instructions + ip;
686
687 ASSERT(!pairinst->NeedRGB || pair->RGB.Opcode == OPCODE_NOP);
688 ASSERT(!pairinst->NeedAlpha || pair->Alpha.Opcode == OPCODE_NOP);
689
690 if (pairinst->NeedRGB) {
691 if (pairinst->IsTranscendent)
692 pair->RGB.Opcode = OPCODE_REPL_ALPHA;
693 else
694 pair->RGB.Opcode = inst->Opcode;
695 if (inst->SaturateMode == SATURATE_ZERO_ONE)
696 pair->RGB.Saturate = 1;
697 }
698 if (pairinst->NeedAlpha) {
699 pair->Alpha.Opcode = inst->Opcode;
700 if (inst->SaturateMode == SATURATE_ZERO_ONE)
701 pair->Alpha.Saturate = 1;
702 }
703
704 int nargs = _mesa_num_inst_src_regs(inst->Opcode);
705 int i;
706
707 /* Special case for DDX/DDY (MDH/MDV). */
708 if (inst->Opcode == OPCODE_DDX || inst->Opcode == OPCODE_DDY) {
709 if (pair->RGB.Src[0].Used || pair->Alpha.Src[0].Used)
710 return GL_FALSE;
711 else
712 nargs++;
713 }
714
715 for(i = 0; i < nargs; ++i) {
716 int source;
717 if (pairinst->NeedRGB && !pairinst->IsTranscendent) {
718 GLboolean srcrgb = GL_FALSE;
719 GLboolean srcalpha = GL_FALSE;
720 GLuint negatebase = 0;
721 int j;
722 for(j = 0; j < 3; ++j) {
723 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
724 if (swz < 3)
725 srcrgb = GL_TRUE;
726 else if (swz < 4)
727 srcalpha = GL_TRUE;
728 if (swz != SWIZZLE_NIL && GET_BIT(inst->SrcReg[i].NegateBase, j))
729 negatebase = 1;
730 }
731 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
732 if (source < 0)
733 return GL_FALSE;
734 pair->RGB.Arg[i].Source = source;
735 pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff;
736 pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs;
737 pair->RGB.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs;
738 }
739 if (pairinst->NeedAlpha) {
740 GLboolean srcrgb = GL_FALSE;
741 GLboolean srcalpha = GL_FALSE;
742 GLuint negatebase = GET_BIT(inst->SrcReg[i].NegateBase, pairinst->IsTranscendent ? 0 : 3);
743 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, pairinst->IsTranscendent ? 0 : 3);
744 if (swz < 3)
745 srcrgb = GL_TRUE;
746 else if (swz < 4)
747 srcalpha = GL_TRUE;
748 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
749 if (source < 0)
750 return GL_FALSE;
751 pair->Alpha.Arg[i].Source = source;
752 pair->Alpha.Arg[i].Swizzle = swz;
753 pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs;
754 pair->Alpha.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs;
755 }
756 }
757
758 return GL_TRUE;
759 }
760
761
762 /**
763 * Fill in the destination register information.
764 *
765 * This is split from filling in source registers because we want
766 * to avoid allocating hardware temporaries for destinations until
767 * we are absolutely certain that we're going to emit a certain
768 * instruction pairing.
769 */
770 static void fill_dest_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip)
771 {
772 struct pair_state_instruction *pairinst = s->Instructions + ip;
773 struct prog_instruction *inst = s->Program->Instructions + ip;
774
775 if (inst->DstReg.File == PROGRAM_OUTPUT) {
776 if (inst->DstReg.Index == FRAG_RESULT_COLR) {
777 pair->RGB.OutputWriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
778 pair->Alpha.OutputWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
779 } else if (inst->DstReg.Index == FRAG_RESULT_DEPR) {
780 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
781 }
782 } else {
783 GLuint hwindex = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
784 if (pairinst->NeedRGB) {
785 pair->RGB.DestIndex = hwindex;
786 pair->RGB.WriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
787 }
788 if (pairinst->NeedAlpha) {
789 pair->Alpha.DestIndex = hwindex;
790 pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
791 }
792 }
793 }
794
795
796 /**
797 * Find a good ALU instruction or pair of ALU instruction and emit it.
798 *
799 * Prefer emitting full ALU instructions, so that when we reach a point
800 * where no full ALU instruction can be emitted, we have more candidates
801 * for RGB/Alpha pairing.
802 */
803 static void emit_alu(struct pair_state *s)
804 {
805 struct radeon_pair_instruction pair;
806
807 if (s->ReadyFullALU || !(s->ReadyRGB && s->ReadyAlpha)) {
808 int ip;
809 if (s->ReadyFullALU) {
810 ip = s->ReadyFullALU - s->Instructions;
811 s->ReadyFullALU = s->ReadyFullALU->NextReady;
812 } else if (s->ReadyRGB) {
813 ip = s->ReadyRGB - s->Instructions;
814 s->ReadyRGB = s->ReadyRGB->NextReady;
815 } else {
816 ip = s->ReadyAlpha - s->Instructions;
817 s->ReadyAlpha = s->ReadyAlpha->NextReady;
818 }
819
820 _mesa_bzero(&pair, sizeof(pair));
821 fill_instruction_into_pair(s, &pair, ip);
822 fill_dest_into_pair(s, &pair, ip);
823 commit_instruction(s, ip);
824 } else {
825 struct pair_state_instruction **prgb;
826 struct pair_state_instruction **palpha;
827
828 /* Some pairings might fail because they require too
829 * many source slots; try all possible pairings if necessary */
830 for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) {
831 for(palpha = &s->ReadyAlpha; *palpha; palpha = &(*palpha)->NextReady) {
832 int rgbip = *prgb - s->Instructions;
833 int alphaip = *palpha - s->Instructions;
834 _mesa_bzero(&pair, sizeof(pair));
835 fill_instruction_into_pair(s, &pair, rgbip);
836 if (!fill_instruction_into_pair(s, &pair, alphaip))
837 continue;
838 *prgb = (*prgb)->NextReady;
839 *palpha = (*palpha)->NextReady;
840 fill_dest_into_pair(s, &pair, rgbip);
841 fill_dest_into_pair(s, &pair, alphaip);
842 commit_instruction(s, rgbip);
843 commit_instruction(s, alphaip);
844 goto success;
845 }
846 }
847
848 /* No success in pairing; just take the first RGB instruction */
849 int ip = s->ReadyRGB - s->Instructions;
850 s->ReadyRGB = s->ReadyRGB->NextReady;
851 _mesa_bzero(&pair, sizeof(pair));
852 fill_instruction_into_pair(s, &pair, ip);
853 fill_dest_into_pair(s, &pair, ip);
854 commit_instruction(s, ip);
855 success: ;
856 }
857
858 if (s->Debug)
859 radeonPrintPairInstruction(&pair);
860
861 s->Error = s->Error || !s->Handler->EmitPaired(s->UserData, &pair);
862 }
863
864
865 GLboolean radeonPairProgram(GLcontext *ctx, struct gl_program *program,
866 const struct radeon_pair_handler* handler, void *userdata)
867 {
868 struct pair_state s;
869
870 _mesa_bzero(&s, sizeof(s));
871 s.Ctx = ctx;
872 s.Program = program;
873 s.Handler = handler;
874 s.UserData = userdata;
875 s.Debug = (RADEON_DEBUG & DEBUG_PIXEL) ? GL_TRUE : GL_FALSE;
876 s.Verbose = GL_FALSE && s.Debug;
877
878 s.Instructions = (struct pair_state_instruction*)_mesa_calloc(
879 sizeof(struct pair_state_instruction)*s.Program->NumInstructions);
880 s.ValuePool = (struct reg_value*)_mesa_calloc(sizeof(struct reg_value)*s.Program->NumInstructions*4);
881 s.ReaderPool = (struct reg_value_reader*)_mesa_calloc(
882 sizeof(struct reg_value_reader)*s.Program->NumInstructions*12);
883
884 if (s.Debug)
885 _mesa_printf("Emit paired program\n");
886
887 scan_instructions(&s);
888 allocate_input_registers(&s);
889
890 while(!s.Error &&
891 (s.ReadyTEX || s.ReadyRGB || s.ReadyAlpha || s.ReadyFullALU)) {
892 if (s.ReadyTEX)
893 emit_all_tex(&s);
894
895 while(s.ReadyFullALU || s.ReadyRGB || s.ReadyAlpha)
896 emit_alu(&s);
897 }
898
899 if (s.Debug)
900 _mesa_printf(" END\n");
901
902 _mesa_free(s.Instructions);
903 _mesa_free(s.ValuePool);
904 _mesa_free(s.ReaderPool);
905
906 return !s.Error;
907 }
908
909
910 static void print_pair_src(int i, struct radeon_pair_instruction_source* src)
911 {
912 _mesa_printf(" Src%i = %s[%i]", i, src->Constant ? "CNST" : "TEMP", src->Index);
913 }
914
915 static const char* opcode_string(GLuint opcode)
916 {
917 if (opcode == OPCODE_REPL_ALPHA)
918 return "SOP";
919 else
920 return _mesa_opcode_string(opcode);
921 }
922
923 static int num_pairinst_args(GLuint opcode)
924 {
925 if (opcode == OPCODE_REPL_ALPHA)
926 return 0;
927 else
928 return _mesa_num_inst_src_regs(opcode);
929 }
930
931 static char swizzle_char(GLuint swz)
932 {
933 switch(swz) {
934 case SWIZZLE_X: return 'x';
935 case SWIZZLE_Y: return 'y';
936 case SWIZZLE_Z: return 'z';
937 case SWIZZLE_W: return 'w';
938 case SWIZZLE_ZERO: return '0';
939 case SWIZZLE_ONE: return '1';
940 case SWIZZLE_NIL: return '_';
941 default: return '?';
942 }
943 }
944
945 void radeonPrintPairInstruction(struct radeon_pair_instruction *inst)
946 {
947 int nargs;
948 int i;
949
950 _mesa_printf(" RGB: ");
951 for(i = 0; i < 3; ++i) {
952 if (inst->RGB.Src[i].Used)
953 print_pair_src(i, inst->RGB.Src + i);
954 }
955 _mesa_printf("\n");
956 _mesa_printf(" Alpha:");
957 for(i = 0; i < 3; ++i) {
958 if (inst->Alpha.Src[i].Used)
959 print_pair_src(i, inst->Alpha.Src + i);
960 }
961 _mesa_printf("\n");
962
963 _mesa_printf(" %s%s", opcode_string(inst->RGB.Opcode), inst->RGB.Saturate ? "_SAT" : "");
964 if (inst->RGB.WriteMask)
965 _mesa_printf(" TEMP[%i].%s%s%s", inst->RGB.DestIndex,
966 (inst->RGB.WriteMask & 1) ? "x" : "",
967 (inst->RGB.WriteMask & 2) ? "y" : "",
968 (inst->RGB.WriteMask & 4) ? "z" : "");
969 if (inst->RGB.OutputWriteMask)
970 _mesa_printf(" COLOR.%s%s%s",
971 (inst->RGB.OutputWriteMask & 1) ? "x" : "",
972 (inst->RGB.OutputWriteMask & 2) ? "y" : "",
973 (inst->RGB.OutputWriteMask & 4) ? "z" : "");
974 nargs = num_pairinst_args(inst->RGB.Opcode);
975 for(i = 0; i < nargs; ++i) {
976 const char* abs = inst->RGB.Arg[i].Abs ? "|" : "";
977 const char* neg = inst->RGB.Arg[i].Negate ? "-" : "";
978 _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg, abs, inst->RGB.Arg[i].Source,
979 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 0)),
980 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 1)),
981 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 2)),
982 abs);
983 }
984 _mesa_printf("\n");
985
986 _mesa_printf(" %s%s", opcode_string(inst->Alpha.Opcode), inst->Alpha.Saturate ? "_SAT" : "");
987 if (inst->Alpha.WriteMask)
988 _mesa_printf(" TEMP[%i].w", inst->Alpha.DestIndex);
989 if (inst->Alpha.OutputWriteMask)
990 _mesa_printf(" COLOR.w");
991 if (inst->Alpha.DepthWriteMask)
992 _mesa_printf(" DEPTH.w");
993 nargs = num_pairinst_args(inst->Alpha.Opcode);
994 for(i = 0; i < nargs; ++i) {
995 const char* abs = inst->Alpha.Arg[i].Abs ? "|" : "";
996 const char* neg = inst->Alpha.Arg[i].Negate ? "-" : "";
997 _mesa_printf(", %s%sSrc%i.%c%s", neg, abs, inst->Alpha.Arg[i].Source,
998 swizzle_char(inst->Alpha.Arg[i].Swizzle), abs);
999 }
1000 _mesa_printf("\n");
1001 }