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slang: initialize the context
[mesa.git] / src / mesa / drivers / dri / r300 / radeon_program_pair.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * @file
30 *
31 * Perform temporary register allocation and attempt to pair off instructions
32 * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction
33 * vs. ALU instruction scheduling.
34 */
35
36 #include "radeon_program_pair.h"
37
38 #include "radeon_context.h"
39
40 #include "shader/prog_print.h"
41
42 #define error(fmt, args...) do { \
43 _mesa_problem(s->Ctx, "%s::%s(): " fmt "\n", \
44 __FILE__, __FUNCTION__, ##args); \
45 s->Error = GL_TRUE; \
46 } while(0)
47
48 struct pair_state_instruction {
49 GLuint IsTex:1; /**< Is a texture instruction */
50 GLuint NeedRGB:1; /**< Needs the RGB ALU */
51 GLuint NeedAlpha:1; /**< Needs the Alpha ALU */
52 GLuint IsTranscendent:1; /**< Is a special transcendent instruction */
53
54 /**
55 * Number of (read and write) dependencies that must be resolved before
56 * this instruction can be scheduled.
57 */
58 GLuint NumDependencies:5;
59
60 /**
61 * Next instruction in the linked list of ready instructions.
62 */
63 struct pair_state_instruction *NextReady;
64
65 /**
66 * Values that this instruction writes
67 */
68 struct reg_value *Values[4];
69 };
70
71
72 /**
73 * Used to keep track of which instructions read a value.
74 */
75 struct reg_value_reader {
76 GLuint IP; /**< IP of the instruction that performs this access */
77 struct reg_value_reader *Next;
78 };
79
80 /**
81 * Used to keep track which values are stored in each component of a
82 * PROGRAM_TEMPORARY.
83 */
84 struct reg_value {
85 GLuint IP; /**< IP of the instruction that writes this value */
86 struct reg_value *Next; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */
87
88 /**
89 * Unordered linked list of instructions that read from this value.
90 */
91 struct reg_value_reader *Readers;
92
93 /**
94 * Number of readers of this value. This is calculated during @ref scan_instructions
95 * and continually decremented during code emission.
96 * When this count reaches zero, the instruction that writes the @ref Next value
97 * can be scheduled.
98 */
99 GLuint NumReaders;
100 };
101
102 /**
103 * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register
104 * to the proper hardware temporary.
105 */
106 struct pair_register_translation {
107 GLuint Allocated:1;
108 GLuint HwIndex:8;
109 GLuint RefCount:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */
110
111 /**
112 * Notes the value that is currently contained in each component
113 * (only used for PROGRAM_TEMPORARY registers).
114 */
115 struct reg_value *Value[4];
116 };
117
118 struct pair_state {
119 GLcontext *Ctx;
120 struct gl_program *Program;
121 const struct radeon_pair_handler *Handler;
122 GLboolean Error;
123 GLboolean Debug;
124 GLboolean Verbose;
125 void *UserData;
126
127 /**
128 * Translate Mesa registers to hardware registers
129 */
130 struct pair_register_translation Inputs[FRAG_ATTRIB_MAX];
131 struct pair_register_translation Temps[MAX_PROGRAM_TEMPS];
132
133 /**
134 * Derived information about program instructions.
135 */
136 struct pair_state_instruction *Instructions;
137
138 struct {
139 GLuint RefCount; /**< # of times this occurs in an unscheduled SrcReg or DstReg */
140 } HwTemps[128];
141
142 /**
143 * Linked list of instructions that can be scheduled right now,
144 * based on which ALU/TEX resources they require.
145 */
146 struct pair_state_instruction *ReadyFullALU;
147 struct pair_state_instruction *ReadyRGB;
148 struct pair_state_instruction *ReadyAlpha;
149 struct pair_state_instruction *ReadyTEX;
150
151 /**
152 * Pool of @ref reg_value structures for fast allocation.
153 */
154 struct reg_value *ValuePool;
155 GLuint ValuePoolUsed;
156 struct reg_value_reader *ReaderPool;
157 GLuint ReaderPoolUsed;
158 };
159
160
161 static struct pair_register_translation *get_register(struct pair_state *s, GLuint file, GLuint index)
162 {
163 switch(file) {
164 case PROGRAM_TEMPORARY: return &s->Temps[index];
165 case PROGRAM_INPUT: return &s->Inputs[index];
166 default: return 0;
167 }
168 }
169
170 static void alloc_hw_reg(struct pair_state *s, GLuint file, GLuint index, GLuint hwindex)
171 {
172 struct pair_register_translation *t = get_register(s, file, index);
173 ASSERT(!s->HwTemps[hwindex].RefCount);
174 ASSERT(!t->Allocated);
175 s->HwTemps[hwindex].RefCount = t->RefCount;
176 t->Allocated = 1;
177 t->HwIndex = hwindex;
178 }
179
180 static GLuint get_hw_reg(struct pair_state *s, GLuint file, GLuint index)
181 {
182 GLuint hwindex;
183
184 struct pair_register_translation *t = get_register(s, file, index);
185 if (!t) {
186 _mesa_problem(s->Ctx, "get_hw_reg: %i[%i]\n", file, index);
187 return 0;
188 }
189
190 if (t->Allocated)
191 return t->HwIndex;
192
193 for(hwindex = 0; hwindex < s->Handler->MaxHwTemps; ++hwindex)
194 if (!s->HwTemps[hwindex].RefCount)
195 break;
196
197 if (hwindex >= s->Handler->MaxHwTemps) {
198 error("Ran out of hardware temporaries");
199 return 0;
200 }
201
202 alloc_hw_reg(s, file, index, hwindex);
203 return hwindex;
204 }
205
206
207 static void deref_hw_reg(struct pair_state *s, GLuint hwindex)
208 {
209 if (!s->HwTemps[hwindex].RefCount) {
210 error("Hwindex %i refcount error", hwindex);
211 return;
212 }
213
214 s->HwTemps[hwindex].RefCount--;
215 }
216
217 static void add_pairinst_to_list(struct pair_state_instruction **list, struct pair_state_instruction *pairinst)
218 {
219 pairinst->NextReady = *list;
220 *list = pairinst;
221 }
222
223 /**
224 * The instruction at the given IP has become ready. Link it into the ready
225 * instructions.
226 */
227 static void instruction_ready(struct pair_state *s, int ip)
228 {
229 struct pair_state_instruction *pairinst = s->Instructions + ip;
230
231 if (s->Verbose)
232 _mesa_printf("instruction_ready(%i)\n", ip);
233
234 if (pairinst->IsTex)
235 add_pairinst_to_list(&s->ReadyTEX, pairinst);
236 else if (!pairinst->NeedAlpha)
237 add_pairinst_to_list(&s->ReadyRGB, pairinst);
238 else if (!pairinst->NeedRGB)
239 add_pairinst_to_list(&s->ReadyAlpha, pairinst);
240 else
241 add_pairinst_to_list(&s->ReadyFullALU, pairinst);
242 }
243
244
245 /**
246 * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
247 * and reverse the order of arguments for CMP.
248 */
249 static void final_rewrite(struct pair_state *s, struct prog_instruction *inst)
250 {
251 struct prog_src_register tmp;
252
253 switch(inst->Opcode) {
254 case OPCODE_ADD:
255 inst->SrcReg[2] = inst->SrcReg[1];
256 inst->SrcReg[1].File = PROGRAM_BUILTIN;
257 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
258 inst->SrcReg[1].NegateBase = 0;
259 inst->SrcReg[1].NegateAbs = 0;
260 inst->Opcode = OPCODE_MAD;
261 break;
262 case OPCODE_CMP:
263 tmp = inst->SrcReg[2];
264 inst->SrcReg[2] = inst->SrcReg[0];
265 inst->SrcReg[0] = tmp;
266 break;
267 case OPCODE_MOV:
268 /* AMD say we should use CMP.
269 * However, when we transform
270 * KIL -r0;
271 * into
272 * CMP tmp, -r0, -r0, 0;
273 * KIL tmp;
274 * we get incorrect behaviour on R500 when r0 == 0.0.
275 * It appears that the R500 KIL hardware treats -0.0 as less
276 * than zero.
277 */
278 inst->SrcReg[1].File = PROGRAM_BUILTIN;
279 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
280 inst->SrcReg[2].File = PROGRAM_BUILTIN;
281 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
282 inst->Opcode = OPCODE_MAD;
283 break;
284 case OPCODE_MUL:
285 inst->SrcReg[2].File = PROGRAM_BUILTIN;
286 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
287 inst->Opcode = OPCODE_MAD;
288 break;
289 default:
290 /* nothing to do */
291 break;
292 }
293 }
294
295
296 /**
297 * Classify an instruction according to which ALUs etc. it needs
298 */
299 static void classify_instruction(struct pair_state *s,
300 struct prog_instruction *inst, struct pair_state_instruction *pairinst)
301 {
302 pairinst->NeedRGB = (inst->DstReg.WriteMask & WRITEMASK_XYZ) ? 1 : 0;
303 pairinst->NeedAlpha = (inst->DstReg.WriteMask & WRITEMASK_W) ? 1 : 0;
304
305 switch(inst->Opcode) {
306 case OPCODE_ADD:
307 case OPCODE_CMP:
308 case OPCODE_DDX:
309 case OPCODE_DDY:
310 case OPCODE_FRC:
311 case OPCODE_MAD:
312 case OPCODE_MAX:
313 case OPCODE_MIN:
314 case OPCODE_MOV:
315 case OPCODE_MUL:
316 break;
317 case OPCODE_COS:
318 case OPCODE_EX2:
319 case OPCODE_LG2:
320 case OPCODE_RCP:
321 case OPCODE_RSQ:
322 case OPCODE_SIN:
323 pairinst->IsTranscendent = 1;
324 pairinst->NeedAlpha = 1;
325 break;
326 case OPCODE_DP4:
327 pairinst->NeedAlpha = 1;
328 /* fall through */
329 case OPCODE_DP3:
330 pairinst->NeedRGB = 1;
331 break;
332 case OPCODE_KIL:
333 case OPCODE_TEX:
334 case OPCODE_TXB:
335 case OPCODE_TXP:
336 case OPCODE_END:
337 pairinst->IsTex = 1;
338 break;
339 default:
340 error("Unknown opcode %d\n", inst->Opcode);
341 break;
342 }
343 }
344
345
346 /**
347 * Count which (input, temporary) register is read and written how often,
348 * and scan the instruction stream to find dependencies.
349 */
350 static void scan_instructions(struct pair_state *s)
351 {
352 struct prog_instruction *inst;
353 struct pair_state_instruction *pairinst;
354 GLuint ip;
355
356 for(inst = s->Program->Instructions, pairinst = s->Instructions, ip = 0;
357 inst->Opcode != OPCODE_END;
358 ++inst, ++pairinst, ++ip) {
359 final_rewrite(s, inst);
360 classify_instruction(s, inst, pairinst);
361
362 int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
363 int j;
364 for(j = 0; j < nsrc; j++) {
365 struct pair_register_translation *t =
366 get_register(s, inst->SrcReg[j].File, inst->SrcReg[j].Index);
367 if (!t)
368 continue;
369
370 t->RefCount++;
371
372 if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) {
373 int i;
374 for(i = 0; i < 4; ++i) {
375 GLuint swz = GET_SWZ(inst->SrcReg[j].Swizzle, i);
376 if (swz >= 4)
377 continue; /* constant or NIL swizzle */
378 if (!t->Value[swz])
379 continue; /* this is an undefined read */
380
381 /* Do not add a dependency if this instruction
382 * also rewrites the value. The code below adds
383 * a dependency for the DstReg, which is a superset
384 * of the SrcReg dependency. */
385 if (inst->DstReg.File == PROGRAM_TEMPORARY &&
386 inst->DstReg.Index == inst->SrcReg[j].Index &&
387 GET_BIT(inst->DstReg.WriteMask, swz))
388 continue;
389
390 struct reg_value_reader* r = &s->ReaderPool[s->ReaderPoolUsed++];
391 pairinst->NumDependencies++;
392 t->Value[swz]->NumReaders++;
393 r->IP = ip;
394 r->Next = t->Value[swz]->Readers;
395 t->Value[swz]->Readers = r;
396 }
397 }
398 }
399
400 int ndst = _mesa_num_inst_dst_regs(inst->Opcode);
401 if (ndst) {
402 struct pair_register_translation *t =
403 get_register(s, inst->DstReg.File, inst->DstReg.Index);
404 if (t) {
405 t->RefCount++;
406
407 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
408 int j;
409 for(j = 0; j < 4; ++j) {
410 if (!GET_BIT(inst->DstReg.WriteMask, j))
411 continue;
412
413 struct reg_value* v = &s->ValuePool[s->ValuePoolUsed++];
414 v->IP = ip;
415 if (t->Value[j]) {
416 pairinst->NumDependencies++;
417 t->Value[j]->Next = v;
418 }
419 t->Value[j] = v;
420 pairinst->Values[j] = v;
421 }
422 }
423 }
424 }
425
426 if (s->Verbose)
427 _mesa_printf("scan(%i): NumDeps = %i\n", ip, pairinst->NumDependencies);
428
429 if (!pairinst->NumDependencies)
430 instruction_ready(s, ip);
431 }
432
433 /* Clear the PROGRAM_TEMPORARY state */
434 int i, j;
435 for(i = 0; i < MAX_PROGRAM_TEMPS; ++i) {
436 for(j = 0; j < 4; ++j)
437 s->Temps[i].Value[j] = 0;
438 }
439 }
440
441
442 /**
443 * Reserve hardware temporary registers for the program inputs.
444 *
445 * @note This allocation is performed explicitly, because the order of inputs
446 * is determined by the RS hardware.
447 */
448 static void allocate_input_registers(struct pair_state *s)
449 {
450 GLuint InputsRead = s->Program->InputsRead;
451 int i;
452 GLuint hwindex = 0;
453
454 /* Primary colour */
455 if (InputsRead & FRAG_BIT_COL0)
456 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL0, hwindex++);
457 InputsRead &= ~FRAG_BIT_COL0;
458
459 /* Secondary color */
460 if (InputsRead & FRAG_BIT_COL1)
461 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL1, hwindex++);
462 InputsRead &= ~FRAG_BIT_COL1;
463
464 /* Texcoords */
465 for (i = 0; i < s->Ctx->Const.MaxTextureUnits; i++) {
466 if (InputsRead & (FRAG_BIT_TEX0 << i))
467 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_TEX0+i, hwindex++);
468 }
469 InputsRead &= ~FRAG_BITS_TEX_ANY;
470
471 /* Fogcoords treated as a texcoord */
472 if (InputsRead & FRAG_BIT_FOGC)
473 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_FOGC, hwindex++);
474 InputsRead &= ~FRAG_BIT_FOGC;
475
476 /* fragment position treated as a texcoord */
477 if (InputsRead & FRAG_BIT_WPOS)
478 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_WPOS, hwindex++);
479 InputsRead &= ~FRAG_BIT_WPOS;
480
481 /* Anything else */
482 if (InputsRead)
483 error("Don't know how to handle inputs 0x%x\n", InputsRead);
484 }
485
486
487 static void decrement_dependencies(struct pair_state *s, int ip)
488 {
489 struct pair_state_instruction *pairinst = s->Instructions + ip;
490 ASSERT(pairinst->NumDependencies > 0);
491 if (!--pairinst->NumDependencies)
492 instruction_ready(s, ip);
493 }
494
495 /**
496 * Update the dependency tracking state based on what the instruction
497 * at the given IP does.
498 */
499 static void commit_instruction(struct pair_state *s, int ip)
500 {
501 struct prog_instruction *inst = s->Program->Instructions + ip;
502 struct pair_state_instruction *pairinst = s->Instructions + ip;
503
504 if (s->Verbose)
505 _mesa_printf("commit_instruction(%i)\n", ip);
506
507 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
508 struct pair_register_translation *t = &s->Temps[inst->DstReg.Index];
509 deref_hw_reg(s, t->HwIndex);
510
511 int i;
512 for(i = 0; i < 4; ++i) {
513 if (!GET_BIT(inst->DstReg.WriteMask, i))
514 continue;
515
516 t->Value[i] = pairinst->Values[i];
517 if (t->Value[i]->NumReaders) {
518 struct reg_value_reader *r;
519 for(r = pairinst->Values[i]->Readers; r; r = r->Next)
520 decrement_dependencies(s, r->IP);
521 } else if (t->Value[i]->Next) {
522 /* This happens when the only reader writes
523 * the register at the same time */
524 decrement_dependencies(s, t->Value[i]->Next->IP);
525 }
526 }
527 }
528
529 int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
530 int i;
531 for(i = 0; i < nsrc; i++) {
532 struct pair_register_translation *t = get_register(s, inst->SrcReg[i].File, inst->SrcReg[i].Index);
533 if (!t)
534 continue;
535
536 deref_hw_reg(s, get_hw_reg(s, inst->SrcReg[i].File, inst->SrcReg[i].Index));
537
538 if (inst->SrcReg[i].File != PROGRAM_TEMPORARY)
539 continue;
540
541 int j;
542 for(j = 0; j < 4; ++j) {
543 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
544 if (swz >= 4)
545 continue;
546 if (!t->Value[swz])
547 continue;
548
549 /* Do not free a dependency if this instruction
550 * also rewrites the value. See scan_instructions. */
551 if (inst->DstReg.File == PROGRAM_TEMPORARY &&
552 inst->DstReg.Index == inst->SrcReg[i].Index &&
553 GET_BIT(inst->DstReg.WriteMask, swz))
554 continue;
555
556 if (!--t->Value[swz]->NumReaders) {
557 if (t->Value[swz]->Next)
558 decrement_dependencies(s, t->Value[swz]->Next->IP);
559 }
560 }
561 }
562 }
563
564
565 /**
566 * Emit all ready texture instructions in a single block.
567 *
568 * Emit as a single block to (hopefully) sample many textures in parallel,
569 * and to avoid hardware indirections on R300.
570 *
571 * In R500, we don't really know when the result of a texture instruction
572 * arrives. So allocate all destinations first, to make sure they do not
573 * arrive early and overwrite a texture coordinate we're going to use later
574 * in the block.
575 */
576 static void emit_all_tex(struct pair_state *s)
577 {
578 struct pair_state_instruction *readytex;
579 struct pair_state_instruction *pairinst;
580
581 ASSERT(s->ReadyTEX);
582
583 // Don't let the ready list change under us!
584 readytex = s->ReadyTEX;
585 s->ReadyTEX = 0;
586
587 // Allocate destination hardware registers in one block to avoid conflicts.
588 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
589 int ip = pairinst - s->Instructions;
590 struct prog_instruction *inst = s->Program->Instructions + ip;
591 if (inst->Opcode != OPCODE_KIL)
592 get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
593 }
594
595 if (s->Debug)
596 _mesa_printf(" BEGIN_TEX\n");
597
598 if (s->Handler->BeginTexBlock)
599 s->Error = s->Error || !s->Handler->BeginTexBlock(s->UserData);
600
601 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
602 int ip = pairinst - s->Instructions;
603 struct prog_instruction *inst = s->Program->Instructions + ip;
604 commit_instruction(s, ip);
605
606 if (inst->Opcode != OPCODE_KIL)
607 inst->DstReg.Index = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
608 inst->SrcReg[0].Index = get_hw_reg(s, inst->SrcReg[0].File, inst->SrcReg[0].Index);
609
610 if (s->Debug) {
611 _mesa_printf(" ");
612 _mesa_print_instruction(inst);
613 }
614 s->Error = s->Error || !s->Handler->EmitTex(s->UserData, inst);
615 }
616
617 if (s->Debug)
618 _mesa_printf(" END_TEX\n");
619 }
620
621
622 static int alloc_pair_source(struct pair_state *s, struct radeon_pair_instruction *pair,
623 struct prog_src_register src, GLboolean rgb, GLboolean alpha)
624 {
625 int candidate = -1;
626 int candidate_quality = -1;
627 int i;
628
629 if (!rgb && !alpha)
630 return 0;
631
632 GLuint constant;
633 GLuint index;
634
635 if (src.File == PROGRAM_TEMPORARY || src.File == PROGRAM_INPUT) {
636 constant = 0;
637 index = get_hw_reg(s, src.File, src.Index);
638 } else {
639 constant = 1;
640 s->Error |= !s->Handler->EmitConst(s->UserData, src.File, src.Index, &index);
641 }
642
643 for(i = 0; i < 3; ++i) {
644 int q = 0;
645 if (rgb) {
646 if (pair->RGB.Src[i].Used) {
647 if (pair->RGB.Src[i].Constant != constant ||
648 pair->RGB.Src[i].Index != index)
649 continue;
650 q++;
651 }
652 }
653 if (alpha) {
654 if (pair->Alpha.Src[i].Used) {
655 if (pair->Alpha.Src[i].Constant != constant ||
656 pair->Alpha.Src[i].Index != index)
657 continue;
658 q++;
659 }
660 }
661 if (q > candidate_quality) {
662 candidate_quality = q;
663 candidate = i;
664 }
665 }
666
667 if (candidate >= 0) {
668 if (rgb) {
669 pair->RGB.Src[candidate].Used = 1;
670 pair->RGB.Src[candidate].Constant = constant;
671 pair->RGB.Src[candidate].Index = index;
672 }
673 if (alpha) {
674 pair->Alpha.Src[candidate].Used = 1;
675 pair->Alpha.Src[candidate].Constant = constant;
676 pair->Alpha.Src[candidate].Index = index;
677 }
678 }
679
680 return candidate;
681 }
682
683 /**
684 * Fill the given ALU instruction's opcodes and source operands into the given pair,
685 * if possible.
686 */
687 static GLboolean fill_instruction_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip)
688 {
689 struct pair_state_instruction *pairinst = s->Instructions + ip;
690 struct prog_instruction *inst = s->Program->Instructions + ip;
691
692 ASSERT(!pairinst->NeedRGB || pair->RGB.Opcode == OPCODE_NOP);
693 ASSERT(!pairinst->NeedAlpha || pair->Alpha.Opcode == OPCODE_NOP);
694
695 if (pairinst->NeedRGB) {
696 if (pairinst->IsTranscendent)
697 pair->RGB.Opcode = OPCODE_REPL_ALPHA;
698 else
699 pair->RGB.Opcode = inst->Opcode;
700 if (inst->SaturateMode == SATURATE_ZERO_ONE)
701 pair->RGB.Saturate = 1;
702 }
703 if (pairinst->NeedAlpha) {
704 pair->Alpha.Opcode = inst->Opcode;
705 if (inst->SaturateMode == SATURATE_ZERO_ONE)
706 pair->Alpha.Saturate = 1;
707 }
708
709 int nargs = _mesa_num_inst_src_regs(inst->Opcode);
710 int i;
711
712 /* Special case for DDX/DDY (MDH/MDV). */
713 if (inst->Opcode == OPCODE_DDX || inst->Opcode == OPCODE_DDY) {
714 if (pair->RGB.Src[0].Used || pair->Alpha.Src[0].Used)
715 return GL_FALSE;
716 else
717 nargs++;
718 }
719
720 for(i = 0; i < nargs; ++i) {
721 int source;
722 if (pairinst->NeedRGB && !pairinst->IsTranscendent) {
723 GLboolean srcrgb = GL_FALSE;
724 GLboolean srcalpha = GL_FALSE;
725 GLuint negatebase = 0;
726 int j;
727 for(j = 0; j < 3; ++j) {
728 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
729 if (swz < 3)
730 srcrgb = GL_TRUE;
731 else if (swz < 4)
732 srcalpha = GL_TRUE;
733 if (swz != SWIZZLE_NIL && GET_BIT(inst->SrcReg[i].NegateBase, j))
734 negatebase = 1;
735 }
736 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
737 if (source < 0)
738 return GL_FALSE;
739 pair->RGB.Arg[i].Source = source;
740 pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff;
741 pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs;
742 pair->RGB.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs;
743 }
744 if (pairinst->NeedAlpha) {
745 GLboolean srcrgb = GL_FALSE;
746 GLboolean srcalpha = GL_FALSE;
747 GLuint negatebase = GET_BIT(inst->SrcReg[i].NegateBase, pairinst->IsTranscendent ? 0 : 3);
748 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, pairinst->IsTranscendent ? 0 : 3);
749 if (swz < 3)
750 srcrgb = GL_TRUE;
751 else if (swz < 4)
752 srcalpha = GL_TRUE;
753 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
754 if (source < 0)
755 return GL_FALSE;
756 pair->Alpha.Arg[i].Source = source;
757 pair->Alpha.Arg[i].Swizzle = swz;
758 pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs;
759 pair->Alpha.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs;
760 }
761 }
762
763 return GL_TRUE;
764 }
765
766
767 /**
768 * Fill in the destination register information.
769 *
770 * This is split from filling in source registers because we want
771 * to avoid allocating hardware temporaries for destinations until
772 * we are absolutely certain that we're going to emit a certain
773 * instruction pairing.
774 */
775 static void fill_dest_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip)
776 {
777 struct pair_state_instruction *pairinst = s->Instructions + ip;
778 struct prog_instruction *inst = s->Program->Instructions + ip;
779
780 if (inst->DstReg.File == PROGRAM_OUTPUT) {
781 if (inst->DstReg.Index == FRAG_RESULT_COLOR) {
782 pair->RGB.OutputWriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
783 pair->Alpha.OutputWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
784 } else if (inst->DstReg.Index == FRAG_RESULT_DEPTH) {
785 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
786 }
787 } else {
788 GLuint hwindex = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
789 if (pairinst->NeedRGB) {
790 pair->RGB.DestIndex = hwindex;
791 pair->RGB.WriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
792 }
793 if (pairinst->NeedAlpha) {
794 pair->Alpha.DestIndex = hwindex;
795 pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
796 }
797 }
798 }
799
800
801 /**
802 * Find a good ALU instruction or pair of ALU instruction and emit it.
803 *
804 * Prefer emitting full ALU instructions, so that when we reach a point
805 * where no full ALU instruction can be emitted, we have more candidates
806 * for RGB/Alpha pairing.
807 */
808 static void emit_alu(struct pair_state *s)
809 {
810 struct radeon_pair_instruction pair;
811
812 if (s->ReadyFullALU || !(s->ReadyRGB && s->ReadyAlpha)) {
813 int ip;
814 if (s->ReadyFullALU) {
815 ip = s->ReadyFullALU - s->Instructions;
816 s->ReadyFullALU = s->ReadyFullALU->NextReady;
817 } else if (s->ReadyRGB) {
818 ip = s->ReadyRGB - s->Instructions;
819 s->ReadyRGB = s->ReadyRGB->NextReady;
820 } else {
821 ip = s->ReadyAlpha - s->Instructions;
822 s->ReadyAlpha = s->ReadyAlpha->NextReady;
823 }
824
825 _mesa_bzero(&pair, sizeof(pair));
826 fill_instruction_into_pair(s, &pair, ip);
827 fill_dest_into_pair(s, &pair, ip);
828 commit_instruction(s, ip);
829 } else {
830 struct pair_state_instruction **prgb;
831 struct pair_state_instruction **palpha;
832
833 /* Some pairings might fail because they require too
834 * many source slots; try all possible pairings if necessary */
835 for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) {
836 for(palpha = &s->ReadyAlpha; *palpha; palpha = &(*palpha)->NextReady) {
837 int rgbip = *prgb - s->Instructions;
838 int alphaip = *palpha - s->Instructions;
839 _mesa_bzero(&pair, sizeof(pair));
840 fill_instruction_into_pair(s, &pair, rgbip);
841 if (!fill_instruction_into_pair(s, &pair, alphaip))
842 continue;
843 *prgb = (*prgb)->NextReady;
844 *palpha = (*palpha)->NextReady;
845 fill_dest_into_pair(s, &pair, rgbip);
846 fill_dest_into_pair(s, &pair, alphaip);
847 commit_instruction(s, rgbip);
848 commit_instruction(s, alphaip);
849 goto success;
850 }
851 }
852
853 /* No success in pairing; just take the first RGB instruction */
854 int ip = s->ReadyRGB - s->Instructions;
855 s->ReadyRGB = s->ReadyRGB->NextReady;
856 _mesa_bzero(&pair, sizeof(pair));
857 fill_instruction_into_pair(s, &pair, ip);
858 fill_dest_into_pair(s, &pair, ip);
859 commit_instruction(s, ip);
860 success: ;
861 }
862
863 if (s->Debug)
864 radeonPrintPairInstruction(&pair);
865
866 s->Error = s->Error || !s->Handler->EmitPaired(s->UserData, &pair);
867 }
868
869
870 GLboolean radeonPairProgram(GLcontext *ctx, struct gl_program *program,
871 const struct radeon_pair_handler* handler, void *userdata)
872 {
873 struct pair_state s;
874
875 _mesa_bzero(&s, sizeof(s));
876 s.Ctx = ctx;
877 s.Program = program;
878 s.Handler = handler;
879 s.UserData = userdata;
880 s.Debug = (RADEON_DEBUG & DEBUG_PIXEL) ? GL_TRUE : GL_FALSE;
881 s.Verbose = GL_FALSE && s.Debug;
882
883 s.Instructions = (struct pair_state_instruction*)_mesa_calloc(
884 sizeof(struct pair_state_instruction)*s.Program->NumInstructions);
885 s.ValuePool = (struct reg_value*)_mesa_calloc(sizeof(struct reg_value)*s.Program->NumInstructions*4);
886 s.ReaderPool = (struct reg_value_reader*)_mesa_calloc(
887 sizeof(struct reg_value_reader)*s.Program->NumInstructions*12);
888
889 if (s.Debug)
890 _mesa_printf("Emit paired program\n");
891
892 scan_instructions(&s);
893 allocate_input_registers(&s);
894
895 while(!s.Error &&
896 (s.ReadyTEX || s.ReadyRGB || s.ReadyAlpha || s.ReadyFullALU)) {
897 if (s.ReadyTEX)
898 emit_all_tex(&s);
899
900 while(s.ReadyFullALU || s.ReadyRGB || s.ReadyAlpha)
901 emit_alu(&s);
902 }
903
904 if (s.Debug)
905 _mesa_printf(" END\n");
906
907 _mesa_free(s.Instructions);
908 _mesa_free(s.ValuePool);
909 _mesa_free(s.ReaderPool);
910
911 return !s.Error;
912 }
913
914
915 static void print_pair_src(int i, struct radeon_pair_instruction_source* src)
916 {
917 _mesa_printf(" Src%i = %s[%i]", i, src->Constant ? "CNST" : "TEMP", src->Index);
918 }
919
920 static const char* opcode_string(GLuint opcode)
921 {
922 if (opcode == OPCODE_REPL_ALPHA)
923 return "SOP";
924 else
925 return _mesa_opcode_string(opcode);
926 }
927
928 static int num_pairinst_args(GLuint opcode)
929 {
930 if (opcode == OPCODE_REPL_ALPHA)
931 return 0;
932 else
933 return _mesa_num_inst_src_regs(opcode);
934 }
935
936 static char swizzle_char(GLuint swz)
937 {
938 switch(swz) {
939 case SWIZZLE_X: return 'x';
940 case SWIZZLE_Y: return 'y';
941 case SWIZZLE_Z: return 'z';
942 case SWIZZLE_W: return 'w';
943 case SWIZZLE_ZERO: return '0';
944 case SWIZZLE_ONE: return '1';
945 case SWIZZLE_NIL: return '_';
946 default: return '?';
947 }
948 }
949
950 void radeonPrintPairInstruction(struct radeon_pair_instruction *inst)
951 {
952 int nargs;
953 int i;
954
955 _mesa_printf(" RGB: ");
956 for(i = 0; i < 3; ++i) {
957 if (inst->RGB.Src[i].Used)
958 print_pair_src(i, inst->RGB.Src + i);
959 }
960 _mesa_printf("\n");
961 _mesa_printf(" Alpha:");
962 for(i = 0; i < 3; ++i) {
963 if (inst->Alpha.Src[i].Used)
964 print_pair_src(i, inst->Alpha.Src + i);
965 }
966 _mesa_printf("\n");
967
968 _mesa_printf(" %s%s", opcode_string(inst->RGB.Opcode), inst->RGB.Saturate ? "_SAT" : "");
969 if (inst->RGB.WriteMask)
970 _mesa_printf(" TEMP[%i].%s%s%s", inst->RGB.DestIndex,
971 (inst->RGB.WriteMask & 1) ? "x" : "",
972 (inst->RGB.WriteMask & 2) ? "y" : "",
973 (inst->RGB.WriteMask & 4) ? "z" : "");
974 if (inst->RGB.OutputWriteMask)
975 _mesa_printf(" COLOR.%s%s%s",
976 (inst->RGB.OutputWriteMask & 1) ? "x" : "",
977 (inst->RGB.OutputWriteMask & 2) ? "y" : "",
978 (inst->RGB.OutputWriteMask & 4) ? "z" : "");
979 nargs = num_pairinst_args(inst->RGB.Opcode);
980 for(i = 0; i < nargs; ++i) {
981 const char* abs = inst->RGB.Arg[i].Abs ? "|" : "";
982 const char* neg = inst->RGB.Arg[i].Negate ? "-" : "";
983 _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg, abs, inst->RGB.Arg[i].Source,
984 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 0)),
985 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 1)),
986 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 2)),
987 abs);
988 }
989 _mesa_printf("\n");
990
991 _mesa_printf(" %s%s", opcode_string(inst->Alpha.Opcode), inst->Alpha.Saturate ? "_SAT" : "");
992 if (inst->Alpha.WriteMask)
993 _mesa_printf(" TEMP[%i].w", inst->Alpha.DestIndex);
994 if (inst->Alpha.OutputWriteMask)
995 _mesa_printf(" COLOR.w");
996 if (inst->Alpha.DepthWriteMask)
997 _mesa_printf(" DEPTH.w");
998 nargs = num_pairinst_args(inst->Alpha.Opcode);
999 for(i = 0; i < nargs; ++i) {
1000 const char* abs = inst->Alpha.Arg[i].Abs ? "|" : "";
1001 const char* neg = inst->Alpha.Arg[i].Negate ? "-" : "";
1002 _mesa_printf(", %s%sSrc%i.%c%s", neg, abs, inst->Alpha.Arg[i].Source,
1003 swizzle_char(inst->Alpha.Arg[i].Swizzle), abs);
1004 }
1005 _mesa_printf("\n");
1006 }