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[mesa.git] / src / mesa / drivers / dri / r300 / radeon_span.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include "glheader.h"
36 #include "imports.h"
37 #include "swrast/swrast.h"
38 #include "colormac.h"
39
40 #include "r200_context.h"
41 #include "radeon_ioctl.h"
42 #include "r300_ioctl.h"
43 #include "radeon_span.h"
44
45 #define DBG 0
46
47 #define LOCAL_VARS \
48 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
49 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
50 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
51 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
52 GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
53 GLuint height = dPriv->h; \
54 char *buf = (char *)(sPriv->pFB + \
55 radeon->state.color.drawOffset + \
56 (dPriv->x * radeonScreen->cpp) + \
57 (dPriv->y * pitch)); \
58 char *read_buf = (char *)(sPriv->pFB + \
59 radeon->state.pixel.readOffset + \
60 (dPriv->x * radeonScreen->cpp) + \
61 (dPriv->y * pitch)); \
62 GLuint p; \
63 (void) read_buf; (void) buf; (void) p
64
65 #define LOCAL_DEPTH_VARS \
66 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
67 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
68 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
69 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
70 GLuint height = dPriv->h; \
71 GLuint xo = dPriv->x; \
72 GLuint yo = dPriv->y; \
73 char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \
74 GLuint pitch = radeonScreen->depthPitch; \
75 (void) buf; (void) pitch
76
77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
78
79 #define CLIPPIXEL( _x, _y ) \
80 ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
81
82 #define CLIPSPAN( _x, _y, _n, _x1, _n1, _i ) \
83 if ( _y < miny || _y >= maxy ) { \
84 _n1 = 0, _x1 = x; \
85 } else { \
86 _n1 = _n; \
87 _x1 = _x; \
88 if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
89 if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx); \
90 }
91
92 #define Y_FLIP( _y ) (height - _y - 1)
93
94 #define HW_LOCK()
95
96 #define HW_CLIPLOOP() \
97 do { \
98 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
99 int _nc = dPriv->numClipRects; \
100 \
101 while ( _nc-- ) { \
102 int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \
103 int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \
104 int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \
105 int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
106
107 #define HW_ENDCLIPLOOP() \
108 } \
109 } while (0)
110
111 #define HW_UNLOCK()
112
113 /* ================================================================
114 * Color buffer
115 */
116
117 /* 16 bit, RGB565 color spanline and pixel functions
118 */
119 #define INIT_MONO_PIXEL(p, color) \
120 p = PACK_COLOR_565( color[0], color[1], color[2] )
121
122 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
123 *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) | \
124 (((int)g & 0xfc) << 3) | \
125 (((int)b & 0xf8) >> 3))
126
127 #define WRITE_PIXEL( _x, _y, p ) \
128 *(GLushort *)(buf + _x*2 + _y*pitch) = p
129
130 #define READ_RGBA( rgba, _x, _y ) \
131 do { \
132 GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch); \
133 rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
134 rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
135 rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \
136 rgba[3] = 0xff; \
137 } while (0)
138
139 #define TAG(x) radeon##x##_RGB565
140 #include "spantmp.h"
141
142 /* 32 bit, ARGB8888 color spanline and pixel functions
143 */
144 #undef INIT_MONO_PIXEL
145 #define INIT_MONO_PIXEL(p, color) \
146 p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
147
148 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
149 do { \
150 *(GLuint *)(buf + _x*4 + _y*pitch) = ((b << 0) | \
151 (g << 8) | \
152 (r << 16) | \
153 (a << 24) ); \
154 } while (0)
155
156 #define WRITE_PIXEL( _x, _y, p ) \
157 do { \
158 *(GLuint *)(buf + _x*4 + _y*pitch) = p; \
159 } while (0)
160
161 #define READ_RGBA( rgba, _x, _y ) \
162 do { \
163 volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
164 GLuint p = *ptr; \
165 rgba[0] = (p >> 16) & 0xff; \
166 rgba[1] = (p >> 8) & 0xff; \
167 rgba[2] = (p >> 0) & 0xff; \
168 rgba[3] = (p >> 24) & 0xff; \
169 } while (0)
170
171 #define TAG(x) radeon##x##_ARGB8888
172 #include "spantmp.h"
173
174 /* ================================================================
175 * Depth buffer
176 */
177
178 /* The Radeon family has depth tiling on all the time, so we have to convert
179 * the x,y coordinates into the memory bus address (mba) in the same
180 * manner as the engine. In each case, the linear block address (ba)
181 * is calculated, and then wired with x and y to produce the final
182 * memory address.
183 */
184
185 #define BIT(x,b) ((x & (1<<b))>>b)
186 static GLuint radeon_mba_z32(radeonContextPtr radeon, GLint x, GLint y)
187 {
188 GLuint pitch = radeon->radeonScreen->depthPitch;
189 GLuint b =
190 ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x3FF) >> 5);
191 GLuint a =
192 (BIT(x, 0) << 2) | (BIT(y, 0) << 3) | (BIT(x, 1) << 4) | (BIT(y, 1)
193 << 5) |
194 (BIT(x, 3) << 6) | (BIT(x, 4) << 7) | (BIT(x, 2) << 8) | (BIT(y, 2)
195 << 9) |
196 (BIT(y, 3) << 10) |
197 (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
198 ((b >> 1) << 12);
199 return a;
200 }
201
202 static GLuint radeon_mba_z16(radeonContextPtr radeon, GLint x, GLint y)
203 {
204 GLuint pitch = radeon->radeonScreen->depthPitch;
205 GLuint b =
206 ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x3FF) >> 6);
207 GLuint a =
208 (BIT(x, 0) << 1) | (BIT(y, 0) << 2) | (BIT(x, 1) << 3) | (BIT(y, 1)
209 << 4) |
210 (BIT(x, 2) << 5) | (BIT(x, 4) << 6) | (BIT(x, 5) << 7) | (BIT(x, 3)
211 << 8) |
212 (BIT(y, 2) << 9) | (BIT(y, 3) << 10) |
213 (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
214 ((b >> 1) << 12);
215 return a;
216 }
217
218
219 /* 16-bit depth buffer functions
220 */
221 #define WRITE_DEPTH( _x, _y, d ) \
222 *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo )) = d;
223
224 #define READ_DEPTH( d, _x, _y ) \
225 d = *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo ));
226
227 #define TAG(x) radeon##x##_16_TILE
228 #include "depthtmp.h"
229
230 /* 24 bit depth, 8 bit stencil depthbuffer functions
231 */
232 #define WRITE_DEPTH( _x, _y, d ) \
233 do { \
234 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
235 GLuint tmp = *(GLuint *)(buf + offset); \
236 tmp &= 0xff000000; \
237 tmp |= ((d) & 0x00ffffff); \
238 *(GLuint *)(buf + offset) = tmp; \
239 } while (0)
240
241 #define READ_DEPTH( d, _x, _y ) \
242 d = *(GLuint *)(buf + radeon_mba_z32( radeon, _x + xo, \
243 _y + yo )) & 0x00ffffff;
244
245 #define TAG(x) radeon##x##_24_8_TILE
246 #include "depthtmp.h"
247
248 /* 16-bit depth buffer functions
249 */
250 #define WRITE_DEPTH( _x, _y, d ) \
251 *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 ) = d;
252
253 #define READ_DEPTH( d, _x, _y ) \
254 d = *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 );
255
256 #define TAG(x) radeon##x##_16_LINEAR
257 #include "depthtmp.h"
258
259 /* 24 bit depth, 8 bit stencil depthbuffer functions
260 *
261 * Careful: It looks like the R300 uses ZZZS byte order while the R200
262 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
263 */
264 #define WRITE_DEPTH( _x, _y, d ) \
265 do { \
266 GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \
267 GLuint tmp = *(GLuint *)(buf + offset); \
268 tmp &= 0x000000ff; \
269 tmp |= ((d << 8) & 0xffffff00); \
270 *(GLuint *)(buf + offset) = tmp; \
271 } while (0)
272
273 #define READ_DEPTH( d, _x, _y ) \
274 d = (*(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0xffffff00) >> 8;
275
276 #define TAG(x) radeon##x##_24_8_LINEAR
277 #include "depthtmp.h"
278
279 /* ================================================================
280 * Stencil buffer
281 */
282
283 /* 24 bit depth, 8 bit stencil depthbuffer functions
284 */
285 #define WRITE_STENCIL( _x, _y, d ) \
286 do { \
287 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
288 GLuint tmp = *(GLuint *)(buf + offset); \
289 tmp &= 0xffffff00; \
290 tmp |= (d) & 0xff; \
291 *(GLuint *)(buf + offset) = tmp; \
292 } while (0)
293
294 #define READ_STENCIL( d, _x, _y ) \
295 do { \
296 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
297 GLuint tmp = *(GLuint *)(buf + offset); \
298 d = tmp & 0x000000ff; \
299 } while (0)
300
301 #define TAG(x) radeon##x##_24_8_TILE
302 #include "stenciltmp.h"
303
304 /* 24 bit depth, 8 bit stencil depthbuffer functions
305 */
306 #define WRITE_STENCIL( _x, _y, d ) \
307 do { \
308 GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \
309 GLuint tmp = *(GLuint *)(buf + offset); \
310 tmp &= 0xffffff00; \
311 tmp |= (d) & 0xff; \
312 *(GLuint *)(buf + offset) = tmp; \
313 } while (0)
314
315 #define READ_STENCIL( d, _x, _y ) \
316 do { \
317 GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \
318 GLuint tmp = *(GLuint *)(buf + offset); \
319 d = tmp & 0x000000ff; \
320 } while (0)
321
322 #define TAG(x) radeon##x##_24_8_LINEAR
323 #include "stenciltmp.h"
324
325 /*
326 * This function is called to specify which buffer to read and write
327 * for software rasterization (swrast) fallbacks. This doesn't necessarily
328 * correspond to glDrawBuffer() or glReadBuffer() calls.
329 */
330 static void radeonSetBuffer(GLcontext * ctx,
331 GLframebuffer * colorBuffer, GLuint bufferBit)
332 {
333 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
334 int buffer;
335
336 switch (bufferBit) {
337 case BUFFER_BIT_FRONT_LEFT:
338 buffer = 0;
339 break;
340
341 case BUFFER_BIT_BACK_LEFT:
342 buffer = 1;
343 break;
344
345 default:
346 _mesa_problem(ctx, "Bad bufferBit in %s", __FUNCTION__);
347 return;
348 }
349
350 if (radeon->doPageFlip && radeon->sarea->pfCurrentPage == 1)
351 buffer ^= 1;
352
353 #if 0
354 fprintf(stderr, "%s: using %s buffer\n", __FUNCTION__,
355 buffer ? "back" : "front");
356 #endif
357
358 if (buffer) {
359 radeon->state.pixel.readOffset =
360 radeon->radeonScreen->backOffset;
361 radeon->state.pixel.readPitch =
362 radeon->radeonScreen->backPitch;
363 radeon->state.color.drawOffset =
364 radeon->radeonScreen->backOffset;
365 radeon->state.color.drawPitch =
366 radeon->radeonScreen->backPitch;
367 } else {
368 radeon->state.pixel.readOffset =
369 radeon->radeonScreen->frontOffset;
370 radeon->state.pixel.readPitch =
371 radeon->radeonScreen->frontPitch;
372 radeon->state.color.drawOffset =
373 radeon->radeonScreen->frontOffset;
374 radeon->state.color.drawPitch =
375 radeon->radeonScreen->frontPitch;
376 }
377 }
378
379 /* Move locking out to get reasonable span performance (10x better
380 * than doing this in HW_LOCK above). WaitForIdle() is the main
381 * culprit.
382 */
383
384 static void radeonSpanRenderStart(GLcontext * ctx)
385 {
386 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
387
388 if (IS_FAMILY_R200(radeon))
389 R200_FIREVERTICES((r200ContextPtr)radeon);
390 else
391 r300Flush(ctx);
392
393 LOCK_HARDWARE(radeon);
394 radeonWaitForIdleLocked(radeon);
395
396 /* Read & rewrite the first pixel in the frame buffer. This should
397 * be a noop, right? In fact without this conform fails as reading
398 * from the framebuffer sometimes produces old results -- the
399 * on-card read cache gets mixed up and doesn't notice that the
400 * framebuffer has been updated.
401 *
402 * In the worst case this is buggy too as p might get the wrong
403 * value first time, so really need a hidden pixel somewhere for this.
404 */
405 {
406 int p;
407 volatile int *read_buf =
408 (volatile int *)(radeon->dri.screen->pFB +
409 radeon->state.pixel.readOffset);
410 p = *read_buf;
411 *read_buf = p;
412 }
413 }
414
415 static void radeonSpanRenderFinish(GLcontext * ctx)
416 {
417 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
418
419 _swrast_flush(ctx);
420 UNLOCK_HARDWARE(radeon);
421 }
422
423 void radeonInitSpanFuncs(GLcontext * ctx)
424 {
425 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
426 struct swrast_device_driver *swdd =
427 _swrast_GetDeviceDriverReference(ctx);
428
429 swdd->SetBuffer = radeonSetBuffer;
430
431 switch (radeon->radeonScreen->cpp) {
432 case 2:
433 #if 0
434 swdd->WriteRGBASpan = radeonWriteRGBASpan_RGB565;
435 swdd->WriteRGBSpan = radeonWriteRGBSpan_RGB565;
436 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_RGB565;
437 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_RGB565;
438 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_RGB565;
439 swdd->ReadRGBASpan = radeonReadRGBASpan_RGB565;
440 swdd->ReadRGBAPixels = radeonReadRGBAPixels_RGB565;
441 #endif
442 break;
443
444 case 4:
445 #if 0
446 swdd->WriteRGBASpan = radeonWriteRGBASpan_ARGB8888;
447 swdd->WriteRGBSpan = radeonWriteRGBSpan_ARGB8888;
448 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_ARGB8888;
449 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_ARGB8888;
450 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_ARGB8888;
451 swdd->ReadRGBASpan = radeonReadRGBASpan_ARGB8888;
452 swdd->ReadRGBAPixels = radeonReadRGBAPixels_ARGB8888;
453 #endif
454 break;
455
456 default:
457 break;
458 }
459
460 if (IS_FAMILY_R300(radeon))
461 {
462 switch (radeon->glCtx->Visual.depthBits) {
463 case 16:
464 #if 0
465 swdd->ReadDepthSpan = radeonReadDepthSpan_16_LINEAR;
466 swdd->WriteDepthSpan = radeonWriteDepthSpan_16_LINEAR;
467 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_LINEAR;
468 swdd->ReadDepthPixels = radeonReadDepthPixels_16_LINEAR;
469 swdd->WriteDepthPixels = radeonWriteDepthPixels_16_LINEAR;
470 #endif
471 break;
472
473 case 24:
474 #if 0
475 swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_LINEAR;
476 swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_LINEAR;
477 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_LINEAR;
478 swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_LINEAR;
479 swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_LINEAR;
480
481 swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_LINEAR;
482 swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_LINEAR;
483 swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_LINEAR;
484 swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_LINEAR;
485 #endif
486 break;
487
488 default:
489 break;
490 }
491 }
492 else
493 {
494 switch (radeon->glCtx->Visual.depthBits) {
495 case 16:
496 #if 0
497 swdd->ReadDepthSpan = radeonReadDepthSpan_16_TILE;
498 swdd->WriteDepthSpan = radeonWriteDepthSpan_16_TILE;
499 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_TILE;
500 swdd->ReadDepthPixels = radeonReadDepthPixels_16_TILE;
501 swdd->WriteDepthPixels = radeonWriteDepthPixels_16_TILE;
502 #endif
503 break;
504
505 case 24:
506 #if 0
507 swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_TILE;
508 swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_TILE;
509 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_TILE;
510 swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_TILE;
511 swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_TILE;
512
513 swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_TILE;
514 swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_TILE;
515 swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_TILE;
516 swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_TILE;
517 #endif
518 break;
519
520 default:
521 break;
522 }
523 }
524
525 swdd->SpanRenderStart = radeonSpanRenderStart;
526 swdd->SpanRenderFinish = radeonSpanRenderFinish;
527 }
528
529 /**
530 * Plug in the Get/Put routines for the given driRenderbuffer.
531 */
532 void radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
533 {
534 if (drb->Base.InternalFormat == GL_RGBA) {
535 if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
536 drb->Base.GetRow = radeonReadRGBASpan_RGB565;
537 drb->Base.GetValues = radeonReadRGBAPixels_RGB565;
538 drb->Base.PutRow = radeonWriteRGBASpan_RGB565;
539 drb->Base.PutRowRGB = radeonWriteRGBSpan_RGB565;
540 drb->Base.PutMonoRow = radeonWriteMonoRGBASpan_RGB565;
541 drb->Base.PutValues = radeonWriteRGBAPixels_RGB565;
542 drb->Base.PutMonoValues = radeonWriteMonoRGBAPixels_RGB565;
543 }
544 else {
545 drb->Base.GetRow = radeonReadRGBASpan_ARGB8888;
546 drb->Base.GetValues = radeonReadRGBAPixels_ARGB8888;
547 drb->Base.PutRow = radeonWriteRGBASpan_ARGB8888;
548 drb->Base.PutRowRGB = radeonWriteRGBSpan_ARGB8888;
549 drb->Base.PutMonoRow = radeonWriteMonoRGBASpan_ARGB8888;
550 drb->Base.PutValues = radeonWriteRGBAPixels_ARGB8888;
551 drb->Base.PutMonoValues = radeonWriteMonoRGBAPixels_ARGB8888;
552 }
553 }
554 else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
555 drb->Base.GetRow = radeonReadDepthSpan_16_LINEAR;
556 drb->Base.GetValues = radeonReadDepthPixels_16_LINEAR;
557 drb->Base.PutRow = radeonWriteDepthSpan_16_LINEAR;
558 drb->Base.PutMonoRow = radeonWriteMonoDepthSpan_16_LINEAR;
559 drb->Base.PutValues = radeonWriteDepthPixels_16_LINEAR;
560 drb->Base.PutMonoValues = NULL;
561 }
562 else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
563 drb->Base.GetRow = radeonReadDepthSpan_24_8_LINEAR;
564 drb->Base.GetValues = radeonReadDepthPixels_24_8_LINEAR;
565 drb->Base.PutRow = radeonWriteDepthSpan_24_8_LINEAR;
566 drb->Base.PutMonoRow = radeonWriteMonoDepthSpan_24_8_LINEAR;
567 drb->Base.PutValues = radeonWriteDepthPixels_24_8_LINEAR;
568 drb->Base.PutMonoValues = NULL;
569 }
570 else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
571 drb->Base.GetRow = radeonReadStencilSpan_24_8_LINEAR;
572 drb->Base.GetValues = radeonReadStencilPixels_24_8_LINEAR;
573 drb->Base.PutRow = radeonWriteStencilSpan_24_8_LINEAR;
574 drb->Base.PutMonoRow = radeonWriteMonoStencilSpan_24_8_LINEAR;
575 drb->Base.PutValues = radeonWriteStencilPixels_24_8_LINEAR;
576 drb->Base.PutMonoValues = NULL;
577 }
578 }
579