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[mesa.git] / src / mesa / drivers / dri / r300 / radeon_span.c
1 /**************************************************************************
2
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 /*
36 * Authors:
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
40 *
41 */
42
43 #include "main/glheader.h"
44 #include "swrast/swrast.h"
45
46 #include "r300_state.h"
47 #include "radeon_ioctl.h"
48 #include "r300_ioctl.h"
49 #include "radeon_span.h"
50
51 #include "drirenderbuffer.h"
52
53 #define DBG 0
54
55 /*
56 * Note that all information needed to access pixels in a renderbuffer
57 * should be obtained through the gl_renderbuffer parameter, not per-context
58 * information.
59 */
60 #define LOCAL_VARS \
61 driRenderbuffer *drb = (driRenderbuffer *) rb; \
62 const __DRIdrawablePrivate *dPriv = drb->dPriv; \
63 const GLuint bottom = dPriv->h - 1; \
64 GLubyte *buf = (GLubyte *) drb->flippedData \
65 + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \
66 GLuint p; \
67 (void) p;
68
69 #define LOCAL_DEPTH_VARS \
70 driRenderbuffer *drb = (driRenderbuffer *) rb; \
71 const __DRIdrawablePrivate *dPriv = drb->dPriv; \
72 const GLuint bottom = dPriv->h - 1; \
73 GLuint xo = dPriv->x; \
74 GLuint yo = dPriv->y; \
75 GLubyte *buf = (GLubyte *) drb->Base.Data;
76
77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
78
79 #define Y_FLIP(Y) (bottom - (Y))
80
81 #define HW_LOCK()
82
83 #define HW_UNLOCK()
84
85 /* ================================================================
86 * Color buffer
87 */
88
89 /* 16 bit, RGB565 color spanline and pixel functions
90 */
91 #define SPANTMP_PIXEL_FMT GL_RGB
92 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
93
94 #define TAG(x) radeon##x##_RGB565
95 #define TAG2(x,y) radeon##x##_RGB565##y
96 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
97 #include "spantmp2.h"
98
99 /* 32 bit, ARGB8888 color spanline and pixel functions
100 */
101 #define SPANTMP_PIXEL_FMT GL_BGRA
102 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
103
104 #define TAG(x) radeon##x##_ARGB8888
105 #define TAG2(x,y) radeon##x##_ARGB8888##y
106 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
107 #include "spantmp2.h"
108
109 /* ================================================================
110 * Depth buffer
111 */
112
113 /* The Radeon family has depth tiling on all the time, so we have to convert
114 * the x,y coordinates into the memory bus address (mba) in the same
115 * manner as the engine. In each case, the linear block address (ba)
116 * is calculated, and then wired with x and y to produce the final
117 * memory address.
118 * The chip will do address translation on its own if the surface registers
119 * are set up correctly. It is not quite enough to get it working with hyperz
120 * too...
121 */
122
123 static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
124 {
125 GLuint pitch = drb->pitch;
126 if (drb->depthHasSurface) {
127 return 4 * (x + y * pitch);
128 } else {
129 GLuint ba, address = 0; /* a[0..1] = 0 */
130
131 #ifdef COMPILE_R300
132 ba = (y / 8) * (pitch / 8) + (x / 8);
133 #else
134 ba = (y / 16) * (pitch / 16) + (x / 16);
135 #endif
136
137 address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
138 address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
139 address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
140 address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
141
142 address |= (y & 0x8) << 7; /* a[10] = y[3] */
143 address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
144 address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
145
146 return address;
147 }
148 }
149
150 static INLINE GLuint
151 radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
152 {
153 GLuint pitch = drb->pitch;
154 if (drb->depthHasSurface) {
155 return 2 * (x + y * pitch);
156 } else {
157 GLuint ba, address = 0; /* a[0] = 0 */
158
159 ba = (y / 16) * (pitch / 32) + (x / 32);
160
161 address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
162 address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
163 address |= (x & 0x8) << 4; /* a[7] = x[3] */
164 address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
165 address |= (y & 0x8) << 7; /* a[10] = y[3] */
166 address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
167 address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
168
169 return address;
170 }
171 }
172
173 /* 16-bit depth buffer functions
174 */
175 #define VALUE_TYPE GLushort
176
177 #define WRITE_DEPTH( _x, _y, d ) \
178 *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
179
180 #define READ_DEPTH( d, _x, _y ) \
181 d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
182
183 #define TAG(x) radeon##x##_z16
184 #include "depthtmp.h"
185
186 /* 24 bit depth, 8 bit stencil depthbuffer functions
187 *
188 * Careful: It looks like the R300 uses ZZZS byte order while the R200
189 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
190 */
191 #define VALUE_TYPE GLuint
192
193 #ifdef COMPILE_R300
194 #define WRITE_DEPTH( _x, _y, d ) \
195 do { \
196 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
197 GLuint tmp = *(GLuint *)(buf + offset); \
198 tmp &= 0x000000ff; \
199 tmp |= ((d << 8) & 0xffffff00); \
200 *(GLuint *)(buf + offset) = tmp; \
201 } while (0)
202 #else
203 #define WRITE_DEPTH( _x, _y, d ) \
204 do { \
205 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
206 GLuint tmp = *(GLuint *)(buf + offset); \
207 tmp &= 0xff000000; \
208 tmp |= ((d) & 0x00ffffff); \
209 *(GLuint *)(buf + offset) = tmp; \
210 } while (0)
211 #endif
212
213 #ifdef COMPILE_R300
214 #define READ_DEPTH( d, _x, _y ) \
215 do { \
216 d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
217 _y + yo )) & 0xffffff00) >> 8; \
218 }while(0)
219 #else
220 #define READ_DEPTH( d, _x, _y ) \
221 d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
222 _y + yo )) & 0x00ffffff;
223 #endif
224
225 #define TAG(x) radeon##x##_z24_s8
226 #include "depthtmp.h"
227
228 /* ================================================================
229 * Stencil buffer
230 */
231
232 /* 24 bit depth, 8 bit stencil depthbuffer functions
233 */
234 #ifdef COMPILE_R300
235 #define WRITE_STENCIL( _x, _y, d ) \
236 do { \
237 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
238 GLuint tmp = *(GLuint *)(buf + offset); \
239 tmp &= 0xffffff00; \
240 tmp |= (d) & 0xff; \
241 *(GLuint *)(buf + offset) = tmp; \
242 } while (0)
243 #else
244 #define WRITE_STENCIL( _x, _y, d ) \
245 do { \
246 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
247 GLuint tmp = *(GLuint *)(buf + offset); \
248 tmp &= 0x00ffffff; \
249 tmp |= (((d) & 0xff) << 24); \
250 *(GLuint *)(buf + offset) = tmp; \
251 } while (0)
252 #endif
253
254 #ifdef COMPILE_R300
255 #define READ_STENCIL( d, _x, _y ) \
256 do { \
257 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
258 GLuint tmp = *(GLuint *)(buf + offset); \
259 d = tmp & 0x000000ff; \
260 } while (0)
261 #else
262 #define READ_STENCIL( d, _x, _y ) \
263 do { \
264 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
265 GLuint tmp = *(GLuint *)(buf + offset); \
266 d = (tmp & 0xff000000) >> 24; \
267 } while (0)
268 #endif
269
270 #define TAG(x) radeon##x##_z24_s8
271 #include "stenciltmp.h"
272
273 /* Move locking out to get reasonable span performance (10x better
274 * than doing this in HW_LOCK above). WaitForIdle() is the main
275 * culprit.
276 */
277
278 static void radeonSpanRenderStart(GLcontext * ctx)
279 {
280 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
281 #ifdef COMPILE_R300
282 r300ContextPtr r300 = (r300ContextPtr) rmesa;
283 R300_FIREVERTICES(r300);
284 #else
285 RADEON_FIREVERTICES(rmesa);
286 #endif
287 LOCK_HARDWARE(rmesa);
288 radeonWaitForIdleLocked(rmesa);
289
290 /* Read the first pixel in the frame buffer. This should
291 * be a noop, right? In fact without this conform fails as reading
292 * from the framebuffer sometimes produces old results -- the
293 * on-card read cache gets mixed up and doesn't notice that the
294 * framebuffer has been updated.
295 *
296 * Note that we should probably be reading some otherwise unused
297 * region of VRAM, otherwise we might get incorrect results when
298 * reading pixels from the top left of the screen.
299 *
300 * I found this problem on an R420 with glean's texCube test.
301 * Note that the R200 span code also *writes* the first pixel in the
302 * framebuffer, but I've found this to be unnecessary.
303 * -- Nicolai Hähnle, June 2008
304 */
305 {
306 int p;
307 driRenderbuffer *drb =
308 (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0];
309 volatile int *buf =
310 (volatile int *)(rmesa->dri.screen->pFB + drb->offset);
311 p = *buf;
312 }
313 }
314
315 static void radeonSpanRenderFinish(GLcontext * ctx)
316 {
317 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
318 _swrast_flush(ctx);
319 UNLOCK_HARDWARE(rmesa);
320 }
321
322 void radeonInitSpanFuncs(GLcontext * ctx)
323 {
324 struct swrast_device_driver *swdd =
325 _swrast_GetDeviceDriverReference(ctx);
326 swdd->SpanRenderStart = radeonSpanRenderStart;
327 swdd->SpanRenderFinish = radeonSpanRenderFinish;
328 }
329
330 /**
331 * Plug in the Get/Put routines for the given driRenderbuffer.
332 */
333 void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
334 {
335 if (drb->Base.InternalFormat == GL_RGBA) {
336 if (vis->redBits == 5 && vis->greenBits == 6
337 && vis->blueBits == 5) {
338 radeonInitPointers_RGB565(&drb->Base);
339 } else {
340 radeonInitPointers_ARGB8888(&drb->Base);
341 }
342 } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
343 radeonInitDepthPointers_z16(&drb->Base);
344 } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
345 radeonInitDepthPointers_z24_s8(&drb->Base);
346 } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
347 radeonInitStencilPointers_z24_s8(&drb->Base);
348 }
349 }