src/mesa/drivers/dri/r300/radeon_span.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   5 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   6                      VA Linux Systems Inc., Fremont, California.
   7
   8 The Weather Channel (TM) funded Tungsten Graphics to develop the
   9 initial release of the Radeon 8500 driver under the XFree86 license.
  10 This notice must be preserved.
  11
  12 All Rights Reserved.
  13
  14 Permission is hereby granted, free of charge, to any person obtaining
  15 a copy of this software and associated documentation files (the
  16 "Software"), to deal in the Software without restriction, including
  17 without limitation the rights to use, copy, modify, merge, publish,
  18 distribute, sublicense, and/or sell copies of the Software, and to
  19 permit persons to whom the Software is furnished to do so, subject to
  20 the following conditions:
  21
  22 The above copyright notice and this permission notice (including the
  23 next paragraph) shall be included in all copies or substantial
  24 portions of the Software.
  25
  26 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  29 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  30 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  31 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  32 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  33
  34 **************************************************************************/
  35
  36 /*
  37  * Authors:
  38  *   Kevin E. Martin <martin@valinux.com>
  39  *   Gareth Hughes <gareth@valinux.com>
  40  *   Keith Whitwell <keith@tungstengraphics.com>
  41  *
  42  */
  43 #include <unistd.h>
  44 #include "glheader.h"
  45 #include "imports.h"
  46 #include "swrast/swrast.h"
  47
  48 #include "r300_state.h"
  49 #include "radeon_ioctl.h"
  50 #include "r300_ioctl.h"
  51 #include "radeon_span.h"
  52
  53 #include "drirenderbuffer.h"
  54
  55
  56 #define DBG 0
  57
  58
  59 /*
  60  * Note that all information needed to access pixels in a renderbuffer
  61  * should be obtained through the gl_renderbuffer parameter, not per-context
  62  * information.
  63  */
  64 #define LOCAL_VARS                                              \
  65    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  66    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  67    const GLuint bottom = dPriv->h - 1;                          \
  68    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  69       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  70    GLuint p;                                                    \
  71    (void) p;
  72
  73 #define LOCAL_DEPTH_VARS                                \
  74    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  75    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  76    const GLuint bottom = dPriv->h - 1;                  \
  77    GLuint xo = dPriv->x;                                \
  78    GLuint yo = dPriv->y;                                \
  79    GLubyte *buf = (GLubyte *) drb->Base.Data;
  80
  81 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  82
  83 #define Y_FLIP(Y) (bottom - (Y))
  84
  85 #define HW_LOCK()
  86
  87 #define HW_UNLOCK()
  88
  89
  90
  91 /* ================================================================
  92  * Color buffer
  93  */
  94
  95 /* 16 bit, RGB565 color spanline and pixel functions
  96  */
  97 #define SPANTMP_PIXEL_FMT GL_RGB
  98 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  99
 100 #define TAG(x)    radeon##x##_RGB565
 101 #define TAG2(x,y) radeon##x##_RGB565##y
 102 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
 103 #include "spantmp2.h"
 104
 105
 106 /* 32 bit, ARGB8888 color spanline and pixel functions
 107  */
 108 #define SPANTMP_PIXEL_FMT GL_BGRA
 109 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 110
 111 #define TAG(x)    radeon##x##_ARGB8888
 112 #define TAG2(x,y) radeon##x##_ARGB8888##y
 113 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 114 #include "spantmp2.h"
 115
 116
 117 /* ================================================================
 118  * Depth buffer
 119  */
 120
 121 /* The Radeon family has depth tiling on all the time, so we have to convert
 122  * the x,y coordinates into the memory bus address (mba) in the same
 123  * manner as the engine.  In each case, the linear block address (ba)
 124  * is calculated, and then wired with x and y to produce the final
 125  * memory address.
 126  * The chip will do address translation on its own if the surface registers
 127  * are set up correctly. It is not quite enough to get it working with hyperz
 128  * too...
 129  */
 130
 131 static GLuint
 132 radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
 133 {
 134    GLuint pitch = drb->pitch;
 135    if (1 /*|| drb->depthHasSurface */) {
 136       return 4 * (x + y * pitch);
 137    }
 138    else {
 139       GLuint ba, address = 0;                   /* a[0..1] = 0           */
 140
 141       ba = (y / 8) * (pitch / 8) + (x / 8);
 142
 143       address |= (x & 0x7) << 2;                /* a[2..4] = x[0..2]     */
 144       address |= (y & 0x3) << 5;                /* a[5..6] = y[0..1]     */
 145       address |=
 146          (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;  /* a[7]    = x[4] ^ y[2] */
 147       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 148
 149       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 150       address |=
 151          (((x & 0x8) << 1) ^ (y & 0x10)) << 7;  /* a[11]   = x[3] ^ y[4] */
 152       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 153
 154       return address;
 155    }
 156 }
 157
 158
 159 static INLINE GLuint
 160 radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
 161 {
 162    GLuint pitch = drb->pitch;
 163    if (1 /*|| drb->depthHasSurface */) {
 164       return 2 * (x + y * pitch);
 165    }
 166    else {
 167       GLuint ba, address = 0;                   /* a[0]    = 0           */
 168
 169       ba = (y / 16) * (pitch / 32) + (x / 32);
 170
 171       address |= (x & 0x7) << 1;                /* a[1..3] = x[0..2]     */
 172       address |= (y & 0x7) << 4;                /* a[4..6] = y[0..2]     */
 173       address |= (x & 0x8) << 4;                /* a[7]    = x[3]        */
 174       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 175       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 176       address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11]   = x[4] ^ y[4] */
 177       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 178
 179       return address;
 180    }
 181 }
 182
 183
 184 /* 16-bit depth buffer functions
 185  */
 186 #define WRITE_DEPTH( _x, _y, d )                                        \
 187    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 188
 189 #define READ_DEPTH( d, _x, _y )                                         \
 190    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 191
 192 #define TAG(x) radeon##x##_z16
 193 #include "depthtmp.h"
 194
 195
 196 /* 24 bit depth, 8 bit stencil depthbuffer functions
 197  *
 198  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 199  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 200  */
 201 #define WRITE_DEPTH( _x, _y, d )                                        \
 202 do {                                                                    \
 203    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 204    GLuint tmp = *(GLuint *)(buf + offset);                              \
 205    tmp &= 0x000000ff;                                                   \
 206    tmp |= ((d << 8) & 0xffffff00);                                      \
 207    *(GLuint *)(buf + offset) = tmp;                                     \
 208 } while (0)
 209
 210 #define READ_DEPTH( d, _x, _y )                                         \
 211   do { \
 212     d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                \
 213                                          _y + yo )) & 0xffffff00) >> 8; \
 214   }while(0)
 215
 216 #define TAG(x) radeon##x##_z24_s8
 217 #include "depthtmp.h"
 218
 219
 220 /* ================================================================
 221  * Stencil buffer
 222  */
 223
 224 /* 24 bit depth, 8 bit stencil depthbuffer functions
 225  */
 226 #define WRITE_STENCIL( _x, _y, d )                                      \
 227 do {                                                                    \
 228    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 229    GLuint tmp = *(GLuint *)(buf + offset);                              \
 230    tmp &= 0xffffff00;                                                   \
 231    tmp |= (d) & 0xff;                                                   \
 232    *(GLuint *)(buf + offset) = tmp;                                     \
 233 } while (0)
 234
 235 #define READ_STENCIL( d, _x, _y )                                       \
 236 do {                                                                    \
 237    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 238    GLuint tmp = *(GLuint *)(buf + offset);                              \
 239    d = tmp & 0x000000ff;                                                \
 240 } while (0)
 241
 242 #define TAG(x) radeon##x##_z24_s8
 243 #include "stenciltmp.h"
 244
 245
 246
 247 /* Move locking out to get reasonable span performance (10x better
 248  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 249  * culprit.
 250  */
 251
 252 static void radeonSpanRenderStart( GLcontext *ctx )
 253 {
 254    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 255    {
 256         static int first = 1;
 257         r300ContextPtr r300 = (r300ContextPtr)rmesa;
 258
 259         if (first) {
 260                 r300->span_dlocking = getenv("R300_SPAN_DISABLE_LOCKING") ? 1 : 0;
 261                 if (r300->span_dlocking == 0) {
 262                         fprintf(stderr, "Try R300_SPAN_DISABLE_LOCKING env var if this hangs.\n");
 263                         fflush(stderr);
 264                         sleep(1);
 265                 }
 266                 first = 0;
 267         }
 268
 269         if (r300->span_dlocking) {
 270                 r300Flush(ctx);
 271                 LOCK_HARDWARE( rmesa );
 272                 radeonWaitForIdleLocked( rmesa );
 273                 UNLOCK_HARDWARE( rmesa );
 274
 275                 return;
 276         }
 277    }
 278    //   R300_FIREVERTICES( rmesa );
 279    // old code has flush
 280    r300Flush(ctx);
 281    LOCK_HARDWARE( rmesa );
 282    radeonWaitForIdleLocked( rmesa );
 283 }
 284
 285 static void radeonSpanRenderFinish( GLcontext *ctx )
 286 {
 287    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 288    r300ContextPtr r300 = (r300ContextPtr)rmesa;
 289    _swrast_flush( ctx );
 290    if (r300->span_dlocking == 0)
 291         UNLOCK_HARDWARE( rmesa );
 292 }
 293
 294 void radeonInitSpanFuncs( GLcontext *ctx )
 295 {
 296    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 297    swdd->SpanRenderStart          = radeonSpanRenderStart;
 298    swdd->SpanRenderFinish         = radeonSpanRenderFinish;
 299 }
 300
 301
 302 /**
 303  * Plug in the Get/Put routines for the given driRenderbuffer.
 304  */
 305 void
 306 radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
 307 {
 308    if (drb->Base.InternalFormat == GL_RGBA) {
 309       if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
 310          radeonInitPointers_RGB565(&drb->Base);
 311       }
 312       else {
 313          radeonInitPointers_ARGB8888(&drb->Base);
 314       }
 315    }
 316    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 317       radeonInitDepthPointers_z16(&drb->Base);
 318    }
 319    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 320       radeonInitDepthPointers_z24_s8(&drb->Base);
 321    }
 322    else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 323       radeonInitStencilPointers_z24_s8(&drb->Base);
 324    }
 325 }