2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "swrast/swrast.h"
40 #include "r200_context.h"
41 #include "radeon_ioctl.h"
42 #include "r300_ioctl.h"
43 #include "radeon_span.h"
48 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
49 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
50 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
51 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
52 GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
53 GLuint height = dPriv->h; \
54 char *buf = (char *)(sPriv->pFB + \
55 radeon->state.color.drawOffset + \
56 (dPriv->x * radeonScreen->cpp) + \
57 (dPriv->y * pitch)); \
58 char *read_buf = (char *)(sPriv->pFB + \
59 radeon->state.pixel.readOffset + \
60 (dPriv->x * radeonScreen->cpp) + \
61 (dPriv->y * pitch)); \
63 (void) read_buf; (void) buf; (void) p
65 #define LOCAL_DEPTH_VARS \
66 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
67 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
68 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
69 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
70 GLuint height = dPriv->h; \
71 GLuint xo = dPriv->x; \
72 GLuint yo = dPriv->y; \
73 char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \
74 GLuint pitch = radeonScreen->depthPitch; \
75 (void) buf; (void) pitch
77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
79 #define CLIPPIXEL( _x, _y ) \
80 ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
82 #define CLIPSPAN( _x, _y, _n, _x1, _n1, _i ) \
83 if ( _y < miny || _y >= maxy ) { \
88 if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
89 if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx); \
92 #define Y_FLIP( _y ) (height - _y - 1)
96 #define HW_CLIPLOOP() \
98 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
99 int _nc = dPriv->numClipRects; \
102 int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \
103 int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \
104 int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \
105 int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
107 #define HW_ENDCLIPLOOP() \
113 /* ================================================================
117 /* 16 bit, RGB565 color spanline and pixel functions
119 #define INIT_MONO_PIXEL(p, color) \
120 p = PACK_COLOR_565( color[0], color[1], color[2] )
122 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
123 *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) | \
124 (((int)g & 0xfc) << 3) | \
125 (((int)b & 0xf8) >> 3))
127 #define WRITE_PIXEL( _x, _y, p ) \
128 *(GLushort *)(buf + _x*2 + _y*pitch) = p
130 #define READ_RGBA( rgba, _x, _y ) \
132 GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch); \
133 rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
134 rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
135 rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \
139 #define TAG(x) radeon##x##_RGB565
142 /* 32 bit, ARGB8888 color spanline and pixel functions
144 #undef INIT_MONO_PIXEL
145 #define INIT_MONO_PIXEL(p, color) \
146 p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
148 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
150 *(GLuint *)(buf + _x*4 + _y*pitch) = ((b << 0) | \
156 #define WRITE_PIXEL( _x, _y, p ) \
158 *(GLuint *)(buf + _x*4 + _y*pitch) = p; \
161 #define READ_RGBA( rgba, _x, _y ) \
163 volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
165 rgba[0] = (p >> 16) & 0xff; \
166 rgba[1] = (p >> 8) & 0xff; \
167 rgba[2] = (p >> 0) & 0xff; \
168 rgba[3] = (p >> 24) & 0xff; \
171 #define TAG(x) radeon##x##_ARGB8888
174 /* ================================================================
178 /* The Radeon family has depth tiling on all the time, so we have to convert
179 * the x,y coordinates into the memory bus address (mba) in the same
180 * manner as the engine. In each case, the linear block address (ba)
181 * is calculated, and then wired with x and y to produce the final
185 #define BIT(x,b) ((x & (1<<b))>>b)
186 static GLuint
radeon_mba_z32(radeonContextPtr radeon
, GLint x
, GLint y
)
188 GLuint pitch
= radeon
->radeonScreen
->depthPitch
;
190 ((y
& 0x3FF) >> 4) * ((pitch
& 0xFFF) >> 5) + ((x
& 0x3FF) >> 5);
192 (BIT(x
, 0) << 2) | (BIT(y
, 0) << 3) | (BIT(x
, 1) << 4) | (BIT(y
, 1)
194 (BIT(x
, 3) << 6) | (BIT(x
, 4) << 7) | (BIT(x
, 2) << 8) | (BIT(y
, 2)
197 (((pitch
& 0x20) ? (b
& 0x01) : ((b
& 0x01) ^ (BIT(y
, 4)))) << 11) |
202 static GLuint
radeon_mba_z16(radeonContextPtr radeon
, GLint x
, GLint y
)
204 GLuint pitch
= radeon
->radeonScreen
->depthPitch
;
206 ((y
& 0x3FF) >> 4) * ((pitch
& 0xFFF) >> 6) + ((x
& 0x3FF) >> 6);
208 (BIT(x
, 0) << 1) | (BIT(y
, 0) << 2) | (BIT(x
, 1) << 3) | (BIT(y
, 1)
210 (BIT(x
, 2) << 5) | (BIT(x
, 4) << 6) | (BIT(x
, 5) << 7) | (BIT(x
, 3)
212 (BIT(y
, 2) << 9) | (BIT(y
, 3) << 10) |
213 (((pitch
& 0x40) ? (b
& 0x01) : ((b
& 0x01) ^ (BIT(y
, 4)))) << 11) |
219 /* 16-bit depth buffer functions
221 #define WRITE_DEPTH( _x, _y, d ) \
222 *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo )) = d;
224 #define READ_DEPTH( d, _x, _y ) \
225 d = *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo ));
227 #define TAG(x) radeon##x##_16_TILE
228 #include "depthtmp.h"
230 /* 24 bit depth, 8 bit stencil depthbuffer functions
232 #define WRITE_DEPTH( _x, _y, d ) \
234 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
235 GLuint tmp = *(GLuint *)(buf + offset); \
237 tmp |= ((d) & 0x00ffffff); \
238 *(GLuint *)(buf + offset) = tmp; \
241 #define READ_DEPTH( d, _x, _y ) \
242 d = *(GLuint *)(buf + radeon_mba_z32( radeon, _x + xo, \
243 _y + yo )) & 0x00ffffff;
245 #define TAG(x) radeon##x##_24_8_TILE
246 #include "depthtmp.h"
248 /* 16-bit depth buffer functions
250 #define WRITE_DEPTH( _x, _y, d ) \
251 *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 ) = d;
253 #define READ_DEPTH( d, _x, _y ) \
254 d = *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 );
256 #define TAG(x) radeon##x##_16_LINEAR
257 #include "depthtmp.h"
259 /* 24 bit depth, 8 bit stencil depthbuffer functions
261 * Careful: It looks like the R300 uses ZZZS byte order while the R200
262 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
264 #define WRITE_DEPTH( _x, _y, d ) \
266 GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \
267 GLuint tmp = *(GLuint *)(buf + offset); \
269 tmp |= ((d << 8) & 0xffffff00); \
270 *(GLuint *)(buf + offset) = tmp; \
273 #define READ_DEPTH( d, _x, _y ) \
274 d = (*(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0xffffff00) >> 8;
276 #define TAG(x) radeon##x##_24_8_LINEAR
277 #include "depthtmp.h"
279 /* ================================================================
283 /* 24 bit depth, 8 bit stencil depthbuffer functions
285 #define WRITE_STENCIL( _x, _y, d ) \
287 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
288 GLuint tmp = *(GLuint *)(buf + offset); \
290 tmp |= (((d) & 0xff) << 24); \
291 *(GLuint *)(buf + offset) = tmp; \
294 #define READ_STENCIL( d, _x, _y ) \
296 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
297 GLuint tmp = *(GLuint *)(buf + offset); \
302 #define TAG(x) radeon##x##_24_8_TILE
303 #include "stenciltmp.h"
305 /* 24 bit depth, 8 bit stencil depthbuffer functions
307 #define WRITE_STENCIL( _x, _y, d ) \
309 GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \
310 GLuint tmp = *(GLuint *)(buf + offset); \
312 tmp |= (((d) & 0xff) << 24); \
313 *(GLuint *)(buf + offset) = tmp; \
316 #define READ_STENCIL( d, _x, _y ) \
318 GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \
319 GLuint tmp = *(GLuint *)(buf + offset); \
324 #define TAG(x) radeon##x##_24_8_LINEAR
325 #include "stenciltmp.h"
328 * This function is called to specify which buffer to read and write
329 * for software rasterization (swrast) fallbacks. This doesn't necessarily
330 * correspond to glDrawBuffer() or glReadBuffer() calls.
332 static void radeonSetBuffer(GLcontext
* ctx
,
333 GLframebuffer
* colorBuffer
, GLuint bufferBit
)
335 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
339 case DD_FRONT_LEFT_BIT
:
343 case DD_BACK_LEFT_BIT
:
348 _mesa_problem(ctx
, "Bad bufferBit in %s", __FUNCTION__
);
352 if (radeon
->doPageFlip
&& radeon
->sarea
->pfCurrentPage
== 1)
356 fprintf(stderr
, "%s: using %s buffer\n", __FUNCTION__
,
357 buffer
? "back" : "front");
361 radeon
->state
.pixel
.readOffset
=
362 radeon
->radeonScreen
->backOffset
;
363 radeon
->state
.pixel
.readPitch
=
364 radeon
->radeonScreen
->backPitch
;
365 radeon
->state
.color
.drawOffset
=
366 radeon
->radeonScreen
->backOffset
;
367 radeon
->state
.color
.drawPitch
=
368 radeon
->radeonScreen
->backPitch
;
370 radeon
->state
.pixel
.readOffset
=
371 radeon
->radeonScreen
->frontOffset
;
372 radeon
->state
.pixel
.readPitch
=
373 radeon
->radeonScreen
->frontPitch
;
374 radeon
->state
.color
.drawOffset
=
375 radeon
->radeonScreen
->frontOffset
;
376 radeon
->state
.color
.drawPitch
=
377 radeon
->radeonScreen
->frontPitch
;
381 /* Move locking out to get reasonable span performance (10x better
382 * than doing this in HW_LOCK above). WaitForIdle() is the main
386 static void radeonSpanRenderStart(GLcontext
* ctx
)
388 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
390 if (IS_FAMILY_R200(radeon
))
391 R200_FIREVERTICES((r200ContextPtr
)radeon
);
395 LOCK_HARDWARE(radeon
);
396 radeonWaitForIdleLocked(radeon
);
398 /* Read & rewrite the first pixel in the frame buffer. This should
399 * be a noop, right? In fact without this conform fails as reading
400 * from the framebuffer sometimes produces old results -- the
401 * on-card read cache gets mixed up and doesn't notice that the
402 * framebuffer has been updated.
404 * In the worst case this is buggy too as p might get the wrong
405 * value first time, so really need a hidden pixel somewhere for this.
409 volatile int *read_buf
=
410 (volatile int *)(radeon
->dri
.screen
->pFB
+
411 radeon
->state
.pixel
.readOffset
);
417 static void radeonSpanRenderFinish(GLcontext
* ctx
)
419 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
422 UNLOCK_HARDWARE(radeon
);
425 void radeonInitSpanFuncs(GLcontext
* ctx
)
427 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
428 struct swrast_device_driver
*swdd
=
429 _swrast_GetDeviceDriverReference(ctx
);
431 swdd
->SetBuffer
= radeonSetBuffer
;
433 switch (radeon
->radeonScreen
->cpp
) {
435 swdd
->WriteRGBASpan
= radeonWriteRGBASpan_RGB565
;
436 swdd
->WriteRGBSpan
= radeonWriteRGBSpan_RGB565
;
437 swdd
->WriteMonoRGBASpan
= radeonWriteMonoRGBASpan_RGB565
;
438 swdd
->WriteRGBAPixels
= radeonWriteRGBAPixels_RGB565
;
439 swdd
->WriteMonoRGBAPixels
= radeonWriteMonoRGBAPixels_RGB565
;
440 swdd
->ReadRGBASpan
= radeonReadRGBASpan_RGB565
;
441 swdd
->ReadRGBAPixels
= radeonReadRGBAPixels_RGB565
;
445 swdd
->WriteRGBASpan
= radeonWriteRGBASpan_ARGB8888
;
446 swdd
->WriteRGBSpan
= radeonWriteRGBSpan_ARGB8888
;
447 swdd
->WriteMonoRGBASpan
= radeonWriteMonoRGBASpan_ARGB8888
;
448 swdd
->WriteRGBAPixels
= radeonWriteRGBAPixels_ARGB8888
;
449 swdd
->WriteMonoRGBAPixels
= radeonWriteMonoRGBAPixels_ARGB8888
;
450 swdd
->ReadRGBASpan
= radeonReadRGBASpan_ARGB8888
;
451 swdd
->ReadRGBAPixels
= radeonReadRGBAPixels_ARGB8888
;
458 if (IS_FAMILY_R300(radeon
))
460 switch (radeon
->glCtx
->Visual
.depthBits
) {
462 swdd
->ReadDepthSpan
= radeonReadDepthSpan_16_LINEAR
;
463 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_16_LINEAR
;
464 swdd
->WriteMonoDepthSpan
= radeonWriteMonoDepthSpan_16_LINEAR
;
465 swdd
->ReadDepthPixels
= radeonReadDepthPixels_16_LINEAR
;
466 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_16_LINEAR
;
470 swdd
->ReadDepthSpan
= radeonReadDepthSpan_24_8_LINEAR
;
471 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_24_8_LINEAR
;
472 swdd
->WriteMonoDepthSpan
= radeonWriteMonoDepthSpan_24_8_LINEAR
;
473 swdd
->ReadDepthPixels
= radeonReadDepthPixels_24_8_LINEAR
;
474 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_24_8_LINEAR
;
476 swdd
->ReadStencilSpan
= radeonReadStencilSpan_24_8_LINEAR
;
477 swdd
->WriteStencilSpan
= radeonWriteStencilSpan_24_8_LINEAR
;
478 swdd
->ReadStencilPixels
= radeonReadStencilPixels_24_8_LINEAR
;
479 swdd
->WriteStencilPixels
= radeonWriteStencilPixels_24_8_LINEAR
;
488 switch (radeon
->glCtx
->Visual
.depthBits
) {
490 swdd
->ReadDepthSpan
= radeonReadDepthSpan_16_TILE
;
491 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_16_TILE
;
492 swdd
->WriteMonoDepthSpan
= radeonWriteMonoDepthSpan_16_TILE
;
493 swdd
->ReadDepthPixels
= radeonReadDepthPixels_16_TILE
;
494 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_16_TILE
;
498 swdd
->ReadDepthSpan
= radeonReadDepthSpan_24_8_TILE
;
499 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_24_8_TILE
;
500 swdd
->WriteMonoDepthSpan
= radeonWriteMonoDepthSpan_24_8_TILE
;
501 swdd
->ReadDepthPixels
= radeonReadDepthPixels_24_8_TILE
;
502 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_24_8_TILE
;
504 swdd
->ReadStencilSpan
= radeonReadStencilSpan_24_8_TILE
;
505 swdd
->WriteStencilSpan
= radeonWriteStencilSpan_24_8_TILE
;
506 swdd
->ReadStencilPixels
= radeonReadStencilPixels_24_8_TILE
;
507 swdd
->WriteStencilPixels
= radeonWriteStencilPixels_24_8_TILE
;
515 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
516 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;