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added support for GL_ARB_draw_buffers
[mesa.git] / src / mesa / drivers / dri / r300 / radeon_span.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include "glheader.h"
36 #include "imports.h"
37 #include "swrast/swrast.h"
38 #include "colormac.h"
39
40 #include "r200_context.h"
41 #include "radeon_ioctl.h"
42 #include "r300_ioctl.h"
43 #include "radeon_span.h"
44
45 #define DBG 0
46
47 #define LOCAL_VARS \
48 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
49 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
50 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
51 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
52 GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
53 GLuint height = dPriv->h; \
54 char *buf = (char *)(sPriv->pFB + \
55 radeon->state.color.drawOffset + \
56 (dPriv->x * radeonScreen->cpp) + \
57 (dPriv->y * pitch)); \
58 char *read_buf = (char *)(sPriv->pFB + \
59 radeon->state.pixel.readOffset + \
60 (dPriv->x * radeonScreen->cpp) + \
61 (dPriv->y * pitch)); \
62 GLuint p; \
63 (void) read_buf; (void) buf; (void) p
64
65 #define LOCAL_DEPTH_VARS \
66 radeonContextPtr radeon = RADEON_CONTEXT(ctx); \
67 radeonScreenPtr radeonScreen = radeon->radeonScreen; \
68 __DRIscreenPrivate *sPriv = radeon->dri.screen; \
69 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
70 GLuint height = dPriv->h; \
71 GLuint xo = dPriv->x; \
72 GLuint yo = dPriv->y; \
73 char *buf = (char *)(sPriv->pFB + radeon->radeonScreen->depthOffset); \
74 GLuint pitch = radeon->radeonScreen->depthPitch; \
75 (void) buf; (void) pitch
76
77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
78
79 #define CLIPPIXEL( _x, _y ) \
80 ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
81
82 #define CLIPSPAN( _x, _y, _n, _x1, _n1, _i ) \
83 if ( _y < miny || _y >= maxy ) { \
84 _n1 = 0, _x1 = x; \
85 } else { \
86 _n1 = _n; \
87 _x1 = _x; \
88 if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
89 if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx); \
90 }
91
92 #define Y_FLIP( _y ) (height - _y - 1)
93
94 #define HW_LOCK()
95
96 #define HW_CLIPLOOP() \
97 do { \
98 __DRIdrawablePrivate *dPriv = radeon->dri.drawable; \
99 int _nc = dPriv->numClipRects; \
100 \
101 while ( _nc-- ) { \
102 int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \
103 int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \
104 int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \
105 int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
106
107 #define HW_ENDCLIPLOOP() \
108 } \
109 } while (0)
110
111 #define HW_UNLOCK()
112
113 /* ================================================================
114 * Color buffer
115 */
116
117 /* 16 bit, RGB565 color spanline and pixel functions
118 */
119 #define INIT_MONO_PIXEL(p, color) \
120 p = PACK_COLOR_565( color[0], color[1], color[2] )
121
122 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
123 *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) | \
124 (((int)g & 0xfc) << 3) | \
125 (((int)b & 0xf8) >> 3))
126
127 #define WRITE_PIXEL( _x, _y, p ) \
128 *(GLushort *)(buf + _x*2 + _y*pitch) = p
129
130 #define READ_RGBA( rgba, _x, _y ) \
131 do { \
132 GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch); \
133 rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
134 rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
135 rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \
136 rgba[3] = 0xff; \
137 } while (0)
138
139 #define TAG(x) radeon##x##_RGB565
140 #include "spantmp.h"
141
142 /* 32 bit, ARGB8888 color spanline and pixel functions
143 */
144 #undef INIT_MONO_PIXEL
145 #define INIT_MONO_PIXEL(p, color) \
146 p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
147
148 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
149 do { \
150 *(GLuint *)(buf + _x*4 + _y*pitch) = ((b << 0) | \
151 (g << 8) | \
152 (r << 16) | \
153 (a << 24) ); \
154 } while (0)
155
156 #define WRITE_PIXEL( _x, _y, p ) \
157 do { \
158 *(GLuint *)(buf + _x*4 + _y*pitch) = p; \
159 } while (0)
160
161 #define READ_RGBA( rgba, _x, _y ) \
162 do { \
163 volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
164 GLuint p = *ptr; \
165 rgba[0] = (p >> 16) & 0xff; \
166 rgba[1] = (p >> 8) & 0xff; \
167 rgba[2] = (p >> 0) & 0xff; \
168 rgba[3] = (p >> 24) & 0xff; \
169 } while (0)
170
171 #define TAG(x) radeon##x##_ARGB8888
172 #include "spantmp.h"
173
174 /* ================================================================
175 * Depth buffer
176 */
177
178 /* The Radeon family has depth tiling on all the time, so we have to convert
179 * the x,y coordinates into the memory bus address (mba) in the same
180 * manner as the engine. In each case, the linear block address (ba)
181 * is calculated, and then wired with x and y to produce the final
182 * memory address.
183 */
184
185 #define BIT(x,b) ((x & (1<<b))>>b)
186 static GLuint radeon_mba_z32(radeonContextPtr radeon, GLint x, GLint y)
187 {
188 GLuint pitch = radeon->radeonScreen->depthPitch;
189 GLuint b =
190 ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x3FF) >> 5);
191 GLuint a =
192 (BIT(x, 0) << 2) | (BIT(y, 0) << 3) | (BIT(x, 1) << 4) | (BIT(y, 1)
193 << 5) |
194 (BIT(x, 3) << 6) | (BIT(x, 4) << 7) | (BIT(x, 2) << 8) | (BIT(y, 2)
195 << 9) |
196 (BIT(y, 3) << 10) |
197 (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
198 ((b >> 1) << 12);
199 return a;
200 }
201
202 static GLuint radeon_mba_z16(radeonContextPtr radeon, GLint x, GLint y)
203 {
204 GLuint pitch = radeon->radeonScreen->depthPitch;
205 GLuint b =
206 ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x3FF) >> 6);
207 GLuint a =
208 (BIT(x, 0) << 1) | (BIT(y, 0) << 2) | (BIT(x, 1) << 3) | (BIT(y, 1)
209 << 4) |
210 (BIT(x, 2) << 5) | (BIT(x, 4) << 6) | (BIT(x, 5) << 7) | (BIT(x, 3)
211 << 8) |
212 (BIT(y, 2) << 9) | (BIT(y, 3) << 10) |
213 (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
214 ((b >> 1) << 12);
215 return a;
216 }
217
218
219 /* 16-bit depth buffer functions
220 */
221 #define WRITE_DEPTH( _x, _y, d ) \
222 *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo )) = d;
223
224 #define READ_DEPTH( d, _x, _y ) \
225 d = *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo ));
226
227 #define TAG(x) radeon##x##_16_TILE
228 #include "depthtmp.h"
229
230 /* 24 bit depth, 8 bit stencil depthbuffer functions
231 */
232 #define WRITE_DEPTH( _x, _y, d ) \
233 do { \
234 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
235 GLuint tmp = *(GLuint *)(buf + offset); \
236 tmp &= 0xff000000; \
237 tmp |= ((d) & 0x00ffffff); \
238 *(GLuint *)(buf + offset) = tmp; \
239 } while (0)
240
241 #define READ_DEPTH( d, _x, _y ) \
242 d = *(GLuint *)(buf + radeon_mba_z32( radeon, _x + xo, \
243 _y + yo )) & 0x00ffffff;
244
245 #define TAG(x) radeon##x##_24_8_TILE
246 #include "depthtmp.h"
247
248 /* 16-bit depth buffer functions
249 */
250 #define WRITE_DEPTH( _x, _y, d ) \
251 *(GLushort *)(buf + (_x + xo)*2 + (_y + yo)*pitch ) = d;
252
253 #define READ_DEPTH( d, _x, _y ) \
254 d = *(GLushort *)(buf + (_x + xo)*2 + (_y + yo)*pitch );
255
256 #define TAG(x) radeon##x##_16_LINEAR
257 #include "depthtmp.h"
258
259 /* 24 bit depth, 8 bit stencil depthbuffer functions
260 */
261 #define WRITE_DEPTH( _x, _y, d ) \
262 do { \
263 GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \
264 GLuint tmp = *(GLuint *)(buf + offset); \
265 tmp &= 0xff000000; \
266 tmp |= ((d) & 0x00ffffff); \
267 *(GLuint *)(buf + offset) = tmp; \
268 } while (0)
269
270 #define READ_DEPTH( d, _x, _y ) \
271 d = *(GLuint *)(buf + (_x + xo)*4 + (_y + yo)*pitch) & 0x00ffffff;
272
273 #define TAG(x) radeon##x##_24_8_LINEAR
274 #include "depthtmp.h"
275
276 /* ================================================================
277 * Stencil buffer
278 */
279
280 /* 24 bit depth, 8 bit stencil depthbuffer functions
281 */
282 #define WRITE_STENCIL( _x, _y, d ) \
283 do { \
284 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
285 GLuint tmp = *(GLuint *)(buf + offset); \
286 tmp &= 0x00ffffff; \
287 tmp |= (((d) & 0xff) << 24); \
288 *(GLuint *)(buf + offset) = tmp; \
289 } while (0)
290
291 #define READ_STENCIL( d, _x, _y ) \
292 do { \
293 GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo ); \
294 GLuint tmp = *(GLuint *)(buf + offset); \
295 tmp &= 0xff000000; \
296 d = tmp >> 24; \
297 } while (0)
298
299 #define TAG(x) radeon##x##_24_8_TILE
300 #include "stenciltmp.h"
301
302 /* 24 bit depth, 8 bit stencil depthbuffer functions
303 */
304 #define WRITE_STENCIL( _x, _y, d ) \
305 do { \
306 GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \
307 GLuint tmp = *(GLuint *)(buf + offset); \
308 tmp &= 0x00ffffff; \
309 tmp |= (((d) & 0xff) << 24); \
310 *(GLuint *)(buf + offset) = tmp; \
311 } while (0)
312
313 #define READ_STENCIL( d, _x, _y ) \
314 do { \
315 GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \
316 GLuint tmp = *(GLuint *)(buf + offset); \
317 tmp &= 0xff000000; \
318 d = tmp >> 24; \
319 } while (0)
320
321 #define TAG(x) radeon##x##_24_8_LINEAR
322 #include "stenciltmp.h"
323
324 /*
325 * This function is called to specify which buffer to read and write
326 * for software rasterization (swrast) fallbacks. This doesn't necessarily
327 * correspond to glDrawBuffer() or glReadBuffer() calls.
328 */
329 static void radeonSetBuffer(GLcontext * ctx,
330 GLframebuffer * colorBuffer, GLuint bufferBit)
331 {
332 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
333
334 switch (bufferBit) {
335 case DD_FRONT_LEFT_BIT:
336 if (radeon->doPageFlip && radeon->sarea->pfCurrentPage == 1) {
337 radeon->state.pixel.readOffset =
338 radeon->radeonScreen->backOffset;
339 radeon->state.pixel.readPitch =
340 radeon->radeonScreen->backPitch;
341 radeon->state.color.drawOffset =
342 radeon->radeonScreen->backOffset;
343 radeon->state.color.drawPitch =
344 radeon->radeonScreen->backPitch;
345 } else {
346 radeon->state.pixel.readOffset =
347 radeon->radeonScreen->frontOffset;
348 radeon->state.pixel.readPitch =
349 radeon->radeonScreen->frontPitch;
350 radeon->state.color.drawOffset =
351 radeon->radeonScreen->frontOffset;
352 radeon->state.color.drawPitch =
353 radeon->radeonScreen->frontPitch;
354 }
355 break;
356 case DD_BACK_LEFT_BIT:
357 if (radeon->doPageFlip && radeon->sarea->pfCurrentPage == 1) {
358 radeon->state.pixel.readOffset =
359 radeon->radeonScreen->frontOffset;
360 radeon->state.pixel.readPitch =
361 radeon->radeonScreen->frontPitch;
362 radeon->state.color.drawOffset =
363 radeon->radeonScreen->frontOffset;
364 radeon->state.color.drawPitch =
365 radeon->radeonScreen->frontPitch;
366 } else {
367 radeon->state.pixel.readOffset =
368 radeon->radeonScreen->backOffset;
369 radeon->state.pixel.readPitch =
370 radeon->radeonScreen->backPitch;
371 radeon->state.color.drawOffset =
372 radeon->radeonScreen->backOffset;
373 radeon->state.color.drawPitch =
374 radeon->radeonScreen->backPitch;
375 }
376 break;
377 default:
378 _mesa_problem(ctx, "Bad bufferBit in %s", __FUNCTION__);
379 break;
380 }
381 }
382
383 /* Move locking out to get reasonable span performance (10x better
384 * than doing this in HW_LOCK above). WaitForIdle() is the main
385 * culprit.
386 */
387
388 static void radeonSpanRenderStart(GLcontext * ctx)
389 {
390 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
391
392 if (IS_FAMILY_R200(radeon))
393 R200_FIREVERTICES((r200ContextPtr)radeon);
394 else
395 r300Flush(ctx);
396
397 LOCK_HARDWARE(radeon);
398 radeonWaitForIdleLocked(radeon);
399
400 /* Read & rewrite the first pixel in the frame buffer. This should
401 * be a noop, right? In fact without this conform fails as reading
402 * from the framebuffer sometimes produces old results -- the
403 * on-card read cache gets mixed up and doesn't notice that the
404 * framebuffer has been updated.
405 *
406 * In the worst case this is buggy too as p might get the wrong
407 * value first time, so really need a hidden pixel somewhere for this.
408 */
409 {
410 int p;
411 volatile int *read_buf =
412 (volatile int *)(radeon->dri.screen->pFB +
413 radeon->state.pixel.readOffset);
414 p = *read_buf;
415 *read_buf = p;
416 }
417 }
418
419 static void radeonSpanRenderFinish(GLcontext * ctx)
420 {
421 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
422
423 _swrast_flush(ctx);
424 UNLOCK_HARDWARE(radeon);
425 }
426
427 void radeonInitSpanFuncs(GLcontext * ctx)
428 {
429 r200ContextPtr rmesa = R200_CONTEXT(ctx);
430 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
431 struct swrast_device_driver *swdd =
432 _swrast_GetDeviceDriverReference(ctx);
433
434 swdd->SetBuffer = radeonSetBuffer;
435
436 switch (radeon->radeonScreen->cpp) {
437 case 2:
438 swdd->WriteRGBASpan = radeonWriteRGBASpan_RGB565;
439 swdd->WriteRGBSpan = radeonWriteRGBSpan_RGB565;
440 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_RGB565;
441 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_RGB565;
442 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_RGB565;
443 swdd->ReadRGBASpan = radeonReadRGBASpan_RGB565;
444 swdd->ReadRGBAPixels = radeonReadRGBAPixels_RGB565;
445 break;
446
447 case 4:
448 swdd->WriteRGBASpan = radeonWriteRGBASpan_ARGB8888;
449 swdd->WriteRGBSpan = radeonWriteRGBSpan_ARGB8888;
450 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_ARGB8888;
451 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_ARGB8888;
452 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_ARGB8888;
453 swdd->ReadRGBASpan = radeonReadRGBASpan_ARGB8888;
454 swdd->ReadRGBAPixels = radeonReadRGBAPixels_ARGB8888;
455 break;
456
457 default:
458 break;
459 }
460
461 if (IS_FAMILY_R300(radeon))
462 {
463 switch (radeon->glCtx->Visual.depthBits) {
464 case 16:
465 swdd->ReadDepthSpan = radeonReadDepthSpan_16_LINEAR;
466 swdd->WriteDepthSpan = radeonWriteDepthSpan_16_LINEAR;
467 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_LINEAR;
468 swdd->ReadDepthPixels = radeonReadDepthPixels_16_LINEAR;
469 swdd->WriteDepthPixels = radeonWriteDepthPixels_16_LINEAR;
470 break;
471
472 case 24:
473 swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_LINEAR;
474 swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_LINEAR;
475 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_LINEAR;
476 swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_LINEAR;
477 swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_LINEAR;
478
479 swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_LINEAR;
480 swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_LINEAR;
481 swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_LINEAR;
482 swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_LINEAR;
483 break;
484
485 default:
486 break;
487 }
488 }
489 else
490 {
491 switch (radeon->glCtx->Visual.depthBits) {
492 case 16:
493 swdd->ReadDepthSpan = radeonReadDepthSpan_16_TILE;
494 swdd->WriteDepthSpan = radeonWriteDepthSpan_16_TILE;
495 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_TILE;
496 swdd->ReadDepthPixels = radeonReadDepthPixels_16_TILE;
497 swdd->WriteDepthPixels = radeonWriteDepthPixels_16_TILE;
498 break;
499
500 case 24:
501 swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_TILE;
502 swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_TILE;
503 swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_TILE;
504 swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_TILE;
505 swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_TILE;
506
507 swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_TILE;
508 swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_TILE;
509 swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_TILE;
510 swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_TILE;
511 break;
512
513 default:
514 break;
515 }
516 }
517
518 swdd->SpanRenderStart = radeonSpanRenderStart;
519 swdd->SpanRenderFinish = radeonSpanRenderFinish;
520 }