src/mesa/drivers/dri/r300/radeon_span.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "glheader.h"
  36 #include "imports.h"
  37 #include "swrast/swrast.h"
  38 #include "colormac.h"
  39
  40 #include "r200_context.h"
  41 #include "radeon_ioctl.h"
  42 #include "r300_ioctl.h"
  43 #include "radeon_span.h"
  44
  45 #define DBG 0
  46
  47 #define LOCAL_VARS                                                      \
  48    radeonContextPtr radeon = RADEON_CONTEXT(ctx);                       \
  49    radeonScreenPtr radeonScreen = radeon->radeonScreen;                 \
  50    __DRIscreenPrivate *sPriv = radeon->dri.screen;                      \
  51    __DRIdrawablePrivate *dPriv = radeon->dri.drawable;                  \
  52    GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp;         \
  53    GLuint height = dPriv->h;                                            \
  54    char *buf = (char *)(sPriv->pFB +                                    \
  55                         radeon->state.color.drawOffset +                \
  56                         (dPriv->x * radeonScreen->cpp) +                \
  57                         (dPriv->y * pitch));                            \
  58    char *read_buf = (char *)(sPriv->pFB +                               \
  59                              radeon->state.pixel.readOffset +           \
  60                              (dPriv->x * radeonScreen->cpp) +           \
  61                              (dPriv->y * pitch));                       \
  62    GLuint p;                                                            \
  63    (void) read_buf; (void) buf; (void) p
  64
  65 #define LOCAL_DEPTH_VARS                                                \
  66    radeonContextPtr radeon = RADEON_CONTEXT(ctx);                       \
  67    radeonScreenPtr radeonScreen = radeon->radeonScreen;                 \
  68    __DRIscreenPrivate *sPriv = radeon->dri.screen;                      \
  69    __DRIdrawablePrivate *dPriv = radeon->dri.drawable;                  \
  70    GLuint height = dPriv->h;                                            \
  71    GLuint xo = dPriv->x;                                                \
  72    GLuint yo = dPriv->y;                                                \
  73    char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset);        \
  74    GLuint pitch = radeonScreen->depthPitch;                             \
  75    (void) buf; (void) pitch
  76
  77 #define LOCAL_STENCIL_VARS      LOCAL_DEPTH_VARS
  78
  79 #define CLIPPIXEL( _x, _y )                                             \
  80    ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
  81
  82 #define CLIPSPAN( _x, _y, _n, _x1, _n1, _i )                            \
  83    if ( _y < miny || _y >= maxy ) {                                     \
  84       _n1 = 0, _x1 = x;                                                 \
  85    } else {                                                             \
  86       _n1 = _n;                                                         \
  87       _x1 = _x;                                                         \
  88       if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
  89       if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx);                 \
  90    }
  91
  92 #define Y_FLIP( _y )            (height - _y - 1)
  93
  94 #define HW_LOCK()
  95
  96 #define HW_CLIPLOOP()                                                   \
  97    do {                                                                 \
  98       __DRIdrawablePrivate *dPriv = radeon->dri.drawable;               \
  99       int _nc = dPriv->numClipRects;                                    \
 100                                                                         \
 101       while ( _nc-- ) {                                                 \
 102          int minx = dPriv->pClipRects[_nc].x1 - dPriv->x;               \
 103          int miny = dPriv->pClipRects[_nc].y1 - dPriv->y;               \
 104          int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x;               \
 105          int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
 106
 107 #define HW_ENDCLIPLOOP()                                                \
 108       }                                                                 \
 109    } while (0)
 110
 111 #define HW_UNLOCK()
 112
 113 /* ================================================================
 114  * Color buffer
 115  */
 116
 117 /* 16 bit, RGB565 color spanline and pixel functions
 118  */
 119 #define INIT_MONO_PIXEL(p, color) \
 120   p = PACK_COLOR_565( color[0], color[1], color[2] )
 121
 122 #define WRITE_RGBA( _x, _y, r, g, b, a )                                \
 123    *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) |     \
 124                                            (((int)g & 0xfc) << 3) |     \
 125                                            (((int)b & 0xf8) >> 3))
 126
 127 #define WRITE_PIXEL( _x, _y, p )                                        \
 128    *(GLushort *)(buf + _x*2 + _y*pitch) = p
 129
 130 #define READ_RGBA( rgba, _x, _y )                                       \
 131    do {                                                                 \
 132       GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch);           \
 133       rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8;                         \
 134       rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc;                         \
 135       rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8;                         \
 136       rgba[3] = 0xff;                                                   \
 137    } while (0)
 138
 139 #define TAG(x) radeon##x##_RGB565
 140 #include "spantmp.h"
 141
 142 /* 32 bit, ARGB8888 color spanline and pixel functions
 143  */
 144 #undef INIT_MONO_PIXEL
 145 #define INIT_MONO_PIXEL(p, color) \
 146   p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
 147
 148 #define WRITE_RGBA( _x, _y, r, g, b, a )                        \
 149 do {                                                            \
 150    *(GLuint *)(buf + _x*4 + _y*pitch) = ((b <<  0) |            \
 151                                          (g <<  8) |            \
 152                                          (r << 16) |            \
 153                                          (a << 24) );           \
 154 } while (0)
 155
 156 #define WRITE_PIXEL( _x, _y, p )                        \
 157 do {                                                    \
 158    *(GLuint *)(buf + _x*4 + _y*pitch) = p;              \
 159 } while (0)
 160
 161 #define READ_RGBA( rgba, _x, _y )                               \
 162 do {                                                            \
 163    volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
 164    GLuint p = *ptr;                                     \
 165    rgba[0] = (p >> 16) & 0xff;                                  \
 166    rgba[1] = (p >>  8) & 0xff;                                  \
 167    rgba[2] = (p >>  0) & 0xff;                                  \
 168    rgba[3] = (p >> 24) & 0xff;                                  \
 169 } while (0)
 170
 171 #define TAG(x) radeon##x##_ARGB8888
 172 #include "spantmp.h"
 173
 174 /* ================================================================
 175  * Depth buffer
 176  */
 177
 178 /* The Radeon family has depth tiling on all the time, so we have to convert
 179  * the x,y coordinates into the memory bus address (mba) in the same
 180  * manner as the engine.  In each case, the linear block address (ba)
 181  * is calculated, and then wired with x and y to produce the final
 182  * memory address.
 183  */
 184
 185 #define BIT(x,b) ((x & (1<<b))>>b)
 186 static GLuint radeon_mba_z32(radeonContextPtr radeon, GLint x, GLint y)
 187 {
 188         GLuint pitch = radeon->radeonScreen->depthPitch;
 189         GLuint b =
 190             ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x3FF) >> 5);
 191         GLuint a =
 192             (BIT(x, 0) << 2) | (BIT(y, 0) << 3) | (BIT(x, 1) << 4) | (BIT(y, 1)
 193                                                                       << 5) |
 194             (BIT(x, 3) << 6) | (BIT(x, 4) << 7) | (BIT(x, 2) << 8) | (BIT(y, 2)
 195                                                                       << 9) |
 196             (BIT(y, 3) << 10) |
 197             (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
 198             ((b >> 1) << 12);
 199         return a;
 200 }
 201
 202 static GLuint radeon_mba_z16(radeonContextPtr radeon, GLint x, GLint y)
 203 {
 204         GLuint pitch = radeon->radeonScreen->depthPitch;
 205         GLuint b =
 206             ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x3FF) >> 6);
 207         GLuint a =
 208             (BIT(x, 0) << 1) | (BIT(y, 0) << 2) | (BIT(x, 1) << 3) | (BIT(y, 1)
 209                                                                       << 4) |
 210             (BIT(x, 2) << 5) | (BIT(x, 4) << 6) | (BIT(x, 5) << 7) | (BIT(x, 3)
 211                                                                       << 8) |
 212             (BIT(y, 2) << 9) | (BIT(y, 3) << 10) |
 213             (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y, 4)))) << 11) |
 214             ((b >> 1) << 12);
 215         return a;
 216 }
 217
 218
 219 /* 16-bit depth buffer functions
 220  */
 221 #define WRITE_DEPTH( _x, _y, d )                                        \
 222    *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo )) = d;
 223
 224 #define READ_DEPTH( d, _x, _y )                                         \
 225    d = *(GLushort *)(buf + radeon_mba_z16( radeon, _x + xo, _y + yo ));
 226
 227 #define TAG(x) radeon##x##_16_TILE
 228 #include "depthtmp.h"
 229
 230 /* 24 bit depth, 8 bit stencil depthbuffer functions
 231  */
 232 #define WRITE_DEPTH( _x, _y, d )                                        \
 233 do {                                                                    \
 234    GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo );          \
 235    GLuint tmp = *(GLuint *)(buf + offset);                              \
 236    tmp &= 0xff000000;                                                   \
 237    tmp |= ((d) & 0x00ffffff);                                           \
 238    *(GLuint *)(buf + offset) = tmp;                                     \
 239 } while (0)
 240
 241 #define READ_DEPTH( d, _x, _y )                                         \
 242    d = *(GLuint *)(buf + radeon_mba_z32( radeon, _x + xo,               \
 243                                          _y + yo )) & 0x00ffffff;
 244
 245 #define TAG(x) radeon##x##_24_8_TILE
 246 #include "depthtmp.h"
 247
 248 /* 16-bit depth buffer functions
 249  */
 250 #define WRITE_DEPTH( _x, _y, d )                                        \
 251    *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 ) = d;
 252
 253 #define READ_DEPTH( d, _x, _y )                                         \
 254    d = *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 );
 255
 256 #define TAG(x) radeon##x##_16_LINEAR
 257 #include "depthtmp.h"
 258
 259 /* 24 bit depth, 8 bit stencil depthbuffer functions
 260  *
 261  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 262  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 263  */
 264 #define WRITE_DEPTH( _x, _y, d )                                        \
 265 do {                                                                    \
 266    GLuint offset = (_x + xo + (_y + yo)*pitch)*4;                       \
 267    GLuint tmp = *(GLuint *)(buf + offset);                              \
 268    tmp &= 0x000000ff;                                                   \
 269    tmp |= ((d << 8) & 0xffffff00);                                      \
 270    *(GLuint *)(buf + offset) = tmp;                                     \
 271 } while (0)
 272
 273 #define READ_DEPTH( d, _x, _y )                                         \
 274    d = (*(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0xffffff00) >> 8;
 275
 276 #define TAG(x) radeon##x##_24_8_LINEAR
 277 #include "depthtmp.h"
 278
 279 /* ================================================================
 280  * Stencil buffer
 281  */
 282
 283 /* 24 bit depth, 8 bit stencil depthbuffer functions
 284  */
 285 #define WRITE_STENCIL( _x, _y, d )                                      \
 286 do {                                                                    \
 287    GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo );          \
 288    GLuint tmp = *(GLuint *)(buf + offset);                              \
 289    tmp &= 0x00ffffff;                                                   \
 290    tmp |= (((d) & 0xff) << 24);                                         \
 291    *(GLuint *)(buf + offset) = tmp;                                     \
 292 } while (0)
 293
 294 #define READ_STENCIL( d, _x, _y )                                       \
 295 do {                                                                    \
 296    GLuint offset = radeon_mba_z32( radeon, _x + xo, _y + yo );          \
 297    GLuint tmp = *(GLuint *)(buf + offset);                              \
 298    tmp &= 0xff000000;                                                   \
 299    d = tmp >> 24;                                                       \
 300 } while (0)
 301
 302 #define TAG(x) radeon##x##_24_8_TILE
 303 #include "stenciltmp.h"
 304
 305 /* 24 bit depth, 8 bit stencil depthbuffer functions
 306  */
 307 #define WRITE_STENCIL( _x, _y, d )                                      \
 308 do {                                                                    \
 309    GLuint offset = (_x + xo)*4 + (_y + yo)*pitch;                       \
 310    GLuint tmp = *(GLuint *)(buf + offset);                              \
 311    tmp &= 0x00ffffff;                                                   \
 312    tmp |= (((d) & 0xff) << 24);                                         \
 313    *(GLuint *)(buf + offset) = tmp;                                     \
 314 } while (0)
 315
 316 #define READ_STENCIL( d, _x, _y )                                       \
 317 do {                                                                    \
 318    GLuint offset = (_x + xo)*4 + (_y + yo)*pitch;                       \
 319    GLuint tmp = *(GLuint *)(buf + offset);                              \
 320    tmp &= 0xff000000;                                                   \
 321    d = tmp >> 24;                                                       \
 322 } while (0)
 323
 324 #define TAG(x) radeon##x##_24_8_LINEAR
 325 #include "stenciltmp.h"
 326
 327 /*
 328  * This function is called to specify which buffer to read and write
 329  * for software rasterization (swrast) fallbacks.  This doesn't necessarily
 330  * correspond to glDrawBuffer() or glReadBuffer() calls.
 331  */
 332 static void radeonSetBuffer(GLcontext * ctx,
 333                           GLframebuffer * colorBuffer, GLuint bufferBit)
 334 {
 335         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 336         int buffer;
 337
 338         switch (bufferBit) {
 339         case DD_FRONT_LEFT_BIT:
 340                 buffer = 0;
 341                 break;
 342
 343         case DD_BACK_LEFT_BIT:
 344                 buffer = 1;
 345                 break;
 346
 347         default:
 348                 _mesa_problem(ctx, "Bad bufferBit in %s", __FUNCTION__);
 349                 return;
 350         }
 351
 352         if (radeon->doPageFlip && radeon->sarea->pfCurrentPage == 1)
 353                 buffer ^= 1;
 354
 355 #if 0
 356         fprintf(stderr, "%s: using %s buffer\n", __FUNCTION__,
 357                 buffer ? "back" : "front");
 358 #endif
 359
 360         if (buffer) {
 361                 radeon->state.pixel.readOffset =
 362                         radeon->radeonScreen->backOffset;
 363                 radeon->state.pixel.readPitch =
 364                         radeon->radeonScreen->backPitch;
 365                 radeon->state.color.drawOffset =
 366                         radeon->radeonScreen->backOffset;
 367                 radeon->state.color.drawPitch =
 368                         radeon->radeonScreen->backPitch;
 369         } else {
 370                 radeon->state.pixel.readOffset =
 371                         radeon->radeonScreen->frontOffset;
 372                 radeon->state.pixel.readPitch =
 373                         radeon->radeonScreen->frontPitch;
 374                 radeon->state.color.drawOffset =
 375                         radeon->radeonScreen->frontOffset;
 376                 radeon->state.color.drawPitch =
 377                         radeon->radeonScreen->frontPitch;
 378         }
 379 }
 380
 381 /* Move locking out to get reasonable span performance (10x better
 382  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 383  * culprit.
 384  */
 385
 386 static void radeonSpanRenderStart(GLcontext * ctx)
 387 {
 388         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 389
 390         if (IS_FAMILY_R200(radeon))
 391                 R200_FIREVERTICES((r200ContextPtr)radeon);
 392         else
 393                 r300Flush(ctx);
 394
 395         LOCK_HARDWARE(radeon);
 396         radeonWaitForIdleLocked(radeon);
 397
 398         /* Read & rewrite the first pixel in the frame buffer.  This should
 399          * be a noop, right?  In fact without this conform fails as reading
 400          * from the framebuffer sometimes produces old results -- the
 401          * on-card read cache gets mixed up and doesn't notice that the
 402          * framebuffer has been updated.
 403          *
 404          * In the worst case this is buggy too as p might get the wrong
 405          * value first time, so really need a hidden pixel somewhere for this.
 406          */
 407         {
 408                 int p;
 409                 volatile int *read_buf =
 410                     (volatile int *)(radeon->dri.screen->pFB +
 411                                      radeon->state.pixel.readOffset);
 412                 p = *read_buf;
 413                 *read_buf = p;
 414         }
 415 }
 416
 417 static void radeonSpanRenderFinish(GLcontext * ctx)
 418 {
 419         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 420
 421         _swrast_flush(ctx);
 422         UNLOCK_HARDWARE(radeon);
 423 }
 424
 425 void radeonInitSpanFuncs(GLcontext * ctx)
 426 {
 427         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 428         struct swrast_device_driver *swdd =
 429             _swrast_GetDeviceDriverReference(ctx);
 430
 431         swdd->SetBuffer = radeonSetBuffer;
 432
 433         switch (radeon->radeonScreen->cpp) {
 434         case 2:
 435                 swdd->WriteRGBASpan = radeonWriteRGBASpan_RGB565;
 436                 swdd->WriteRGBSpan = radeonWriteRGBSpan_RGB565;
 437                 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_RGB565;
 438                 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_RGB565;
 439                 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_RGB565;
 440                 swdd->ReadRGBASpan = radeonReadRGBASpan_RGB565;
 441                 swdd->ReadRGBAPixels = radeonReadRGBAPixels_RGB565;
 442                 break;
 443
 444         case 4:
 445                 swdd->WriteRGBASpan = radeonWriteRGBASpan_ARGB8888;
 446                 swdd->WriteRGBSpan = radeonWriteRGBSpan_ARGB8888;
 447                 swdd->WriteMonoRGBASpan = radeonWriteMonoRGBASpan_ARGB8888;
 448                 swdd->WriteRGBAPixels = radeonWriteRGBAPixels_ARGB8888;
 449                 swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_ARGB8888;
 450                 swdd->ReadRGBASpan = radeonReadRGBASpan_ARGB8888;
 451                 swdd->ReadRGBAPixels = radeonReadRGBAPixels_ARGB8888;
 452                 break;
 453
 454         default:
 455                 break;
 456         }
 457
 458         if (IS_FAMILY_R300(radeon))
 459         {
 460                 switch (radeon->glCtx->Visual.depthBits) {
 461                 case 16:
 462                         swdd->ReadDepthSpan = radeonReadDepthSpan_16_LINEAR;
 463                         swdd->WriteDepthSpan = radeonWriteDepthSpan_16_LINEAR;
 464                         swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_LINEAR;
 465                         swdd->ReadDepthPixels = radeonReadDepthPixels_16_LINEAR;
 466                         swdd->WriteDepthPixels = radeonWriteDepthPixels_16_LINEAR;
 467                         break;
 468
 469                 case 24:
 470                         swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_LINEAR;
 471                         swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_LINEAR;
 472                         swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_LINEAR;
 473                         swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_LINEAR;
 474                         swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_LINEAR;
 475
 476                         swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_LINEAR;
 477                         swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_LINEAR;
 478                         swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_LINEAR;
 479                         swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_LINEAR;
 480                         break;
 481
 482                 default:
 483                         break;
 484                 }
 485         }
 486         else
 487         {
 488                 switch (radeon->glCtx->Visual.depthBits) {
 489                 case 16:
 490                         swdd->ReadDepthSpan = radeonReadDepthSpan_16_TILE;
 491                         swdd->WriteDepthSpan = radeonWriteDepthSpan_16_TILE;
 492                         swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_16_TILE;
 493                         swdd->ReadDepthPixels = radeonReadDepthPixels_16_TILE;
 494                         swdd->WriteDepthPixels = radeonWriteDepthPixels_16_TILE;
 495                         break;
 496
 497                 case 24:
 498                         swdd->ReadDepthSpan = radeonReadDepthSpan_24_8_TILE;
 499                         swdd->WriteDepthSpan = radeonWriteDepthSpan_24_8_TILE;
 500                         swdd->WriteMonoDepthSpan = radeonWriteMonoDepthSpan_24_8_TILE;
 501                         swdd->ReadDepthPixels = radeonReadDepthPixels_24_8_TILE;
 502                         swdd->WriteDepthPixels = radeonWriteDepthPixels_24_8_TILE;
 503
 504                         swdd->ReadStencilSpan = radeonReadStencilSpan_24_8_TILE;
 505                         swdd->WriteStencilSpan = radeonWriteStencilSpan_24_8_TILE;
 506                         swdd->ReadStencilPixels = radeonReadStencilPixels_24_8_TILE;
 507                         swdd->WriteStencilPixels = radeonWriteStencilPixels_24_8_TILE;
 508                         break;
 509
 510                 default:
 511                         break;
 512                 }
 513         }
 514
 515         swdd->SpanRenderStart = radeonSpanRenderStart;
 516         swdd->SpanRenderFinish = radeonSpanRenderFinish;
 517 }