src/mesa/drivers/dri/r300/radeon_span.c

   1 /**************************************************************************
   2
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 The Weather Channel (TM) funded Tungsten Graphics to develop the
   8 initial release of the Radeon 8500 driver under the XFree86 license.
   9 This notice must be preserved.
  10
  11 All Rights Reserved.
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32
  33 **************************************************************************/
  34
  35 /*
  36  * Authors:
  37  *   Kevin E. Martin <martin@valinux.com>
  38  *   Gareth Hughes <gareth@valinux.com>
  39  *   Keith Whitwell <keith@tungstengraphics.com>
  40  *
  41  */
  42 #include <unistd.h>
  43 #include "glheader.h"
  44 #include "imports.h"
  45 #include "swrast/swrast.h"
  46
  47 #include "r300_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "r300_ioctl.h"
  50 #include "radeon_span.h"
  51
  52 #include "drirenderbuffer.h"
  53
  54
  55 #define DBG 0
  56
  57
  58 /*
  59  * Note that all information needed to access pixels in a renderbuffer
  60  * should be obtained through the gl_renderbuffer parameter, not per-context
  61  * information.
  62  */
  63 #define LOCAL_VARS                                              \
  64    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  65    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  66    const GLuint bottom = dPriv->h - 1;                          \
  67    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  68       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  69    GLuint p;                                                    \
  70    (void) p;
  71
  72 #define LOCAL_DEPTH_VARS                                \
  73    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  74    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  75    const GLuint bottom = dPriv->h - 1;                  \
  76    GLuint xo = dPriv->x;                                \
  77    GLuint yo = dPriv->y;                                \
  78    GLubyte *buf = (GLubyte *) drb->Base.Data;
  79
  80 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  81
  82 #define Y_FLIP(Y) (bottom - (Y))
  83
  84 #define HW_LOCK()
  85
  86 #define HW_UNLOCK()
  87
  88
  89
  90 /* ================================================================
  91  * Color buffer
  92  */
  93
  94 /* 16 bit, RGB565 color spanline and pixel functions
  95  */
  96 #define SPANTMP_PIXEL_FMT GL_RGB
  97 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  98
  99 #define TAG(x)    radeon##x##_RGB565
 100 #define TAG2(x,y) radeon##x##_RGB565##y
 101 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
 102 #include "spantmp2.h"
 103
 104
 105 /* 32 bit, ARGB8888 color spanline and pixel functions
 106  */
 107 #define SPANTMP_PIXEL_FMT GL_BGRA
 108 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 109
 110 #define TAG(x)    radeon##x##_ARGB8888
 111 #define TAG2(x,y) radeon##x##_ARGB8888##y
 112 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 113 #include "spantmp2.h"
 114
 115
 116 /* ================================================================
 117  * Depth buffer
 118  */
 119
 120 /* The Radeon family has depth tiling on all the time, so we have to convert
 121  * the x,y coordinates into the memory bus address (mba) in the same
 122  * manner as the engine.  In each case, the linear block address (ba)
 123  * is calculated, and then wired with x and y to produce the final
 124  * memory address.
 125  * The chip will do address translation on its own if the surface registers
 126  * are set up correctly. It is not quite enough to get it working with hyperz
 127  * too...
 128  */
 129
 130 static GLuint
 131 radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
 132 {
 133    GLuint pitch = drb->pitch;
 134    if (1 /*|| drb->depthHasSurface */) {
 135       return 4 * (x + y * pitch);
 136    }
 137    else {
 138       GLuint ba, address = 0;                   /* a[0..1] = 0           */
 139
 140       ba = (y / 8) * (pitch / 8) + (x / 8);
 141
 142       address |= (x & 0x7) << 2;                /* a[2..4] = x[0..2]     */
 143       address |= (y & 0x3) << 5;                /* a[5..6] = y[0..1]     */
 144       address |=
 145          (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;  /* a[7]    = x[4] ^ y[2] */
 146       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 147
 148       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 149       address |=
 150          (((x & 0x8) << 1) ^ (y & 0x10)) << 7;  /* a[11]   = x[3] ^ y[4] */
 151       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 152
 153       return address;
 154    }
 155 }
 156
 157
 158 static INLINE GLuint
 159 radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
 160 {
 161    GLuint pitch = drb->pitch;
 162    if (1 /*|| drb->depthHasSurface */) {
 163       return 2 * (x + y * pitch);
 164    }
 165    else {
 166       GLuint ba, address = 0;                   /* a[0]    = 0           */
 167
 168       ba = (y / 16) * (pitch / 32) + (x / 32);
 169
 170       address |= (x & 0x7) << 1;                /* a[1..3] = x[0..2]     */
 171       address |= (y & 0x7) << 4;                /* a[4..6] = y[0..2]     */
 172       address |= (x & 0x8) << 4;                /* a[7]    = x[3]        */
 173       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 174       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 175       address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11]   = x[4] ^ y[4] */
 176       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 177
 178       return address;
 179    }
 180 }
 181
 182
 183 /* 16-bit depth buffer functions
 184  */
 185 #define WRITE_DEPTH( _x, _y, d )                                        \
 186    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 187
 188 #define READ_DEPTH( d, _x, _y )                                         \
 189    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 190
 191 #define TAG(x) radeon##x##_z16
 192 #include "depthtmp.h"
 193
 194
 195 /* 24 bit depth, 8 bit stencil depthbuffer functions
 196  *
 197  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 198  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 199  */
 200 #define WRITE_DEPTH( _x, _y, d )                                        \
 201 do {                                                                    \
 202    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 203    GLuint tmp = *(GLuint *)(buf + offset);                              \
 204    tmp &= 0x000000ff;                                                   \
 205    tmp |= ((d << 8) & 0xffffff00);                                      \
 206    *(GLuint *)(buf + offset) = tmp;                                     \
 207 } while (0)
 208
 209 #define READ_DEPTH( d, _x, _y )                                         \
 210   do { \
 211     d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                \
 212                                          _y + yo )) & 0xffffff00) >> 8; \
 213   }while(0)
 214
 215 #define TAG(x) radeon##x##_z24_s8
 216 #include "depthtmp.h"
 217
 218
 219 /* ================================================================
 220  * Stencil buffer
 221  */
 222
 223 /* 24 bit depth, 8 bit stencil depthbuffer functions
 224  */
 225 #define WRITE_STENCIL( _x, _y, d )                                      \
 226 do {                                                                    \
 227    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 228    GLuint tmp = *(GLuint *)(buf + offset);                              \
 229    tmp &= 0xffffff00;                                                   \
 230    tmp |= (d) & 0xff;                                                   \
 231    *(GLuint *)(buf + offset) = tmp;                                     \
 232 } while (0)
 233
 234 #define READ_STENCIL( d, _x, _y )                                       \
 235 do {                                                                    \
 236    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 237    GLuint tmp = *(GLuint *)(buf + offset);                              \
 238    d = tmp & 0x000000ff;                                                \
 239 } while (0)
 240
 241 #define TAG(x) radeon##x##_z24_s8
 242 #include "stenciltmp.h"
 243
 244
 245
 246 /* Move locking out to get reasonable span performance (10x better
 247  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 248  * culprit.
 249  */
 250
 251 static void radeonSpanRenderStart( GLcontext *ctx )
 252 {
 253    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 254    {
 255         static int first = 1;
 256         r300ContextPtr r300 = (r300ContextPtr)rmesa;
 257
 258         if (first) {
 259                 r300->span_dlocking = getenv("R300_SPAN_DISABLE_LOCKING") ? 1 : 0;
 260                 if (r300->span_dlocking == 0) {
 261                         fprintf(stderr, "Try R300_SPAN_DISABLE_LOCKING env var if this hangs.\n");
 262                         fflush(stderr);
 263                         sleep(1);
 264                 }
 265                 first = 0;
 266         }
 267
 268         if (r300->span_dlocking) {
 269                 r300Flush(ctx);
 270                 LOCK_HARDWARE( rmesa );
 271                 radeonWaitForIdleLocked( rmesa );
 272                 UNLOCK_HARDWARE( rmesa );
 273
 274                 return;
 275         }
 276    }
 277    //   R300_FIREVERTICES( rmesa );
 278    // old code has flush
 279    r300Flush(ctx);
 280    LOCK_HARDWARE( rmesa );
 281    radeonWaitForIdleLocked( rmesa );
 282 }
 283
 284 static void radeonSpanRenderFinish( GLcontext *ctx )
 285 {
 286    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 287    r300ContextPtr r300 = (r300ContextPtr)rmesa;
 288    _swrast_flush( ctx );
 289    if (r300->span_dlocking == 0)
 290         UNLOCK_HARDWARE( rmesa );
 291 }
 292
 293 void radeonInitSpanFuncs( GLcontext *ctx )
 294 {
 295    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 296    swdd->SpanRenderStart          = radeonSpanRenderStart;
 297    swdd->SpanRenderFinish         = radeonSpanRenderFinish;
 298 }
 299
 300
 301 /**
 302  * Plug in the Get/Put routines for the given driRenderbuffer.
 303  */
 304 void
 305 radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
 306 {
 307    if (drb->Base.InternalFormat == GL_RGBA) {
 308       if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
 309          radeonInitPointers_RGB565(&drb->Base);
 310       }
 311       else {
 312          radeonInitPointers_ARGB8888(&drb->Base);
 313       }
 314    }
 315    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 316       radeonInitDepthPointers_z16(&drb->Base);
 317    }
 318    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 319       radeonInitDepthPointers_z24_s8(&drb->Base);
 320    }
 321    else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 322       radeonInitStencilPointers_z24_s8(&drb->Base);
 323    }
 324 }